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Date: Thu, 2 Aug 2018 07:47:25 +0100
From: Stefan Hajnoczi <stefanha@gmail.com>
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Subject: Re: [Qemu-devel] [PATCH v3 4/7] target/arm: add "cortex-m0" CPU
 model
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To: Peter Maydell <peter.maydell@linaro.org>
Cc: Stefan Hajnoczi <stefanha@redhat.com>, Jim Mussared <jim@groklearning.com>, Steffen =?iso-8859-1?Q?G=F6rtz?= <mail@steffen-goertz.de>, Su Hang <suhang16@mails.ucas.ac.cn>, Liviu Ionescu <ilg@livius.net>, Alistair Francis <alistair@alistair23.me>, QEMU Developers <qemu-devel@nongnu.org>, Subbaraya Sundeep <sundeep.lkml@gmail.com>, Steffen Gortz <qemu.ml@steffen-goertz.de>, qemu-arm <qemu-arm@nongnu.org>, Joel Stanley <joel@jms.id.au>, Julia Suvorova <jusual@mail.ru>


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On Mon, Jul 30, 2018 at 06:52:29PM +0100, Peter Maydell wrote:
> On 25 July 2018 at 09:59, Stefan Hajnoczi <stefanha@redhat.com> wrote:
> > Define a "cortex-m0" ARMv6-M CPU model.
> >
> > Most of the register reset values set by other CPU models are not
> > relevant for the cut-down ARMv6-M architecture.
> >
> > Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
> > ---
> >  target/arm/cpu.c | 11 +++++++++++
> >  1 file changed, 11 insertions(+)
> >
> > diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> > index 3848ef46aa..7e477c0d23 100644
> > --- a/target/arm/cpu.c
> > +++ b/target/arm/cpu.c
> > @@ -1255,6 +1255,15 @@ static void arm11mpcore_initfn(Object *obj)
> >      cpu->reset_auxcr =3D 1;
> >  }
> >
> > +static void cortex_m0_initfn(Object *obj)
> > +{
> > +    ARMCPU *cpu =3D ARM_CPU(obj);
> > +    set_feature(&cpu->env, ARM_FEATURE_V6);
> > +    set_feature(&cpu->env, ARM_FEATURE_M);
> > +
> > +    cpu->midr =3D 0x410cc200;
> > +}
>=20
> We have all the patches for turning off not-v6M bits of
> behaviour either in master or in target-arm.for-3.1 already,
> right?

Yes.  I've sent this series because Julia's work is now in
target-arm.for-3.1.

Stefan

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