From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (146.0.238.70:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 09 Aug 2018 02:58:21 -0000 Received: from mga17.intel.com ([192.55.52.151]) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1fnb9Y-0004Gs-9x for speck@linutronix.de; Thu, 09 Aug 2018 04:58:20 +0200 Date: Wed, 8 Aug 2018 19:57:56 -0700 From: Andi Kleen Subject: [MODERATED] Re: [PATCH] SPTE masking Message-ID: <20180809025756.GD4238@tassilo.jf.intel.com> References: MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: On Wed, Aug 08, 2018 at 04:21:14PM -0700, speck for Jim Mattson wrote: > [PATCH] kvm: x86: Set highest physical address bit in non-present/reserved SPTEs > > Always set the upper-most supported physical address bit to 1 for SPTEs > that are marked as non-present or reserved, to make them unusable for > L1TF attacks from the guest. Currently, this just applies to MMIO SPTEs. L1TF only works for cached memory. Are you concerned about cacheable MMIO? I didn't think it could happen. -Andi