From mboxrd@z Thu Jan 1 00:00:00 1970 From: Aapo Vienamo Subject: Re: [PATCH 5/8] arm64: dts: tegra186: Add SDMMC4 DQS trim value Date: Thu, 9 Aug 2018 15:37:32 +0300 Message-ID: <20180809153732.4c91e425@dhcp-10-21-25-168> References: <1533650404-18125-1-git-send-email-avienamo@nvidia.com> <1533650404-18125-6-git-send-email-avienamo@nvidia.com> <20180809114922.GN21639@ulmo> <20180809150226.64657f56@dhcp-10-21-25-168> <03fc6726-25ff-20de-d271-ebae19b753c7@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <03fc6726-25ff-20de-d271-ebae19b753c7@gmail.com> Sender: linux-kernel-owner@vger.kernel.org To: Peter Geis Cc: Thierry Reding , Ulf Hansson , Rob Herring , Mark Rutland , Jonathan Hunter , Adrian Hunter , Mikko Perttunen , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org List-Id: linux-tegra@vger.kernel.org On Thu, 9 Aug 2018 08:23:16 -0400 Peter Geis wrote: > On 08/09/2018 08:02 AM, Aapo Vienamo wrote: > > On Thu, 9 Aug 2018 13:49:22 +0200 > > Thierry Reding wrote: > > > >> On Tue, Aug 07, 2018 at 05:00:01PM +0300, Aapo Vienamo wrote: > >>> Add the HS400 DQS trim value for Tegra186 SDMMC4. > >>> > >>> Signed-off-by: Aapo Vienamo > >>> --- > >>> arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 + > >>> 1 file changed, 1 insertion(+) > >>> > >>> diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi > >>> index 6e9ef26..9e07bc6 100644 > >>> --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi > >>> +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi > >>> @@ -313,6 +313,7 @@ > >>> nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; > >>> nvidia,default-tap = <0x5>; > >>> nvidia,default-trim = <0x9>; > >>> + nvidia,dqs-trim = <63>; > >>> status = "disabled"; > >>> }; > >>> > >> > >> Isn't this technically dependent on the board layout and as such would > >> belong in the board DTS file? Or does this value work on all existing > >> Tegra186 platforms? > > > > This value is specified as part of the controller initialization > > sequence in the TRM. I've understood that this (and other tap and trim) > > value(s) are used for compensating the propagation delay differences > > that are caused by the internal SoC layout. > > > > -Aapo > > -- > > The Tegra2 and Tegra3 TRMs also specify recommended DQS values, and I am > working on at least one device that differs in the platform data from > the default value. > I see that you mentioned this is for the newer devices that support > HS200/HS400 modes, but does it enable setting DQS on older devices? I can't find any mention of _SDMMC_ DQS trimmer on Tegra2, Tegra3 or Tegra124 TRMs. As far as I can tell, programming the DQS trimmer value is only required by HS400 signaling on Tegra210 and Tegra186. -Aapo From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5927C46470 for ; Thu, 9 Aug 2018 12:37:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7A448208A5 for ; Thu, 9 Aug 2018 12:37:44 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7A448208A5 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732247AbeHIPCY (ORCPT ); Thu, 9 Aug 2018 11:02:24 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:15564 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730506AbeHIPCY (ORCPT ); Thu, 9 Aug 2018 11:02:24 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1, AES128-SHA) id ; Thu, 09 Aug 2018 05:37:28 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 09 Aug 2018 05:37:41 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 09 Aug 2018 05:37:41 -0700 Received: from dhcp-10-21-25-168 (10.21.25.201) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 9 Aug 2018 12:37:38 +0000 Date: Thu, 9 Aug 2018 15:37:32 +0300 From: Aapo Vienamo To: Peter Geis CC: Thierry Reding , Ulf Hansson , Rob Herring , Mark Rutland , Jonathan Hunter , "Adrian Hunter" , Mikko Perttunen , , , , Subject: Re: [PATCH 5/8] arm64: dts: tegra186: Add SDMMC4 DQS trim value Message-ID: <20180809153732.4c91e425@dhcp-10-21-25-168> In-Reply-To: <03fc6726-25ff-20de-d271-ebae19b753c7@gmail.com> References: <1533650404-18125-1-git-send-email-avienamo@nvidia.com> <1533650404-18125-6-git-send-email-avienamo@nvidia.com> <20180809114922.GN21639@ulmo> <20180809150226.64657f56@dhcp-10-21-25-168> <03fc6726-25ff-20de-d271-ebae19b753c7@gmail.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.21.25.201] X-ClientProxiedBy: UKMAIL102.nvidia.com (10.26.138.15) To HQMAIL101.nvidia.com (172.20.187.10) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 9 Aug 2018 08:23:16 -0400 Peter Geis wrote: > On 08/09/2018 08:02 AM, Aapo Vienamo wrote: > > On Thu, 9 Aug 2018 13:49:22 +0200 > > Thierry Reding wrote: > > > >> On Tue, Aug 07, 2018 at 05:00:01PM +0300, Aapo Vienamo wrote: > >>> Add the HS400 DQS trim value for Tegra186 SDMMC4. > >>> > >>> Signed-off-by: Aapo Vienamo > >>> --- > >>> arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 + > >>> 1 file changed, 1 insertion(+) > >>> > >>> diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi > >>> index 6e9ef26..9e07bc6 100644 > >>> --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi > >>> +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi > >>> @@ -313,6 +313,7 @@ > >>> nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; > >>> nvidia,default-tap = <0x5>; > >>> nvidia,default-trim = <0x9>; > >>> + nvidia,dqs-trim = <63>; > >>> status = "disabled"; > >>> }; > >>> > >> > >> Isn't this technically dependent on the board layout and as such would > >> belong in the board DTS file? Or does this value work on all existing > >> Tegra186 platforms? > > > > This value is specified as part of the controller initialization > > sequence in the TRM. I've understood that this (and other tap and trim) > > value(s) are used for compensating the propagation delay differences > > that are caused by the internal SoC layout. > > > > -Aapo > > -- > > The Tegra2 and Tegra3 TRMs also specify recommended DQS values, and I am > working on at least one device that differs in the platform data from > the default value. > I see that you mentioned this is for the newer devices that support > HS200/HS400 modes, but does it enable setting DQS on older devices? I can't find any mention of _SDMMC_ DQS trimmer on Tegra2, Tegra3 or Tegra124 TRMs. As far as I can tell, programming the DQS trimmer value is only required by HS400 signaling on Tegra210 and Tegra186. -Aapo