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From: Eugeniu Rosca <roscaeugeniu@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 03/13] armv8: mmu: Fix signed shift overflow
Date: Mon, 27 Aug 2018 01:13:21 +0200	[thread overview]
Message-ID: <20180826231332.2491-4-erosca@de.adit-jv.com> (raw)
In-Reply-To: <20180826231332.2491-1-erosca@de.adit-jv.com>

Fix the following UBSAN warnings:

------8<-----
CPU: Renesas Electronics R8A7795 rev 2.0
Model: Renesas Salvator-X board based on r8a7795 ES2.0+
 ====================================================================
 UBSAN: Undefined behaviour in arch/arm/cpu/armv8/cache_v8.c:72:9
 left shift of 1 by 31 places cannot be represented in type 'int'
 ====================================================================
 ====================================================================
 UBSAN: Undefined behaviour in arch/arm/cpu/armv8/cache_v8.c:74:9
 left shift of 1 by 31 places cannot be represented in type 'int'
 ====================================================================
------8<-----

Use (1UL << i) instead of BIT() macro for consistency.

Fixes: ad3d6e88a1a4 ("armv8/mmu: Set bits marked RES1 in TCR")
Fixes: 9bb367a590fe ("arm64: Disable TTBR1 maps in EL1")
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
---

Changes in v2:
 - Shorten the summary line
 - Use (1UL << i) instead of BIT() macro for consistency
---
 arch/arm/include/asm/armv8/mmu.h | 42 +++++++++++++++++++++---------------------
 1 file changed, 21 insertions(+), 21 deletions(-)

diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 62d00d15c26d..632d3a442df8 100644
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -78,27 +78,27 @@
  * TCR flags.
  */
 #define TCR_T0SZ(x)		((64 - (x)) << 0)
-#define TCR_IRGN_NC		(0 << 8)
-#define TCR_IRGN_WBWA		(1 << 8)
-#define TCR_IRGN_WT		(2 << 8)
-#define TCR_IRGN_WBNWA		(3 << 8)
-#define TCR_IRGN_MASK		(3 << 8)
-#define TCR_ORGN_NC		(0 << 10)
-#define TCR_ORGN_WBWA		(1 << 10)
-#define TCR_ORGN_WT		(2 << 10)
-#define TCR_ORGN_WBNWA		(3 << 10)
-#define TCR_ORGN_MASK		(3 << 10)
-#define TCR_SHARED_NON		(0 << 12)
-#define TCR_SHARED_OUTER	(2 << 12)
-#define TCR_SHARED_INNER	(3 << 12)
-#define TCR_TG0_4K		(0 << 14)
-#define TCR_TG0_64K		(1 << 14)
-#define TCR_TG0_16K		(2 << 14)
-#define TCR_EPD1_DISABLE	(1 << 23)
-
-#define TCR_EL1_RSVD		(1 << 31)
-#define TCR_EL2_RSVD		(1 << 31 | 1 << 23)
-#define TCR_EL3_RSVD		(1 << 31 | 1 << 23)
+#define TCR_IRGN_NC		(0UL << 8)
+#define TCR_IRGN_WBWA		(1UL << 8)
+#define TCR_IRGN_WT		(2UL << 8)
+#define TCR_IRGN_WBNWA		(3UL << 8)
+#define TCR_IRGN_MASK		(3UL << 8)
+#define TCR_ORGN_NC		(0UL << 10)
+#define TCR_ORGN_WBWA		(1UL << 10)
+#define TCR_ORGN_WT		(2UL << 10)
+#define TCR_ORGN_WBNWA		(3UL << 10)
+#define TCR_ORGN_MASK		(3UL << 10)
+#define TCR_SHARED_NON		(0UL << 12)
+#define TCR_SHARED_OUTER	(2UL << 12)
+#define TCR_SHARED_INNER	(3UL << 12)
+#define TCR_TG0_4K		(0UL << 14)
+#define TCR_TG0_64K		(1UL << 14)
+#define TCR_TG0_16K		(2UL << 14)
+#define TCR_EPD1_DISABLE	(1UL << 23)
+
+#define TCR_EL1_RSVD		(1UL << 31)
+#define TCR_EL2_RSVD		(1UL << 31 | 1UL << 23)
+#define TCR_EL3_RSVD		(1UL << 31 | 1UL << 23)
 
 #ifndef __ASSEMBLY__
 static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)
-- 
2.18.0

  parent reply	other threads:[~2018-08-26 23:13 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-08-26 23:13 [U-Boot] [PATCH v2 00/13] Import Undefined Behavior Sanitizer Eugeniu Rosca
2018-08-26 23:13 ` [U-Boot] [PATCH v2 01/13] UBSAN: run-time undefined behavior sanity checker Eugeniu Rosca
2018-08-27 14:13   ` Tom Rini
2018-08-26 23:13 ` [U-Boot] [PATCH v2 02/13] mmc: Fix signed shift overflow Eugeniu Rosca
2018-08-26 23:13 ` Eugeniu Rosca [this message]
2018-08-27 14:13   ` [U-Boot] [PATCH v2 03/13] armv8: mmu: " Tom Rini
2018-08-26 23:13 ` [U-Boot] [PATCH v2 04/13] pinctrl: renesas: " Eugeniu Rosca
2018-08-26 23:13 ` [U-Boot] [PATCH v2 05/13] net: phy: " Eugeniu Rosca
2018-08-26 23:13 ` [U-Boot] [PATCH v2 06/13] net: ravb: " Eugeniu Rosca
2018-08-26 23:22   ` Marek Vasut
2018-08-27 20:24     ` Eugeniu Rosca
2018-08-27 23:55       ` Marek Vasut
2018-08-26 23:13 ` [U-Boot] [PATCH v2 07/13] x86: Fix signed shift overflow in MSR_IA32_APICBASE_BASE Eugeniu Rosca
2018-08-28  2:05   ` Bin Meng
2018-08-28  6:42     ` Eugeniu Rosca
2018-09-01 10:59       ` Eugeniu Rosca
2018-09-04  4:00         ` Bin Meng
2018-09-16 18:46           ` Eugeniu Rosca
2018-09-22 23:10             ` Eugeniu Rosca
2018-09-25  2:06               ` Bin Meng
2018-10-09  0:22                 ` Eugeniu Rosca
2018-08-28  8:14     ` Andy Shevchenko
2018-08-26 23:13 ` [U-Boot] [PATCH v2 08/13] disk: part_dos: Fix signed shift overflow Eugeniu Rosca
2018-08-26 23:13 ` [U-Boot] [PATCH v2 09/13] common.h: Fix signed shift overflow in cpumask_next() Eugeniu Rosca
2018-08-26 23:13 ` [U-Boot] [PATCH v2 10/13] mmc: Fix read-past-end-of-array Eugeniu Rosca
2018-08-26 23:13 ` [U-Boot] [PATCH v2 11/13] hashtable: Fix zero-sized array Eugeniu Rosca
2018-08-27 14:13   ` Tom Rini
2018-08-26 23:13 ` [U-Boot] [PATCH v2 12/13] input: " Eugeniu Rosca
2018-08-27 14:13   ` Tom Rini
2018-08-26 23:13 ` [U-Boot] [PATCH v2 13/13] configs: sandbox*: Enable UBSAN Eugeniu Rosca
2018-08-30  2:51   ` Simon Glass
2018-09-17 21:10     ` Eugeniu Rosca

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