From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14E38C433F5 for ; Mon, 27 Aug 2018 18:57:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B1296208E2 for ; Mon, 27 Aug 2018 18:57:13 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B1296208E2 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727563AbeH0WpA (ORCPT ); Mon, 27 Aug 2018 18:45:00 -0400 Received: from mga05.intel.com ([192.55.52.43]:56507 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727058AbeH0WpA (ORCPT ); Mon, 27 Aug 2018 18:45:00 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Aug 2018 11:57:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,296,1531810800"; d="scan'208";a="69524583" Received: from nitikasi-mobl.ger.corp.intel.com (HELO localhost) ([10.249.36.186]) by orsmga006.jf.intel.com with ESMTP; 27 Aug 2018 11:56:43 -0700 From: Jarkko Sakkinen To: x86@kernel.org, platform-driver-x86@vger.kernel.org Cc: dave.hansen@intel.com, sean.j.christopherson@intel.com, nhorman@redhat.com, npmccallum@redhat.com, linux-sgx@vger.kernel.org, Suresh Siddha , Jarkko Sakkinen , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , Serge Ayoun , "Rafael J. Wysocki" , Borislav Petkov , Reinette Chatre , Andi Kleen , Greg Kroah-Hartman , "Kirill A. Shutemov" , linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)) Subject: [PATCH v13 06/13] x86/sgx: Detect Intel SGX Date: Mon, 27 Aug 2018 21:53:27 +0300 Message-Id: <20180827185507.17087-7-jarkko.sakkinen@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180827185507.17087-1-jarkko.sakkinen@linux.intel.com> References: <20180827185507.17087-1-jarkko.sakkinen@linux.intel.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sean Christopherson Intel(R) SGX is a set of CPU instructions that can be used by applications to set aside private regions of code and data. The code outside the enclave is disallowed to access the memory inside the enclave by the CPU access control. Add a check for SGX to arch/x86 and a new config option, INTEL_SGX_CORE. Expose a boolean variable 'sgx_enabled' to query whether or not the SGX support is available. Signed-off-by: Sean Christopherson Co-developed-by: Jarkko Sakkinen Co-developed-by: Suresh Siddha Signed-off-by: Suresh Siddha Signed-off-by: Jarkko Sakkinen --- arch/x86/Kconfig | 19 +++++++++++++ arch/x86/include/asm/sgx.h | 12 +++++++++ arch/x86/include/asm/sgx_pr.h | 13 +++++++++ arch/x86/kernel/cpu/Makefile | 1 + arch/x86/kernel/cpu/intel_sgx.c | 47 +++++++++++++++++++++++++++++++++ 5 files changed, 92 insertions(+) create mode 100644 arch/x86/include/asm/sgx.h create mode 100644 arch/x86/include/asm/sgx_pr.h create mode 100644 arch/x86/kernel/cpu/intel_sgx.c diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index b0312f8947ce..3c7571422a07 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1911,6 +1911,25 @@ config X86_INTEL_MEMORY_PROTECTION_KEYS If unsure, say y. +config INTEL_SGX_CORE + prompt "Intel SGX core functionality" + def_bool n + depends on X86_64 && CPU_SUP_INTEL + help + Intel Software Guard eXtensions (SGX) is a set of CPU instructions + that allows ring 3 applications to create enclaves, private regions + of memory that are protected, by hardware, from unauthorized access + and/or modification. + + This option enables kernel recognition of SGX, high-level management + of the Enclave Page Cache (EPC), tracking and writing of SGX Launch + Enclave Hash MSRs, and allows for virtualization of SGX via KVM. By + iteslf, this option does not provide SGX support to userspace. + + For details, see Documentation/x86/intel_sgx.rst + + If unsure, say N. + config EFI bool "EFI runtime service support" depends on ACPI diff --git a/arch/x86/include/asm/sgx.h b/arch/x86/include/asm/sgx.h new file mode 100644 index 000000000000..2130e639ab49 --- /dev/null +++ b/arch/x86/include/asm/sgx.h @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +// Copyright(c) 2016-18 Intel Corporation. + +#ifndef _ASM_X86_SGX_H +#define _ASM_X86_SGX_H + +#include + +extern bool sgx_enabled; +extern bool sgx_lc_enabled; + +#endif /* _ASM_X86_SGX_H */ diff --git a/arch/x86/include/asm/sgx_pr.h b/arch/x86/include/asm/sgx_pr.h new file mode 100644 index 000000000000..c68578127620 --- /dev/null +++ b/arch/x86/include/asm/sgx_pr.h @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +// Copyright(c) 2016-17 Intel Corporation. + +#ifndef _ASM_X86_SGX_PR_H +#define _ASM_X86_SGX_PR_H + +#include +#include + +#undef pr_fmt +#define pr_fmt(fmt) "sgx: " fmt + +#endif /* _ASM_X86_SGX_PR_H */ diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile index 347137e80bf5..71876f2b35fc 100644 --- a/arch/x86/kernel/cpu/Makefile +++ b/arch/x86/kernel/cpu/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_CPU_SUP_UMC_32) += umc.o obj-$(CONFIG_INTEL_RDT) += intel_rdt.o intel_rdt_rdtgroup.o intel_rdt_monitor.o obj-$(CONFIG_INTEL_RDT) += intel_rdt_ctrlmondata.o intel_rdt_pseudo_lock.o CFLAGS_intel_rdt_pseudo_lock.o = -I$(src) +obj-$(CONFIG_INTEL_SGX_CORE) += intel_sgx.o obj-$(CONFIG_X86_MCE) += mcheck/ obj-$(CONFIG_MTRR) += mtrr/ diff --git a/arch/x86/kernel/cpu/intel_sgx.c b/arch/x86/kernel/cpu/intel_sgx.c new file mode 100644 index 000000000000..17b46bec9c54 --- /dev/null +++ b/arch/x86/kernel/cpu/intel_sgx.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +// Copyright(c) 2016-17 Intel Corporation. + +#include +#include +#include +#include +#include +#include +#include +#include + +bool sgx_enabled __ro_after_init; +EXPORT_SYMBOL_GPL(sgx_enabled); +bool sgx_lc_enabled __ro_after_init; +EXPORT_SYMBOL_GPL(sgx_lc_enabled); + +static __init int sgx_init(void) +{ + unsigned long fc; + + if (!boot_cpu_has(X86_FEATURE_SGX)) + return false; + + if (!boot_cpu_has(X86_FEATURE_SGX1)) + return false; + + rdmsrl(MSR_IA32_FEATURE_CONTROL, fc); + if (!(fc & FEATURE_CONTROL_LOCKED)) { + pr_info("IA32_FEATURE_CONTROL MSR is not locked\n"); + return false; + } + + if (!(fc & FEATURE_CONTROL_SGX_ENABLE)) { + pr_info("disabled by the firmware\n"); + return false; + } + + if (!(fc & FEATURE_CONTROL_SGX_LE_WR)) + pr_info("IA32_SGXLEPUBKEYHASHn MSRs are not writable\n"); + + sgx_enabled = true; + sgx_lc_enabled = !!(fc & FEATURE_CONTROL_SGX_LE_WR); + return 0; +} + +arch_initcall(sgx_init); -- 2.17.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jarkko Sakkinen To: , CC: , , , , , Suresh Siddha , Jarkko Sakkinen , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , "Serge Ayoun" , "Rafael J. Wysocki" , Borislav Petkov , Reinette Chatre , Andi Kleen , "Greg Kroah-Hartman" , "Kirill A. Shutemov" , "open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)" Subject: [PATCH v13 06/13] x86/sgx: Detect Intel SGX Date: Mon, 27 Aug 2018 21:53:27 +0300 Message-ID: <20180827185507.17087-7-jarkko.sakkinen@linux.intel.com> In-Reply-To: <20180827185507.17087-1-jarkko.sakkinen@linux.intel.com> References: <20180827185507.17087-1-jarkko.sakkinen@linux.intel.com> Content-Type: text/plain Return-Path: jarkko.sakkinen@intel.com MIME-Version: 1.0 List-ID: From: Sean Christopherson Intel(R) SGX is a set of CPU instructions that can be used by applications to set aside private regions of code and data. The code outside the enclave is disallowed to access the memory inside the enclave by the CPU access control. Add a check for SGX to arch/x86 and a new config option, INTEL_SGX_CORE. Expose a boolean variable 'sgx_enabled' to query whether or not the SGX support is available. Signed-off-by: Sean Christopherson Co-developed-by: Jarkko Sakkinen Co-developed-by: Suresh Siddha Signed-off-by: Suresh Siddha Signed-off-by: Jarkko Sakkinen --- arch/x86/Kconfig | 19 +++++++++++++ arch/x86/include/asm/sgx.h | 12 +++++++++ arch/x86/include/asm/sgx_pr.h | 13 +++++++++ arch/x86/kernel/cpu/Makefile | 1 + arch/x86/kernel/cpu/intel_sgx.c | 47 +++++++++++++++++++++++++++++++++ 5 files changed, 92 insertions(+) create mode 100644 arch/x86/include/asm/sgx.h create mode 100644 arch/x86/include/asm/sgx_pr.h create mode 100644 arch/x86/kernel/cpu/intel_sgx.c diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index b0312f8947ce..3c7571422a07 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1911,6 +1911,25 @@ config X86_INTEL_MEMORY_PROTECTION_KEYS If unsure, say y. +config INTEL_SGX_CORE + prompt "Intel SGX core functionality" + def_bool n + depends on X86_64 && CPU_SUP_INTEL + help + Intel Software Guard eXtensions (SGX) is a set of CPU instructions + that allows ring 3 applications to create enclaves, private regions + of memory that are protected, by hardware, from unauthorized access + and/or modification. + + This option enables kernel recognition of SGX, high-level management + of the Enclave Page Cache (EPC), tracking and writing of SGX Launch + Enclave Hash MSRs, and allows for virtualization of SGX via KVM. By + iteslf, this option does not provide SGX support to userspace. + + For details, see Documentation/x86/intel_sgx.rst + + If unsure, say N. + config EFI bool "EFI runtime service support" depends on ACPI diff --git a/arch/x86/include/asm/sgx.h b/arch/x86/include/asm/sgx.h new file mode 100644 index 000000000000..2130e639ab49 --- /dev/null +++ b/arch/x86/include/asm/sgx.h @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +// Copyright(c) 2016-18 Intel Corporation. + +#ifndef _ASM_X86_SGX_H +#define _ASM_X86_SGX_H + +#include + +extern bool sgx_enabled; +extern bool sgx_lc_enabled; + +#endif /* _ASM_X86_SGX_H */ diff --git a/arch/x86/include/asm/sgx_pr.h b/arch/x86/include/asm/sgx_pr.h new file mode 100644 index 000000000000..c68578127620 --- /dev/null +++ b/arch/x86/include/asm/sgx_pr.h @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +// Copyright(c) 2016-17 Intel Corporation. + +#ifndef _ASM_X86_SGX_PR_H +#define _ASM_X86_SGX_PR_H + +#include +#include + +#undef pr_fmt +#define pr_fmt(fmt) "sgx: " fmt + +#endif /* _ASM_X86_SGX_PR_H */ diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile index 347137e80bf5..71876f2b35fc 100644 --- a/arch/x86/kernel/cpu/Makefile +++ b/arch/x86/kernel/cpu/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_CPU_SUP_UMC_32) += umc.o obj-$(CONFIG_INTEL_RDT) += intel_rdt.o intel_rdt_rdtgroup.o intel_rdt_monitor.o obj-$(CONFIG_INTEL_RDT) += intel_rdt_ctrlmondata.o intel_rdt_pseudo_lock.o CFLAGS_intel_rdt_pseudo_lock.o = -I$(src) +obj-$(CONFIG_INTEL_SGX_CORE) += intel_sgx.o obj-$(CONFIG_X86_MCE) += mcheck/ obj-$(CONFIG_MTRR) += mtrr/ diff --git a/arch/x86/kernel/cpu/intel_sgx.c b/arch/x86/kernel/cpu/intel_sgx.c new file mode 100644 index 000000000000..17b46bec9c54 --- /dev/null +++ b/arch/x86/kernel/cpu/intel_sgx.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +// Copyright(c) 2016-17 Intel Corporation. + +#include +#include +#include +#include +#include +#include +#include +#include + +bool sgx_enabled __ro_after_init; +EXPORT_SYMBOL_GPL(sgx_enabled); +bool sgx_lc_enabled __ro_after_init; +EXPORT_SYMBOL_GPL(sgx_lc_enabled); + +static __init int sgx_init(void) +{ + unsigned long fc; + + if (!boot_cpu_has(X86_FEATURE_SGX)) + return false; + + if (!boot_cpu_has(X86_FEATURE_SGX1)) + return false; + + rdmsrl(MSR_IA32_FEATURE_CONTROL, fc); + if (!(fc & FEATURE_CONTROL_LOCKED)) { + pr_info("IA32_FEATURE_CONTROL MSR is not locked\n"); + return false; + } + + if (!(fc & FEATURE_CONTROL_SGX_ENABLE)) { + pr_info("disabled by the firmware\n"); + return false; + } + + if (!(fc & FEATURE_CONTROL_SGX_LE_WR)) + pr_info("IA32_SGXLEPUBKEYHASHn MSRs are not writable\n"); + + sgx_enabled = true; + sgx_lc_enabled = !!(fc & FEATURE_CONTROL_SGX_LE_WR); + return 0; +} + +arch_initcall(sgx_init); -- 2.17.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jarkko Sakkinen Subject: [PATCH v13 06/13] x86/sgx: Detect Intel SGX Date: Mon, 27 Aug 2018 21:53:27 +0300 Message-ID: <20180827185507.17087-7-jarkko.sakkinen@linux.intel.com> References: <20180827185507.17087-1-jarkko.sakkinen@linux.intel.com> Return-path: In-Reply-To: <20180827185507.17087-1-jarkko.sakkinen@linux.intel.com> Sender: linux-kernel-owner@vger.kernel.org To: x86@kernel.org, platform-driver-x86@vger.kernel.org Cc: dave.hansen@intel.com, sean.j.christopherson@intel.com, nhorman@redhat.com, npmccallum@redhat.com, linux-sgx@vger.kernel.org, Suresh Siddha , Jarkko Sakkinen , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , Serge Ayoun , "Rafael J. Wysocki" , Borislav Petkov , Reinette Chatre , Andi Kleen , Greg Kroah-Hartman , "Kirill A. Shutemov" , "open list:X86 ARCHITECTURE 32-BIT AND 64-BIT" List-Id: platform-driver-x86.vger.kernel.org From: Sean Christopherson Intel(R) SGX is a set of CPU instructions that can be used by applications to set aside private regions of code and data. The code outside the enclave is disallowed to access the memory inside the enclave by the CPU access control. Add a check for SGX to arch/x86 and a new config option, INTEL_SGX_CORE. Expose a boolean variable 'sgx_enabled' to query whether or not the SGX support is available. Signed-off-by: Sean Christopherson Co-developed-by: Jarkko Sakkinen Co-developed-by: Suresh Siddha Signed-off-by: Suresh Siddha Signed-off-by: Jarkko Sakkinen --- arch/x86/Kconfig | 19 +++++++++++++ arch/x86/include/asm/sgx.h | 12 +++++++++ arch/x86/include/asm/sgx_pr.h | 13 +++++++++ arch/x86/kernel/cpu/Makefile | 1 + arch/x86/kernel/cpu/intel_sgx.c | 47 +++++++++++++++++++++++++++++++++ 5 files changed, 92 insertions(+) create mode 100644 arch/x86/include/asm/sgx.h create mode 100644 arch/x86/include/asm/sgx_pr.h create mode 100644 arch/x86/kernel/cpu/intel_sgx.c diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index b0312f8947ce..3c7571422a07 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1911,6 +1911,25 @@ config X86_INTEL_MEMORY_PROTECTION_KEYS If unsure, say y. +config INTEL_SGX_CORE + prompt "Intel SGX core functionality" + def_bool n + depends on X86_64 && CPU_SUP_INTEL + help + Intel Software Guard eXtensions (SGX) is a set of CPU instructions + that allows ring 3 applications to create enclaves, private regions + of memory that are protected, by hardware, from unauthorized access + and/or modification. + + This option enables kernel recognition of SGX, high-level management + of the Enclave Page Cache (EPC), tracking and writing of SGX Launch + Enclave Hash MSRs, and allows for virtualization of SGX via KVM. By + iteslf, this option does not provide SGX support to userspace. + + For details, see Documentation/x86/intel_sgx.rst + + If unsure, say N. + config EFI bool "EFI runtime service support" depends on ACPI diff --git a/arch/x86/include/asm/sgx.h b/arch/x86/include/asm/sgx.h new file mode 100644 index 000000000000..2130e639ab49 --- /dev/null +++ b/arch/x86/include/asm/sgx.h @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +// Copyright(c) 2016-18 Intel Corporation. + +#ifndef _ASM_X86_SGX_H +#define _ASM_X86_SGX_H + +#include + +extern bool sgx_enabled; +extern bool sgx_lc_enabled; + +#endif /* _ASM_X86_SGX_H */ diff --git a/arch/x86/include/asm/sgx_pr.h b/arch/x86/include/asm/sgx_pr.h new file mode 100644 index 000000000000..c68578127620 --- /dev/null +++ b/arch/x86/include/asm/sgx_pr.h @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +// Copyright(c) 2016-17 Intel Corporation. + +#ifndef _ASM_X86_SGX_PR_H +#define _ASM_X86_SGX_PR_H + +#include +#include + +#undef pr_fmt +#define pr_fmt(fmt) "sgx: " fmt + +#endif /* _ASM_X86_SGX_PR_H */ diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile index 347137e80bf5..71876f2b35fc 100644 --- a/arch/x86/kernel/cpu/Makefile +++ b/arch/x86/kernel/cpu/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_CPU_SUP_UMC_32) += umc.o obj-$(CONFIG_INTEL_RDT) += intel_rdt.o intel_rdt_rdtgroup.o intel_rdt_monitor.o obj-$(CONFIG_INTEL_RDT) += intel_rdt_ctrlmondata.o intel_rdt_pseudo_lock.o CFLAGS_intel_rdt_pseudo_lock.o = -I$(src) +obj-$(CONFIG_INTEL_SGX_CORE) += intel_sgx.o obj-$(CONFIG_X86_MCE) += mcheck/ obj-$(CONFIG_MTRR) += mtrr/ diff --git a/arch/x86/kernel/cpu/intel_sgx.c b/arch/x86/kernel/cpu/intel_sgx.c new file mode 100644 index 000000000000..17b46bec9c54 --- /dev/null +++ b/arch/x86/kernel/cpu/intel_sgx.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +// Copyright(c) 2016-17 Intel Corporation. + +#include +#include +#include +#include +#include +#include +#include +#include + +bool sgx_enabled __ro_after_init; +EXPORT_SYMBOL_GPL(sgx_enabled); +bool sgx_lc_enabled __ro_after_init; +EXPORT_SYMBOL_GPL(sgx_lc_enabled); + +static __init int sgx_init(void) +{ + unsigned long fc; + + if (!boot_cpu_has(X86_FEATURE_SGX)) + return false; + + if (!boot_cpu_has(X86_FEATURE_SGX1)) + return false; + + rdmsrl(MSR_IA32_FEATURE_CONTROL, fc); + if (!(fc & FEATURE_CONTROL_LOCKED)) { + pr_info("IA32_FEATURE_CONTROL MSR is not locked\n"); + return false; + } + + if (!(fc & FEATURE_CONTROL_SGX_ENABLE)) { + pr_info("disabled by the firmware\n"); + return false; + } + + if (!(fc & FEATURE_CONTROL_SGX_LE_WR)) + pr_info("IA32_SGXLEPUBKEYHASHn MSRs are not writable\n"); + + sgx_enabled = true; + sgx_lc_enabled = !!(fc & FEATURE_CONTROL_SGX_LE_WR); + return 0; +} + +arch_initcall(sgx_init); -- 2.17.1