From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD6A2C433F4 for ; Tue, 28 Aug 2018 10:21:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7EB6B20842 for ; Tue, 28 Aug 2018 10:21:21 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7EB6B20842 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=suse.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727336AbeH1OMQ (ORCPT ); Tue, 28 Aug 2018 10:12:16 -0400 Received: from mx2.suse.de ([195.135.220.15]:40344 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727124AbeH1OMQ (ORCPT ); Tue, 28 Aug 2018 10:12:16 -0400 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay1.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 27B71B056; Tue, 28 Aug 2018 10:21:17 +0000 (UTC) Date: Tue, 28 Aug 2018 12:21:40 +0200 From: Borislav Petkov To: Jarkko Sakkinen Cc: x86@kernel.org, platform-driver-x86@vger.kernel.org, dave.hansen@intel.com, sean.j.christopherson@intel.com, nhorman@redhat.com, npmccallum@redhat.com, linux-sgx@vger.kernel.org, Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , Paolo Bonzini , Radim =?utf-8?B?S3LEjW3DocWZ?= , Peter Zijlstra , Greg Kroah-Hartman , David Woodhouse , Alexei Starovoitov , Andi Kleen , Konrad Rzeszutek Wilk , Ricardo Neri , "Kirill A. Shutemov" , Andy Lutomirski , "open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "open list:KERNEL VIRTUAL MACHINE FOR X86 (KVM/x86)" Subject: Re: [PATCH v13 03/13] x86/cpufeatures: Add Intel-defined SGX leaf CPUID_12_EAX Message-ID: <20180828102140.GA31102@nazgul.tnic> References: <20180827185507.17087-1-jarkko.sakkinen@linux.intel.com> <20180827185507.17087-4-jarkko.sakkinen@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20180827185507.17087-4-jarkko.sakkinen@linux.intel.com> User-Agent: Mutt/1.6.0 (2016-04-01) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Aug 27, 2018 at 09:53:24PM +0300, Jarkko Sakkinen wrote: > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index 7bb647f57d42..4af60a0fdb20 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -13,7 +13,7 @@ > /* > * Defines x86 CPU feature bits > */ > -#define NCAPINTS 19 /* N 32-bit words worth of info */ > +#define NCAPINTS 20 /* N 32-bit words worth of info */ > #define NBUGINTS 1 /* N 32-bit bug flags */ > > /* > @@ -349,6 +349,12 @@ > #define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */ > #define X86_FEATURE_SPEC_CTRL_SSBD (18*32+31) /* "" Speculative Store Bypass Disable */ > > +/* Intel SGX CPU features, CPUID level 0x000000012:0 (EAX), word 19 */ > +#define X86_FEATURE_SGX1 (19*32+ 0) /* SGX1 leaf functions */ > +#define X86_FEATURE_SGX2 (19*32+ 1) /* SGX2 leaf functions */ > +#define X86_FEATURE_SGX_ENCLV (19*32+ 5) /* SGX ENCLV instruction, leafs E[INC|DEC]VIRTCHILD, ESETCONTEXT */ > +#define X86_FEATURE_SGX_ENCLS_C (19*32+ 6) /* SGX ENCLS leafs ERDINFO, ETRACK, ELDBC and ELDUC */ No need to add a whole new ->x86_capability member for 4 bits - just add those bits to leaf 8 where the artificial virtualization flags are - there's some room there. Thx. -- Regards/Gruss, Boris. SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham Norton, HRB 21284 (AG Nürnberg) -- From mboxrd@z Thu Jan 1 00:00:00 1970 From: Borislav Petkov Subject: Re: [PATCH v13 03/13] x86/cpufeatures: Add Intel-defined SGX leaf CPUID_12_EAX Date: Tue, 28 Aug 2018 12:21:40 +0200 Message-ID: <20180828102140.GA31102@nazgul.tnic> References: <20180827185507.17087-1-jarkko.sakkinen@linux.intel.com> <20180827185507.17087-4-jarkko.sakkinen@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Return-path: Content-Disposition: inline In-Reply-To: <20180827185507.17087-4-jarkko.sakkinen@linux.intel.com> Sender: linux-kernel-owner@vger.kernel.org To: Jarkko Sakkinen Cc: x86@kernel.org, platform-driver-x86@vger.kernel.org, dave.hansen@intel.com, sean.j.christopherson@intel.com, nhorman@redhat.com, npmccallum@redhat.com, linux-sgx@vger.kernel.org, Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , Paolo Bonzini , Radim =?utf-8?B?S3LEjW3DocWZ?= , Peter Zijlstra , Greg Kroah-Hartman , David Woodhouse , Alexei Starovoitov , Andi Kleen , Konrad Rzeszutek Wilk , Ricardo Neri , "Kirill A. Shutemov" , Andy Lutomirski List-Id: platform-driver-x86.vger.kernel.org On Mon, Aug 27, 2018 at 09:53:24PM +0300, Jarkko Sakkinen wrote: > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index 7bb647f57d42..4af60a0fdb20 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -13,7 +13,7 @@ > /* > * Defines x86 CPU feature bits > */ > -#define NCAPINTS 19 /* N 32-bit words worth of info */ > +#define NCAPINTS 20 /* N 32-bit words worth of info */ > #define NBUGINTS 1 /* N 32-bit bug flags */ > > /* > @@ -349,6 +349,12 @@ > #define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */ > #define X86_FEATURE_SPEC_CTRL_SSBD (18*32+31) /* "" Speculative Store Bypass Disable */ > > +/* Intel SGX CPU features, CPUID level 0x000000012:0 (EAX), word 19 */ > +#define X86_FEATURE_SGX1 (19*32+ 0) /* SGX1 leaf functions */ > +#define X86_FEATURE_SGX2 (19*32+ 1) /* SGX2 leaf functions */ > +#define X86_FEATURE_SGX_ENCLV (19*32+ 5) /* SGX ENCLV instruction, leafs E[INC|DEC]VIRTCHILD, ESETCONTEXT */ > +#define X86_FEATURE_SGX_ENCLS_C (19*32+ 6) /* SGX ENCLS leafs ERDINFO, ETRACK, ELDBC and ELDUC */ No need to add a whole new ->x86_capability member for 4 bits - just add those bits to leaf 8 where the artificial virtualization flags are - there's some room there. Thx. -- Regards/Gruss, Boris. SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham Norton, HRB 21284 (AG Nürnberg) --