Re: [Qemu-devel] [SeaBIOS] [RFC v2 0/3] Support multiple pci domains in pci_device

[Kevin O'Connor <kevin@koconnor.net>]

On Tue, Aug 28, 2018 at 08:17:19PM +0300, Marcel Apfelbaum wrote:
> On 08/28/2018 08:02 PM, Kevin O'Connor wrote:
> > On Tue, Aug 28, 2018 at 12:14:58PM +0200, Gerd Hoffmann wrote:
> > > > > Where is the pxb-pcie device?  0000:$somewhere?  Or $domain:00:00.0?
> > > >   0000:$somewhere (On PCI domain 0)
> > > Cool, so we don't have an chicken-and-egg issue.
> > > 
> > > > > If we can access pxb-pcie registers before configuring MMCFG then yes,
> > > > > we should use pxb-pcie registers for that.
> > > > Yes, we can.
> > > Ok, so we can configure mmcfg as hidden pci bar, simliar to the q35
> > > mmcfg.  Any configuration hints can be passed as pci vendor capability
> > > (simliar to the bridge window size hints), if needed.
> > Just so I understand, the proposal is to have SeaBIOS search for
> > pxb-pcie devices on the main PCI bus and allocate address space for
> > each.  (These devices would not be considered pci buses in the
> > traditional sense.)  Then SeaBIOS will traverse that address space
> > (MMCFG) and allocate BARs (both address space and io space) for the
> > PCI devices found in that address space.  Finally, QEMU will take all
> > those allocations and use it when generating the ACPI tables.
> > 
> > Did I get that right?
> 
> Yes, the pxb-pcie exposes a new PCI root bus, but we want it
> in a different PCI domain. This is done in order to remove the
> 256 PCI Express devices limitation on a PCI Express machine.
> 
> Does the plan sounds sane?

It sounds okay to me.

Separately, we could "dust off" the SeaBIOS PAE patches if we want to
place the address space allocations above 4GB.

-Kevin