From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [3/3] dmaengine: xilinx_dma: Fix 64-bit simple CDMA transfer From: Vinod Koul Message-Id: <20180829040111.GD2388@vkoul-mobl> Date: Wed, 29 Aug 2018 09:31:11 +0530 To: Radhey Shyam Pandey Cc: "dan.j.williams@intel.com" , Michal Simek , Appana Durga Kedareswara Rao , "lars@metafoo.de" , "dmaengine@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" List-ID: T24gMjgtMDgtMTgsIDE0OjAzLCBSYWRoZXkgU2h5YW0gUGFuZGV5IHdyb3RlOgo+ID4gT24gMjct MDctMTgsIDE2OjIwLCBSYWRoZXkgU2h5YW0gUGFuZGV5IHdyb3RlOgo+ID4gPiBJbiBBWEkgQ0RN QSBzaW1wbGUgbW9kZSBhbHNvIHBhc3MgTVNCIGJpdHMgb2Ygc291cmNlIGFuZCBkZXN0aW5hdGlv bgo+ID4gPiBhZGRyZXNzIHRvIHhpbGlueF93cml0ZSBmdW5jdGlvbi4gVGhpcyBmaXhlcyBzaW1w bGUgQ0RNQSBvcGVyYXRpb24KPiA+ID4gbW9kZSB1c2luZyA2NC1iaXQgYWRkcmVzc2luZy4KPiA+ ID4KPiA+ID4gU2lnbmVkLW9mZi1ieTogUmFkaGV5IFNoeWFtIFBhbmRleSA8cmFkaGV5LnNoeWFt LnBhbmRleUB4aWxpbnguY29tPgo+ID4gPiBTaWduZWQtb2ZmLWJ5OiBNaWNoYWwgU2ltZWsgPG1p Y2hhbC5zaW1la0B4aWxpbnguY29tPgo+ID4gPiAtLS0KPiA+ID4gIGRyaXZlcnMvZG1hL3hpbGlu eC94aWxpbnhfZG1hLmMgfCAgICA2ICsrKystLQo+ID4gPiAgMSBmaWxlcyBjaGFuZ2VkLCA0IGlu c2VydGlvbnMoKyksIDIgZGVsZXRpb25zKC0pCj4gPiA+Cj4gPiA+IGRpZmYgLS1naXQgYS9kcml2 ZXJzL2RtYS94aWxpbngveGlsaW54X2RtYS5jIGIvZHJpdmVycy9kbWEveGlsaW54L3hpbGlueF9k bWEuYwo+ID4gPiBpbmRleCBhMzc4NzFlLi4yZTE1ZDg2IDEwMDY0NAo+ID4gPiAtLS0gYS9kcml2 ZXJzL2RtYS94aWxpbngveGlsaW54X2RtYS5jCj4gPiA+ICsrKyBiL2RyaXZlcnMvZG1hL3hpbGlu eC94aWxpbnhfZG1hLmMKPiA+ID4gQEAgLTEyNDUsOCArMTI0NSwxMCBAQCBzdGF0aWMgdm9pZCB4 aWxpbnhfY2RtYV9zdGFydF90cmFuc2ZlcihzdHJ1Y3QKPiA+IHhpbGlueF9kbWFfY2hhbiAqY2hh bikKPiA+ID4KPiA+ID4gIAkJaHcgPSAmc2VnbWVudC0+aHc7Cj4gPiA+Cj4gPiA+IC0JCXhpbGlu eF93cml0ZShjaGFuLCBYSUxJTlhfQ0RNQV9SRUdfU1JDQUREUiwgaHctCj4gPiA+c3JjX2FkZHIp Owo+ID4gPiAtCQl4aWxpbnhfd3JpdGUoY2hhbiwgWElMSU5YX0NETUFfUkVHX0RTVEFERFIsIGh3 LQo+ID4gPmRlc3RfYWRkcik7Cj4gPiA+ICsJCXhpbGlueF93cml0ZShjaGFuLCBYSUxJTlhfQ0RN QV9SRUdfU1JDQUREUiwKPiA+IChkbWFfYWRkcl90KQo+ID4gPiArCQkJICAgICAoKHU2NClody0+ c3JjX2FkZHJfbXNiIDw8IDMyIHwgaHctPnNyY19hZGRyKSk7Cj4gPiAKPiA+IHNvIHRoaXMgaXM6 Cj4gPiAgICAgICAgIChkbWFfYWRkcl90KSgodTY0KWh3LT5zcmNfYWRkcl9tc2IgPDwgMzIgfCBo dy0+c3JjX2FkZHIpCj4gPiAKPiA+IHdoYXQgaXMgc3JjX2FkZHIgZGF0YSB0eXBlPyBJIHRoaW5r IGl0cyB1MzIuIEl0IHdvdWxkIGJlIGJldHRlciB0bwo+ID4gdXBkYXRlIHhpbGlueF93cml0ZSgp IHRvIHRha2UgdTY0IGFuZCBub3QgZG1hX2FkZHJfdC4KPiAKPiBZZXMsIHNyY19hZGRyX21zYiBh bmQgc3JjX2FkZHIgQkQgZmllbGRzIGFyZSB1MzIuIFRvIGV4cGxhaW46IFRoZXJlIGlzIG5vCj4g cHJvYiBpbiB4aWxpbnhfd3JpdGUgaXQgdGFrZXMgZG1hX2FkZHJfdCBhcyBhbiBhcmcgd2hpY2gg aXMgMzIvNjQgYml0IAo+IGRlcGVuZGluZyBvbiBfRE1BX0FERFJfVF82NEJJVC4gSW4gNjRiaXQg Q0RNQSB0cmFuc2ZlciwgdGhlcmUgd2FzIGEgYnVnCj4gaS5lIGluIHRoZSBjYWxsIHRvIHhpbGlu eF93cml0ZSBzcmNfYWRkcl9tc2IgMzIgYml0cyB3ZXJlIG5vdCBwYXNzZWQuIFRvIGZpeAo+IHRo YXQgY29tYmluZSBNU0IgYW5kIExTQiAzMiBiaXRzIGJlZm9yZSBwYXNzaW5nIGl0IHRvIHhpbGlu eF93cml0ZS4KClllYWggdGhhdCBwYXJ0IHdhcyBjbGVhciBidXQgdGhlIGltcGxlbWVudGF0aW9u IGNhbiBiZSBiZXR0ZXIuLgo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,MAILING_LIST_MULTI,SPF_PASS,T_DKIMWL_WL_HIGH,URIBL_BLOCKED, USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48472C433F4 for ; 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Wed, 29 Aug 2018 04:01:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1535515281; bh=mzGPb9ii1y+rcmHuqMM7Mi4BNtiBHe2MgIrJn3+j94k=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=VwI1GgmwOdPNQ1p6EdkXgZwGwrVpdby47JOy82CblWGw9ttVvKpdl5j1DwlIt3KJ1 DeUGUPeHVfCMnVMGgAwtPYPgAWUdwxJ4eVIH+pgNeUJP17ekchCFeDhoq9nOaZtiYS YHTotAYYPiWLeDWZeUcaHndTfUcACccaou6Wfg3o= Date: Wed, 29 Aug 2018 09:31:11 +0530 From: Vinod To: Radhey Shyam Pandey Cc: "dan.j.williams@intel.com" , Michal Simek , Appana Durga Kedareswara Rao , "lars@metafoo.de" , "dmaengine@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH 3/3] dmaengine: xilinx_dma: Fix 64-bit simple CDMA transfer Message-ID: <20180829040111.GD2388@vkoul-mobl> References: <1532688639-32230-1-git-send-email-radhey.shyam.pandey@xilinx.com> <1532688639-32230-4-git-send-email-radhey.shyam.pandey@xilinx.com> <20180821155553.GI2388@vkoul-mobl> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.2 (2017-12-15) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 28-08-18, 14:03, Radhey Shyam Pandey wrote: > > On 27-07-18, 16:20, Radhey Shyam Pandey wrote: > > > In AXI CDMA simple mode also pass MSB bits of source and destination > > > address to xilinx_write function. This fixes simple CDMA operation > > > mode using 64-bit addressing. > > > > > > Signed-off-by: Radhey Shyam Pandey > > > Signed-off-by: Michal Simek > > > --- > > > drivers/dma/xilinx/xilinx_dma.c | 6 ++++-- > > > 1 files changed, 4 insertions(+), 2 deletions(-) > > > > > > diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c > > > index a37871e..2e15d86 100644 > > > --- a/drivers/dma/xilinx/xilinx_dma.c > > > +++ b/drivers/dma/xilinx/xilinx_dma.c > > > @@ -1245,8 +1245,10 @@ static void xilinx_cdma_start_transfer(struct > > xilinx_dma_chan *chan) > > > > > > hw = &segment->hw; > > > > > > - xilinx_write(chan, XILINX_CDMA_REG_SRCADDR, hw- > > >src_addr); > > > - xilinx_write(chan, XILINX_CDMA_REG_DSTADDR, hw- > > >dest_addr); > > > + xilinx_write(chan, XILINX_CDMA_REG_SRCADDR, > > (dma_addr_t) > > > + ((u64)hw->src_addr_msb << 32 | hw->src_addr)); > > > > so this is: > > (dma_addr_t)((u64)hw->src_addr_msb << 32 | hw->src_addr) > > > > what is src_addr data type? I think its u32. It would be better to > > update xilinx_write() to take u64 and not dma_addr_t. > > Yes, src_addr_msb and src_addr BD fields are u32. To explain: There is no > prob in xilinx_write it takes dma_addr_t as an arg which is 32/64 bit > depending on _DMA_ADDR_T_64BIT. In 64bit CDMA transfer, there was a bug > i.e in the call to xilinx_write src_addr_msb 32 bits were not passed. To fix > that combine MSB and LSB 32 bits before passing it to xilinx_write. Yeah that part was clear but the implementation can be better.. -- ~Vinod From mboxrd@z Thu Jan 1 00:00:00 1970 From: vkoul@kernel.org (Vinod) Date: Wed, 29 Aug 2018 09:31:11 +0530 Subject: [PATCH 3/3] dmaengine: xilinx_dma: Fix 64-bit simple CDMA transfer In-Reply-To: References: <1532688639-32230-1-git-send-email-radhey.shyam.pandey@xilinx.com> <1532688639-32230-4-git-send-email-radhey.shyam.pandey@xilinx.com> <20180821155553.GI2388@vkoul-mobl> Message-ID: <20180829040111.GD2388@vkoul-mobl> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 28-08-18, 14:03, Radhey Shyam Pandey wrote: > > On 27-07-18, 16:20, Radhey Shyam Pandey wrote: > > > In AXI CDMA simple mode also pass MSB bits of source and destination > > > address to xilinx_write function. This fixes simple CDMA operation > > > mode using 64-bit addressing. > > > > > > Signed-off-by: Radhey Shyam Pandey > > > Signed-off-by: Michal Simek > > > --- > > > drivers/dma/xilinx/xilinx_dma.c | 6 ++++-- > > > 1 files changed, 4 insertions(+), 2 deletions(-) > > > > > > diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c > > > index a37871e..2e15d86 100644 > > > --- a/drivers/dma/xilinx/xilinx_dma.c > > > +++ b/drivers/dma/xilinx/xilinx_dma.c > > > @@ -1245,8 +1245,10 @@ static void xilinx_cdma_start_transfer(struct > > xilinx_dma_chan *chan) > > > > > > hw = &segment->hw; > > > > > > - xilinx_write(chan, XILINX_CDMA_REG_SRCADDR, hw- > > >src_addr); > > > - xilinx_write(chan, XILINX_CDMA_REG_DSTADDR, hw- > > >dest_addr); > > > + xilinx_write(chan, XILINX_CDMA_REG_SRCADDR, > > (dma_addr_t) > > > + ((u64)hw->src_addr_msb << 32 | hw->src_addr)); > > > > so this is: > > (dma_addr_t)((u64)hw->src_addr_msb << 32 | hw->src_addr) > > > > what is src_addr data type? I think its u32. It would be better to > > update xilinx_write() to take u64 and not dma_addr_t. > > Yes, src_addr_msb and src_addr BD fields are u32. To explain: There is no > prob in xilinx_write it takes dma_addr_t as an arg which is 32/64 bit > depending on _DMA_ADDR_T_64BIT. In 64bit CDMA transfer, there was a bug > i.e in the call to xilinx_write src_addr_msb 32 bits were not passed. To fix > that combine MSB and LSB 32 bits before passing it to xilinx_write. Yeah that part was clear but the implementation can be better.. -- ~Vinod