All of lore.kernel.org
 help / color / mirror / Atom feed
* [PATCH v9 0/2] Add XYUV format support
@ 2018-08-30 14:24 Stanislav Lisovskiy
  2018-08-30 14:24 ` [PATCH v9 1/2] drm: Introduce new DRM_FORMAT_XYUV Stanislav Lisovskiy
                   ` (6 more replies)
  0 siblings, 7 replies; 12+ messages in thread
From: Stanislav Lisovskiy @ 2018-08-30 14:24 UTC (permalink / raw)
  To: dri-devel; +Cc: intel-gfx, Ville.Syrjala, juha-pekka.heikkila

Introduced new XYUV scan-in format for framebuffer and
added support for it to i915(SkyLake+).

Stanislav Lisovskiy (2):
  drm: Introduce new DRM_FORMAT_XYUV
  drm/i915: Adding YUV444 packed format support for skl+

 drivers/gpu/drm/drm_fourcc.c         |  1 +
 drivers/gpu/drm/i915/i915_reg.h      |  2 +-
 drivers/gpu/drm/i915/intel_display.c | 15 +++++++++++++++
 drivers/gpu/drm/i915/intel_sprite.c  |  1 +
 include/uapi/drm/drm_fourcc.h        |  1 +
 5 files changed, 19 insertions(+), 1 deletion(-)

-- 
2.17.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread
* [PATCH v9 1/2] drm: Introduce new DRM_FORMAT_XYUV
  2018-08-30 14:24 [PATCH v9 0/2] Add XYUV format support Stanislav Lisovskiy
@ 2018-08-30 14:24 ` Stanislav Lisovskiy
  2018-08-30 14:24 ` [PATCH v9 2/2] drm/i915: Adding YUV444 packed format support for skl+ Stanislav Lisovskiy
                   ` (5 subsequent siblings)
  6 siblings, 0 replies; 12+ messages in thread
From: Stanislav Lisovskiy @ 2018-08-30 14:24 UTC (permalink / raw)
  To: dri-devel; +Cc: intel-gfx, Ville.Syrjala, juha-pekka.heikkila

v5: This is YUV444 packed format same as AYUV, but without alpha,
    as supported by i915.

v6: Removed unneeded initializer for new XYUV format.

v7: Added is_yuv field initialization according to latest
    drm_fourcc format structure initialization changes.

v8: Edited commit message to be more clear about skl+, renamed
    PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
    doesn't support per-pixel alpha. Fixed minor code issues.

v9: Moved DRM format check to proper place in intel_framebuffer_init.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/drm_fourcc.c  | 1 +
 include/uapi/drm/drm_fourcc.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 35c1e2742c27..2ad09c7ecebc 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -173,6 +173,7 @@ const struct drm_format_info *__drm_format_info(u32 format)
 		{ .format = DRM_FORMAT_UYVY,		.depth = 0,  .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
 		{ .format = DRM_FORMAT_VYUY,		.depth = 0,  .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
 		{ .format = DRM_FORMAT_AYUV,		.depth = 0,  .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true, .is_yuv = true },
+		{ .format = DRM_FORMAT_XYUV,		.depth = 0,  .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
 	};
 
 	unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 2ed46e9ae16a..5ba5b1473342 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -148,6 +148,7 @@ extern "C" {
 #define DRM_FORMAT_VYUY		fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
 
 #define DRM_FORMAT_AYUV		fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
+#define DRM_FORMAT_XYUV		fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
 
 /*
  * 2 plane RGB + A
-- 
2.17.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [PATCH v9 2/2] drm/i915: Adding YUV444 packed format support for skl+
  2018-08-30 14:24 [PATCH v9 0/2] Add XYUV format support Stanislav Lisovskiy
  2018-08-30 14:24 ` [PATCH v9 1/2] drm: Introduce new DRM_FORMAT_XYUV Stanislav Lisovskiy
@ 2018-08-30 14:24 ` Stanislav Lisovskiy
  2018-09-04 12:47   ` [Intel-gfx] " Maarten Lankhorst
  2018-08-30 15:30 ` ✗ Fi.CI.CHECKPATCH: warning for Add XYUV format support (rev5) Patchwork
                   ` (4 subsequent siblings)
  6 siblings, 1 reply; 12+ messages in thread
From: Stanislav Lisovskiy @ 2018-08-30 14:24 UTC (permalink / raw)
  To: dri-devel; +Cc: intel-gfx, Ville.Syrjala, juha-pekka.heikkila

PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
specification.

v2: Edited commit message, removed redundant whitespaces.

v3: Fixed fallthrough logic for the format switch cases.

v4: Yet again fixed fallthrough logic, to reuse code from other case
    labels.

v5: Started to use XYUV instead of AYUV, as we don't use alpha.

v6: Removed unneeded initializer for new XYUV format.

v7: Added scaling support for DRM_FORMAT_XYUV

v8: Edited commit message to be more clear about skl+, renamed
    PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
    doesn't support per-pixel alpha. Fixed minor code issues.

v9: Moved DRM format check to proper place in intel_framebuffer_init.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |  2 +-
 drivers/gpu/drm/i915/intel_display.c | 15 +++++++++++++++
 drivers/gpu/drm/i915/intel_sprite.c  |  1 +
 3 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8534f88a60f6..e0c8480aaa02 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6499,7 +6499,7 @@ enum {
 #define   PLANE_CTL_FORMAT_XRGB_2101010		(2 << 24)
 #define   PLANE_CTL_FORMAT_XRGB_8888		(4 << 24)
 #define   PLANE_CTL_FORMAT_XRGB_16161616F	(6 << 24)
-#define   PLANE_CTL_FORMAT_AYUV			(8 << 24)
+#define   PLANE_CTL_FORMAT_XYUV			(8 << 24)
 #define   PLANE_CTL_FORMAT_INDEXED		(12 << 24)
 #define   PLANE_CTL_FORMAT_RGB_565		(14 << 24)
 #define   ICL_PLANE_CTL_FORMAT_MASK		(0x1f << 23)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 30fdfd1a3037..9323708db71f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -86,6 +86,7 @@ static const uint32_t skl_primary_formats[] = {
 	DRM_FORMAT_YVYU,
 	DRM_FORMAT_UYVY,
 	DRM_FORMAT_VYUY,
+	DRM_FORMAT_XYUV,
 };
 
 static const uint32_t skl_pri_planar_formats[] = {
@@ -101,6 +102,7 @@ static const uint32_t skl_pri_planar_formats[] = {
 	DRM_FORMAT_YVYU,
 	DRM_FORMAT_UYVY,
 	DRM_FORMAT_VYUY,
+	DRM_FORMAT_XYUV,
 	DRM_FORMAT_NV12,
 };
 
@@ -2672,6 +2674,8 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
 		return DRM_FORMAT_RGB565;
 	case PLANE_CTL_FORMAT_NV12:
 		return DRM_FORMAT_NV12;
+	case PLANE_CTL_FORMAT_XYUV:
+		return DRM_FORMAT_XYUV;
 	default:
 	case PLANE_CTL_FORMAT_XRGB_8888:
 		if (rgb_order) {
@@ -3501,6 +3505,8 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
 		return PLANE_CTL_FORMAT_XRGB_2101010;
 	case DRM_FORMAT_XBGR2101010:
 		return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
+	case DRM_FORMAT_XYUV:
+		return PLANE_CTL_FORMAT_XYUV;
 	case DRM_FORMAT_YUYV:
 		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
 	case DRM_FORMAT_YVYU:
@@ -4959,6 +4965,7 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
 	case DRM_FORMAT_UYVY:
 	case DRM_FORMAT_VYUY:
 	case DRM_FORMAT_NV12:
+	case DRM_FORMAT_XYUV:
 		break;
 	default:
 		DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
@@ -13414,6 +13421,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
 	case DRM_FORMAT_UYVY:
 	case DRM_FORMAT_VYUY:
 	case DRM_FORMAT_NV12:
+	case DRM_FORMAT_XYUV:
 		if (modifier == I915_FORMAT_MOD_Yf_TILED)
 			return true;
 		/* fall through */
@@ -14540,6 +14548,13 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 			goto err;
 		}
 		break;
+	case DRM_FORMAT_XYUV:
+		if (INTEL_GEN(dev_priv) < 9) {
+			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
+				      drm_get_format_name(mode_cmd->pixel_format, &format_name));
+			goto err;
+		}
+		break;
 	case DRM_FORMAT_YUYV:
 	case DRM_FORMAT_UYVY:
 	case DRM_FORMAT_YVYU:
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index c286dda625e4..2ac9471974c2 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1420,6 +1420,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
 	case DRM_FORMAT_UYVY:
 	case DRM_FORMAT_VYUY:
 	case DRM_FORMAT_NV12:
+	case DRM_FORMAT_XYUV:
 		if (modifier == I915_FORMAT_MOD_Yf_TILED)
 			return true;
 		/* fall through */
-- 
2.17.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Add XYUV format support (rev5)
  2018-08-30 14:24 [PATCH v9 0/2] Add XYUV format support Stanislav Lisovskiy
  2018-08-30 14:24 ` [PATCH v9 1/2] drm: Introduce new DRM_FORMAT_XYUV Stanislav Lisovskiy
  2018-08-30 14:24 ` [PATCH v9 2/2] drm/i915: Adding YUV444 packed format support for skl+ Stanislav Lisovskiy
@ 2018-08-30 15:30 ` Patchwork
  2018-08-30 15:51 ` ✓ Fi.CI.BAT: success " Patchwork
                   ` (3 subsequent siblings)
  6 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2018-08-30 15:30 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: intel-gfx

== Series Details ==

Series: Add XYUV format support (rev5)
URL   : https://patchwork.freedesktop.org/series/48007/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
48d9e0cf5f5e drm: Introduce new DRM_FORMAT_XYUV
-:30: WARNING:LONG_LINE: line over 100 characters
#30: FILE: drivers/gpu/drm/drm_fourcc.c:176:
+		{ .format = DRM_FORMAT_XYUV,		.depth = 0,  .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },

-:42: WARNING:LONG_LINE_COMMENT: line over 100 characters
#42: FILE: include/uapi/drm/drm_fourcc.h:151:
+#define DRM_FORMAT_XYUV		fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */

total: 0 errors, 2 warnings, 0 checks, 14 lines checked
7eb5932ca612 drm/i915: Adding YUV444 packed format support for skl+

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread
* ✓ Fi.CI.BAT: success for Add XYUV format support (rev5)
  2018-08-30 14:24 [PATCH v9 0/2] Add XYUV format support Stanislav Lisovskiy
                   ` (2 preceding siblings ...)
  2018-08-30 15:30 ` ✗ Fi.CI.CHECKPATCH: warning for Add XYUV format support (rev5) Patchwork
@ 2018-08-30 15:51 ` Patchwork
  2018-08-30 20:40 ` ✗ Fi.CI.IGT: failure " Patchwork
                   ` (2 subsequent siblings)
  6 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2018-08-30 15:51 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: intel-gfx

== Series Details ==

Series: Add XYUV format support (rev5)
URL   : https://patchwork.freedesktop.org/series/48007/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4740 -> Patchwork_10053 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/48007/revisions/5/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10053:

  === IGT changes ===

    ==== Warnings ====

    {igt@pm_rpm@module-reload}:
      fi-hsw-4770r:       PASS -> SKIP

    
== Known issues ==

  Here are the changes found in Patchwork_10053 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_module_reload@basic-reload-inject:
      fi-hsw-4770r:       PASS -> DMESG-WARN (fdo#107425)

    igt@gem_exec_suspend@basic-s3:
      {fi-kbl-soraka}:    NOTRUN -> INCOMPLETE (fdo#107556)

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
      fi-skl-6260u:       PASS -> INCOMPLETE (fdo#107556, fdo#104108)

    
    ==== Possible fixes ====

    {igt@amdgpu/amd_prime@i915-to-amd}:
      fi-bxt-j4205:       INCOMPLETE (fdo#103927) -> SKIP

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
      {fi-byt-clapper}:   FAIL (fdo#107362, fdo#103191) -> PASS

    {igt@pm_rpm@module-reload}:
      fi-bxt-j4205:       DMESG-FAIL (fdo#107712) -> PASS

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107425 https://bugs.freedesktop.org/show_bug.cgi?id=107425
  fdo#107556 https://bugs.freedesktop.org/show_bug.cgi?id=107556
  fdo#107712 https://bugs.freedesktop.org/show_bug.cgi?id=107712


== Participating hosts (53 -> 49) ==

  Additional (1): fi-kbl-soraka 
  Missing    (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u 


== Build changes ==

    * Linux: CI_DRM_4740 -> Patchwork_10053

  CI_DRM_4740: dc30149e06cea1672bac53f0fa7b8f5606ca8d1c @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4612: e39e09910fc8e369e24f6a0cabaeb9356dbfae08 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10053: 7eb5932ca612e002b83fde01dd4f5316ce2e2efe @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

7eb5932ca612 drm/i915: Adding YUV444 packed format support for skl+
48d9e0cf5f5e drm: Introduce new DRM_FORMAT_XYUV

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10053/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread
* ✗ Fi.CI.IGT: failure for Add XYUV format support (rev5)
  2018-08-30 14:24 [PATCH v9 0/2] Add XYUV format support Stanislav Lisovskiy
                   ` (3 preceding siblings ...)
  2018-08-30 15:51 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-08-30 20:40 ` Patchwork
  2018-09-04 11:33 ` ✓ Fi.CI.BAT: success " Patchwork
  2018-09-04 13:58 ` ✗ Fi.CI.IGT: failure " Patchwork
  6 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2018-08-30 20:40 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: intel-gfx

== Series Details ==

Series: Add XYUV format support (rev5)
URL   : https://patchwork.freedesktop.org/series/48007/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4740_full -> Patchwork_10053_full =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_10053_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10053_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10053_full:

  === IGT changes ===

    ==== Possible regressions ====

    igt@kms_available_modes_crc@available_mode_test_crc:
      shard-apl:          PASS -> FAIL

    
    ==== Warnings ====

    igt@kms_cursor_legacy@flip-vs-cursor-legacy:
      shard-snb:          SKIP -> PASS +2

    
== Known issues ==

  Here are the changes found in Patchwork_10053_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_ppgtt@blt-vs-render-ctx0:
      shard-kbl:          PASS -> INCOMPLETE (fdo#103665, fdo#106023)

    igt@perf_pmu@enable-race-bcs0:
      shard-snb:          SKIP -> INCOMPLETE (fdo#105411)

    
    ==== Possible fixes ====

    igt@drv_suspend@shrink:
      shard-hsw:          INCOMPLETE (fdo#106886, fdo#103540) -> PASS

    igt@gem_exec_await@wide-contexts:
      shard-kbl:          FAIL (fdo#105900) -> PASS

    igt@gem_render_linear_blits@basic:
      shard-kbl:          INCOMPLETE (fdo#103665) -> PASS

    igt@kms_frontbuffer_tracking@fbc-badstride:
      shard-glk:          FAIL (fdo#103167) -> PASS

    igt@perf@polling:
      shard-hsw:          FAIL (fdo#102252) -> PASS

    
  fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
  fdo#105900 https://bugs.freedesktop.org/show_bug.cgi?id=105900
  fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023
  fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4740 -> Patchwork_10053

  CI_DRM_4740: dc30149e06cea1672bac53f0fa7b8f5606ca8d1c @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4612: e39e09910fc8e369e24f6a0cabaeb9356dbfae08 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10053: 7eb5932ca612e002b83fde01dd4f5316ce2e2efe @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10053/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread
* ✓ Fi.CI.BAT: success for Add XYUV format support (rev5)
  2018-08-30 14:24 [PATCH v9 0/2] Add XYUV format support Stanislav Lisovskiy
                   ` (4 preceding siblings ...)
  2018-08-30 20:40 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2018-09-04 11:33 ` Patchwork
  2018-09-04 13:58 ` ✗ Fi.CI.IGT: failure " Patchwork
  6 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2018-09-04 11:33 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: intel-gfx

== Series Details ==

Series: Add XYUV format support (rev5)
URL   : https://patchwork.freedesktop.org/series/48007/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4763 -> Patchwork_10078 =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_10078 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10078, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/48007/revisions/5/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10078:

  === IGT changes ===

    ==== Warnings ====

    igt@pm_rpm@module-reload:
      fi-hsw-4770r:       PASS -> SKIP

    
== Known issues ==

  Here are the changes found in Patchwork_10078 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_module_reload@basic-reload-inject:
      fi-hsw-4770r:       PASS -> DMESG-WARN (fdo#107425)

    igt@kms_frontbuffer_tracking@basic:
      fi-hsw-peppy:       PASS -> DMESG-WARN (fdo#102614)

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-byt-clapper:     PASS -> FAIL (fdo#103191, fdo#107362) +1

    igt@kms_psr@primary_page_flip:
      fi-cnl-psr:         PASS -> FAIL (fdo#107336)

    
    ==== Possible fixes ====

    igt@kms_pipe_crc_basic@hang-read-crc-pipe-b:
      fi-skl-guc:         FAIL (fdo#103191) -> PASS

    igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence:
      fi-byt-clapper:     FAIL (fdo#103191, fdo#107362) -> PASS

    igt@pm_rpm@module-reload:
      fi-cnl-psr:         WARN (fdo#107602, fdo#107708) -> PASS

    
    ==== Warnings ====

    igt@pm_rpm@module-reload:
      fi-bsw-n3050:       DMESG-WARN (fdo#107704) -> DMESG-FAIL (fdo#107704)

    
  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107425 https://bugs.freedesktop.org/show_bug.cgi?id=107425
  fdo#107602 https://bugs.freedesktop.org/show_bug.cgi?id=107602
  fdo#107704 https://bugs.freedesktop.org/show_bug.cgi?id=107704
  fdo#107708 https://bugs.freedesktop.org/show_bug.cgi?id=107708


== Participating hosts (52 -> 46) ==

  Missing    (6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 


== Build changes ==

    * Linux: CI_DRM_4763 -> Patchwork_10078

  CI_DRM_4763: 1f8c06844acac7a349fb80471afcc09f33c6cfc0 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4622: 022be555443eaa3317da6a9a451cf2c9dfcd6ab8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10078: 5c8a6f919689dd4a640ddadc5ba8c0ce07025a45 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

5c8a6f919689 drm/i915: Adding YUV444 packed format support for skl+
65e3d6aeadbe drm: Introduce new DRM_FORMAT_XYUV

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10078/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH v9 2/2] drm/i915: Adding YUV444 packed format support for skl+
  2018-08-30 14:24 ` [PATCH v9 2/2] drm/i915: Adding YUV444 packed format support for skl+ Stanislav Lisovskiy
@ 2018-09-04 12:47   ` Maarten Lankhorst
  2018-09-04 13:50     ` Ville Syrjälä
  0 siblings, 1 reply; 12+ messages in thread
From: Maarten Lankhorst @ 2018-09-04 12:47 UTC (permalink / raw)
  To: Stanislav Lisovskiy, dri-devel
  Cc: intel-gfx, Ville.Syrjala, juha-pekka.heikkila

Op 30-08-18 om 16:24 schreef Stanislav Lisovskiy:
> PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
> specification.
>
> v2: Edited commit message, removed redundant whitespaces.
>
> v3: Fixed fallthrough logic for the format switch cases.
>
> v4: Yet again fixed fallthrough logic, to reuse code from other case
>     labels.
>
> v5: Started to use XYUV instead of AYUV, as we don't use alpha.
>
> v6: Removed unneeded initializer for new XYUV format.
>
> v7: Added scaling support for DRM_FORMAT_XYUV
>
> v8: Edited commit message to be more clear about skl+, renamed
>     PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
>     doesn't support per-pixel alpha. Fixed minor code issues.
>
> v9: Moved DRM format check to proper place in intel_framebuffer_init.
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      |  2 +-
>  drivers/gpu/drm/i915/intel_display.c | 15 +++++++++++++++
>  drivers/gpu/drm/i915/intel_sprite.c  |  1 +
>  3 files changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8534f88a60f6..e0c8480aaa02 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6499,7 +6499,7 @@ enum {
>  #define   PLANE_CTL_FORMAT_XRGB_2101010		(2 << 24)
>  #define   PLANE_CTL_FORMAT_XRGB_8888		(4 << 24)
>  #define   PLANE_CTL_FORMAT_XRGB_16161616F	(6 << 24)
> -#define   PLANE_CTL_FORMAT_AYUV			(8 << 24)
> +#define   PLANE_CTL_FORMAT_XYUV			(8 << 24)
>  #define   PLANE_CTL_FORMAT_INDEXED		(12 << 24)
>  #define   PLANE_CTL_FORMAT_RGB_565		(14 << 24)
>  #define   ICL_PLANE_CTL_FORMAT_MASK		(0x1f << 23)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 30fdfd1a3037..9323708db71f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -86,6 +86,7 @@ static const uint32_t skl_primary_formats[] = {
>  	DRM_FORMAT_YVYU,
>  	DRM_FORMAT_UYVY,
>  	DRM_FORMAT_VYUY,
> +	DRM_FORMAT_XYUV,
>  };
>  
>  static const uint32_t skl_pri_planar_formats[] = {
> @@ -101,6 +102,7 @@ static const uint32_t skl_pri_planar_formats[] = {
>  	DRM_FORMAT_YVYU,
>  	DRM_FORMAT_UYVY,
>  	DRM_FORMAT_VYUY,
> +	DRM_FORMAT_XYUV,
>  	DRM_FORMAT_NV12,
>  };
>  
> @@ -2672,6 +2674,8 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
>  		return DRM_FORMAT_RGB565;
>  	case PLANE_CTL_FORMAT_NV12:
>  		return DRM_FORMAT_NV12;
> +	case PLANE_CTL_FORMAT_XYUV:
> +		return DRM_FORMAT_XYUV;
>  	default:
>  	case PLANE_CTL_FORMAT_XRGB_8888:
>  		if (rgb_order) {
> @@ -3501,6 +3505,8 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
>  		return PLANE_CTL_FORMAT_XRGB_2101010;
>  	case DRM_FORMAT_XBGR2101010:
>  		return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
> +	case DRM_FORMAT_XYUV:
> +		return PLANE_CTL_FORMAT_XYUV;
>  	case DRM_FORMAT_YUYV:
>  		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
>  	case DRM_FORMAT_YVYU:
> @@ -4959,6 +4965,7 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
>  	case DRM_FORMAT_UYVY:
>  	case DRM_FORMAT_VYUY:
>  	case DRM_FORMAT_NV12:
> +	case DRM_FORMAT_XYUV:
>  		break;
>  	default:
>  		DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
> @@ -13414,6 +13421,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
>  	case DRM_FORMAT_UYVY:
>  	case DRM_FORMAT_VYUY:
>  	case DRM_FORMAT_NV12:
> +	case DRM_FORMAT_XYUV:
>  		if (modifier == I915_FORMAT_MOD_Yf_TILED)
>  			return true;
>  		/* fall through */
> @@ -14540,6 +14548,13 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>  			goto err;
>  		}
>  		break;
> +	case DRM_FORMAT_XYUV:
> +		if (INTEL_GEN(dev_priv) < 9) {
> +			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
> +				      drm_get_format_name(mode_cmd->pixel_format, &format_name));
> +			goto err;
> +		}
> +		break;
This hunk isn't needed. DRM core rejects any formats not in the format arrays.

Can you add another patch to audit the framebuffer formats in intel_framebuffer_init and remove the errors we can no longer hit?
It should be all of them, but might mean we have to add a few more format arrays. It will probably be more readable to split it off
to its own function that returns the array and its size.

~Maarten
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH v9 2/2] drm/i915: Adding YUV444 packed format support for skl+
  2018-09-04 12:47   ` [Intel-gfx] " Maarten Lankhorst
@ 2018-09-04 13:50     ` Ville Syrjälä
  2018-09-04 13:52       ` Maarten Lankhorst
  0 siblings, 1 reply; 12+ messages in thread
From: Ville Syrjälä @ 2018-09-04 13:50 UTC (permalink / raw)
  To: Maarten Lankhorst; +Cc: intel-gfx, juha-pekka.heikkila, dri-devel

On Tue, Sep 04, 2018 at 02:47:51PM +0200, Maarten Lankhorst wrote:
> Op 30-08-18 om 16:24 schreef Stanislav Lisovskiy:
> > PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
> > specification.
> >
> > v2: Edited commit message, removed redundant whitespaces.
> >
> > v3: Fixed fallthrough logic for the format switch cases.
> >
> > v4: Yet again fixed fallthrough logic, to reuse code from other case
> >     labels.
> >
> > v5: Started to use XYUV instead of AYUV, as we don't use alpha.
> >
> > v6: Removed unneeded initializer for new XYUV format.
> >
> > v7: Added scaling support for DRM_FORMAT_XYUV
> >
> > v8: Edited commit message to be more clear about skl+, renamed
> >     PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
> >     doesn't support per-pixel alpha. Fixed minor code issues.
> >
> > v9: Moved DRM format check to proper place in intel_framebuffer_init.
> >
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h      |  2 +-
> >  drivers/gpu/drm/i915/intel_display.c | 15 +++++++++++++++
> >  drivers/gpu/drm/i915/intel_sprite.c  |  1 +
> >  3 files changed, 17 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 8534f88a60f6..e0c8480aaa02 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6499,7 +6499,7 @@ enum {
> >  #define   PLANE_CTL_FORMAT_XRGB_2101010		(2 << 24)
> >  #define   PLANE_CTL_FORMAT_XRGB_8888		(4 << 24)
> >  #define   PLANE_CTL_FORMAT_XRGB_16161616F	(6 << 24)
> > -#define   PLANE_CTL_FORMAT_AYUV			(8 << 24)
> > +#define   PLANE_CTL_FORMAT_XYUV			(8 << 24)
> >  #define   PLANE_CTL_FORMAT_INDEXED		(12 << 24)
> >  #define   PLANE_CTL_FORMAT_RGB_565		(14 << 24)
> >  #define   ICL_PLANE_CTL_FORMAT_MASK		(0x1f << 23)
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 30fdfd1a3037..9323708db71f 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -86,6 +86,7 @@ static const uint32_t skl_primary_formats[] = {
> >  	DRM_FORMAT_YVYU,
> >  	DRM_FORMAT_UYVY,
> >  	DRM_FORMAT_VYUY,
> > +	DRM_FORMAT_XYUV,
> >  };
> >  
> >  static const uint32_t skl_pri_planar_formats[] = {
> > @@ -101,6 +102,7 @@ static const uint32_t skl_pri_planar_formats[] = {
> >  	DRM_FORMAT_YVYU,
> >  	DRM_FORMAT_UYVY,
> >  	DRM_FORMAT_VYUY,
> > +	DRM_FORMAT_XYUV,
> >  	DRM_FORMAT_NV12,
> >  };
> >  
> > @@ -2672,6 +2674,8 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
> >  		return DRM_FORMAT_RGB565;
> >  	case PLANE_CTL_FORMAT_NV12:
> >  		return DRM_FORMAT_NV12;
> > +	case PLANE_CTL_FORMAT_XYUV:
> > +		return DRM_FORMAT_XYUV;
> >  	default:
> >  	case PLANE_CTL_FORMAT_XRGB_8888:
> >  		if (rgb_order) {
> > @@ -3501,6 +3505,8 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
> >  		return PLANE_CTL_FORMAT_XRGB_2101010;
> >  	case DRM_FORMAT_XBGR2101010:
> >  		return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
> > +	case DRM_FORMAT_XYUV:
> > +		return PLANE_CTL_FORMAT_XYUV;
> >  	case DRM_FORMAT_YUYV:
> >  		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
> >  	case DRM_FORMAT_YVYU:
> > @@ -4959,6 +4965,7 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
> >  	case DRM_FORMAT_UYVY:
> >  	case DRM_FORMAT_VYUY:
> >  	case DRM_FORMAT_NV12:
> > +	case DRM_FORMAT_XYUV:
> >  		break;
> >  	default:
> >  		DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
> > @@ -13414,6 +13421,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
> >  	case DRM_FORMAT_UYVY:
> >  	case DRM_FORMAT_VYUY:
> >  	case DRM_FORMAT_NV12:
> > +	case DRM_FORMAT_XYUV:
> >  		if (modifier == I915_FORMAT_MOD_Yf_TILED)
> >  			return true;
> >  		/* fall through */
> > @@ -14540,6 +14548,13 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
> >  			goto err;
> >  		}
> >  		break;
> > +	case DRM_FORMAT_XYUV:
> > +		if (INTEL_GEN(dev_priv) < 9) {
> > +			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
> > +				      drm_get_format_name(mode_cmd->pixel_format, &format_name));
> > +			goto err;
> > +		}
> > +		break;
> This hunk isn't needed. DRM core rejects any formats not in the format arrays.

There is no formats array for addfb. My patches to elimintate this ugly
code by cross checking with every plane got stuck in limbo.

-- 
Ville Syrjälä
Intel
---------------------------------------------------------------------
Intel Finland Oy
Registered Address: PL 281, 00181 Helsinki 
Business Identity Code: 0357606 - 4 
Domiciled in Helsinki 

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH v9 2/2] drm/i915: Adding YUV444 packed format support for skl+
  2018-09-04 13:50     ` Ville Syrjälä
@ 2018-09-04 13:52       ` Maarten Lankhorst
  2018-09-04 14:06         ` Ville Syrjälä
  0 siblings, 1 reply; 12+ messages in thread
From: Maarten Lankhorst @ 2018-09-04 13:52 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx, juha-pekka.heikkila, dri-devel

Op 04-09-18 om 15:50 schreef Ville Syrjälä:
> On Tue, Sep 04, 2018 at 02:47:51PM +0200, Maarten Lankhorst wrote:
>> Op 30-08-18 om 16:24 schreef Stanislav Lisovskiy:
>>> PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
>>> specification.
>>>
>>> v2: Edited commit message, removed redundant whitespaces.
>>>
>>> v3: Fixed fallthrough logic for the format switch cases.
>>>
>>> v4: Yet again fixed fallthrough logic, to reuse code from other case
>>>     labels.
>>>
>>> v5: Started to use XYUV instead of AYUV, as we don't use alpha.
>>>
>>> v6: Removed unneeded initializer for new XYUV format.
>>>
>>> v7: Added scaling support for DRM_FORMAT_XYUV
>>>
>>> v8: Edited commit message to be more clear about skl+, renamed
>>>     PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
>>>     doesn't support per-pixel alpha. Fixed minor code issues.
>>>
>>> v9: Moved DRM format check to proper place in intel_framebuffer_init.
>>>
>>> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>>> ---
>>>  drivers/gpu/drm/i915/i915_reg.h      |  2 +-
>>>  drivers/gpu/drm/i915/intel_display.c | 15 +++++++++++++++
>>>  drivers/gpu/drm/i915/intel_sprite.c  |  1 +
>>>  3 files changed, 17 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>> index 8534f88a60f6..e0c8480aaa02 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -6499,7 +6499,7 @@ enum {
>>>  #define   PLANE_CTL_FORMAT_XRGB_2101010		(2 << 24)
>>>  #define   PLANE_CTL_FORMAT_XRGB_8888		(4 << 24)
>>>  #define   PLANE_CTL_FORMAT_XRGB_16161616F	(6 << 24)
>>> -#define   PLANE_CTL_FORMAT_AYUV			(8 << 24)
>>> +#define   PLANE_CTL_FORMAT_XYUV			(8 << 24)
>>>  #define   PLANE_CTL_FORMAT_INDEXED		(12 << 24)
>>>  #define   PLANE_CTL_FORMAT_RGB_565		(14 << 24)
>>>  #define   ICL_PLANE_CTL_FORMAT_MASK		(0x1f << 23)
>>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>>> index 30fdfd1a3037..9323708db71f 100644
>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>> @@ -86,6 +86,7 @@ static const uint32_t skl_primary_formats[] = {
>>>  	DRM_FORMAT_YVYU,
>>>  	DRM_FORMAT_UYVY,
>>>  	DRM_FORMAT_VYUY,
>>> +	DRM_FORMAT_XYUV,
>>>  };
>>>  
>>>  static const uint32_t skl_pri_planar_formats[] = {
>>> @@ -101,6 +102,7 @@ static const uint32_t skl_pri_planar_formats[] = {
>>>  	DRM_FORMAT_YVYU,
>>>  	DRM_FORMAT_UYVY,
>>>  	DRM_FORMAT_VYUY,
>>> +	DRM_FORMAT_XYUV,
>>>  	DRM_FORMAT_NV12,
>>>  };
>>>  
>>> @@ -2672,6 +2674,8 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
>>>  		return DRM_FORMAT_RGB565;
>>>  	case PLANE_CTL_FORMAT_NV12:
>>>  		return DRM_FORMAT_NV12;
>>> +	case PLANE_CTL_FORMAT_XYUV:
>>> +		return DRM_FORMAT_XYUV;
>>>  	default:
>>>  	case PLANE_CTL_FORMAT_XRGB_8888:
>>>  		if (rgb_order) {
>>> @@ -3501,6 +3505,8 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
>>>  		return PLANE_CTL_FORMAT_XRGB_2101010;
>>>  	case DRM_FORMAT_XBGR2101010:
>>>  		return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
>>> +	case DRM_FORMAT_XYUV:
>>> +		return PLANE_CTL_FORMAT_XYUV;
>>>  	case DRM_FORMAT_YUYV:
>>>  		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
>>>  	case DRM_FORMAT_YVYU:
>>> @@ -4959,6 +4965,7 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
>>>  	case DRM_FORMAT_UYVY:
>>>  	case DRM_FORMAT_VYUY:
>>>  	case DRM_FORMAT_NV12:
>>> +	case DRM_FORMAT_XYUV:
>>>  		break;
>>>  	default:
>>>  		DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
>>> @@ -13414,6 +13421,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
>>>  	case DRM_FORMAT_UYVY:
>>>  	case DRM_FORMAT_VYUY:
>>>  	case DRM_FORMAT_NV12:
>>> +	case DRM_FORMAT_XYUV:
>>>  		if (modifier == I915_FORMAT_MOD_Yf_TILED)
>>>  			return true;
>>>  		/* fall through */
>>> @@ -14540,6 +14548,13 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>>>  			goto err;
>>>  		}
>>>  		break;
>>> +	case DRM_FORMAT_XYUV:
>>> +		if (INTEL_GEN(dev_priv) < 9) {
>>> +			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
>>> +				      drm_get_format_name(mode_cmd->pixel_format, &format_name));
>>> +			goto err;
>>> +		}
>>> +		break;
>> This hunk isn't needed. DRM core rejects any formats not in the format arrays.
> There is no formats array for addfb. My patches to elimintate this ugly
> code by cross checking with every plane got stuck in limbo.
>
Link?

Lets fix that.

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread
* ✗ Fi.CI.IGT: failure for Add XYUV format support (rev5)
  2018-08-30 14:24 [PATCH v9 0/2] Add XYUV format support Stanislav Lisovskiy
                   ` (5 preceding siblings ...)
  2018-09-04 11:33 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-09-04 13:58 ` Patchwork
  6 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2018-09-04 13:58 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: intel-gfx

== Series Details ==

Series: Add XYUV format support (rev5)
URL   : https://patchwork.freedesktop.org/series/48007/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4763_full -> Patchwork_10078_full =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_10078_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10078_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10078_full:

  === IGT changes ===

    ==== Possible regressions ====

    igt@kms_available_modes_crc@available_mode_test_crc:
      shard-apl:          PASS -> FAIL

    
    ==== Warnings ====

    igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack:
      shard-snb:          SKIP -> PASS

    
== Known issues ==

  Here are the changes found in Patchwork_10078_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_cursor_legacy@cursor-vs-flip-toggle:
      shard-hsw:          PASS -> FAIL (fdo#103355)

    igt@kms_flip@flip-vs-expired-vblank-interruptible:
      shard-glk:          PASS -> FAIL (fdo#102887, fdo#105363)

    igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-plflip-blt:
      shard-glk:          PASS -> FAIL (fdo#103167)

    
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103355 https://bugs.freedesktop.org/show_bug.cgi?id=103355
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4763 -> Patchwork_10078

  CI_DRM_4763: 1f8c06844acac7a349fb80471afcc09f33c6cfc0 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4622: 022be555443eaa3317da6a9a451cf2c9dfcd6ab8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10078: 5c8a6f919689dd4a640ddadc5ba8c0ce07025a45 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10078/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH v9 2/2] drm/i915: Adding YUV444 packed format support for skl+
  2018-09-04 13:52       ` Maarten Lankhorst
@ 2018-09-04 14:06         ` Ville Syrjälä
  0 siblings, 0 replies; 12+ messages in thread
From: Ville Syrjälä @ 2018-09-04 14:06 UTC (permalink / raw)
  To: Maarten Lankhorst
  Cc: intel-gfx, Ville Syrjälä, juha-pekka.heikkila, dri-devel

On Tue, Sep 04, 2018 at 03:52:51PM +0200, Maarten Lankhorst wrote:
> Op 04-09-18 om 15:50 schreef Ville Syrjälä:
> > On Tue, Sep 04, 2018 at 02:47:51PM +0200, Maarten Lankhorst wrote:
> >> Op 30-08-18 om 16:24 schreef Stanislav Lisovskiy:
> >>> PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
> >>> specification.
> >>>
> >>> v2: Edited commit message, removed redundant whitespaces.
> >>>
> >>> v3: Fixed fallthrough logic for the format switch cases.
> >>>
> >>> v4: Yet again fixed fallthrough logic, to reuse code from other case
> >>>     labels.
> >>>
> >>> v5: Started to use XYUV instead of AYUV, as we don't use alpha.
> >>>
> >>> v6: Removed unneeded initializer for new XYUV format.
> >>>
> >>> v7: Added scaling support for DRM_FORMAT_XYUV
> >>>
> >>> v8: Edited commit message to be more clear about skl+, renamed
> >>>     PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
> >>>     doesn't support per-pixel alpha. Fixed minor code issues.
> >>>
> >>> v9: Moved DRM format check to proper place in intel_framebuffer_init.
> >>>
> >>> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> >>> ---
> >>>  drivers/gpu/drm/i915/i915_reg.h      |  2 +-
> >>>  drivers/gpu/drm/i915/intel_display.c | 15 +++++++++++++++
> >>>  drivers/gpu/drm/i915/intel_sprite.c  |  1 +
> >>>  3 files changed, 17 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >>> index 8534f88a60f6..e0c8480aaa02 100644
> >>> --- a/drivers/gpu/drm/i915/i915_reg.h
> >>> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >>> @@ -6499,7 +6499,7 @@ enum {
> >>>  #define   PLANE_CTL_FORMAT_XRGB_2101010		(2 << 24)
> >>>  #define   PLANE_CTL_FORMAT_XRGB_8888		(4 << 24)
> >>>  #define   PLANE_CTL_FORMAT_XRGB_16161616F	(6 << 24)
> >>> -#define   PLANE_CTL_FORMAT_AYUV			(8 << 24)
> >>> +#define   PLANE_CTL_FORMAT_XYUV			(8 << 24)
> >>>  #define   PLANE_CTL_FORMAT_INDEXED		(12 << 24)
> >>>  #define   PLANE_CTL_FORMAT_RGB_565		(14 << 24)
> >>>  #define   ICL_PLANE_CTL_FORMAT_MASK		(0x1f << 23)
> >>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> >>> index 30fdfd1a3037..9323708db71f 100644
> >>> --- a/drivers/gpu/drm/i915/intel_display.c
> >>> +++ b/drivers/gpu/drm/i915/intel_display.c
> >>> @@ -86,6 +86,7 @@ static const uint32_t skl_primary_formats[] = {
> >>>  	DRM_FORMAT_YVYU,
> >>>  	DRM_FORMAT_UYVY,
> >>>  	DRM_FORMAT_VYUY,
> >>> +	DRM_FORMAT_XYUV,
> >>>  };
> >>>  
> >>>  static const uint32_t skl_pri_planar_formats[] = {
> >>> @@ -101,6 +102,7 @@ static const uint32_t skl_pri_planar_formats[] = {
> >>>  	DRM_FORMAT_YVYU,
> >>>  	DRM_FORMAT_UYVY,
> >>>  	DRM_FORMAT_VYUY,
> >>> +	DRM_FORMAT_XYUV,
> >>>  	DRM_FORMAT_NV12,
> >>>  };
> >>>  
> >>> @@ -2672,6 +2674,8 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
> >>>  		return DRM_FORMAT_RGB565;
> >>>  	case PLANE_CTL_FORMAT_NV12:
> >>>  		return DRM_FORMAT_NV12;
> >>> +	case PLANE_CTL_FORMAT_XYUV:
> >>> +		return DRM_FORMAT_XYUV;
> >>>  	default:
> >>>  	case PLANE_CTL_FORMAT_XRGB_8888:
> >>>  		if (rgb_order) {
> >>> @@ -3501,6 +3505,8 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
> >>>  		return PLANE_CTL_FORMAT_XRGB_2101010;
> >>>  	case DRM_FORMAT_XBGR2101010:
> >>>  		return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
> >>> +	case DRM_FORMAT_XYUV:
> >>> +		return PLANE_CTL_FORMAT_XYUV;
> >>>  	case DRM_FORMAT_YUYV:
> >>>  		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
> >>>  	case DRM_FORMAT_YVYU:
> >>> @@ -4959,6 +4965,7 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
> >>>  	case DRM_FORMAT_UYVY:
> >>>  	case DRM_FORMAT_VYUY:
> >>>  	case DRM_FORMAT_NV12:
> >>> +	case DRM_FORMAT_XYUV:
> >>>  		break;
> >>>  	default:
> >>>  		DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
> >>> @@ -13414,6 +13421,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
> >>>  	case DRM_FORMAT_UYVY:
> >>>  	case DRM_FORMAT_VYUY:
> >>>  	case DRM_FORMAT_NV12:
> >>> +	case DRM_FORMAT_XYUV:
> >>>  		if (modifier == I915_FORMAT_MOD_Yf_TILED)
> >>>  			return true;
> >>>  		/* fall through */
> >>> @@ -14540,6 +14548,13 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
> >>>  			goto err;
> >>>  		}
> >>>  		break;
> >>> +	case DRM_FORMAT_XYUV:
> >>> +		if (INTEL_GEN(dev_priv) < 9) {
> >>> +			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
> >>> +				      drm_get_format_name(mode_cmd->pixel_format, &format_name));
> >>> +			goto err;
> >>> +		}
> >>> +		break;
> >> This hunk isn't needed. DRM core rejects any formats not in the format arrays.
> > There is no formats array for addfb. My patches to elimintate this ugly
> > code by cross checking with every plane got stuck in limbo.
> >
> Link?

Two different sort of attempts:

Leave it up to each driver (Eric wasn't keen on taking this for vc4):
https://patchwork.freedesktop.org/series/39701/

Make the core do it unconditionally (more convoluted due to the
legacy tiling->modifier handling):
https://patchwork.freedesktop.org/series/39814/

So not really sure which way we should go. Or maybe there's a less
complex way to do this in the core?

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread
end of thread, other threads:[~2018-09-04 14:06 UTC | newest]

Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-08-30 14:24 [PATCH v9 0/2] Add XYUV format support Stanislav Lisovskiy
2018-08-30 14:24 ` [PATCH v9 1/2] drm: Introduce new DRM_FORMAT_XYUV Stanislav Lisovskiy
2018-08-30 14:24 ` [PATCH v9 2/2] drm/i915: Adding YUV444 packed format support for skl+ Stanislav Lisovskiy
2018-09-04 12:47   ` [Intel-gfx] " Maarten Lankhorst
2018-09-04 13:50     ` Ville Syrjälä
2018-09-04 13:52       ` Maarten Lankhorst
2018-09-04 14:06         ` Ville Syrjälä
2018-08-30 15:30 ` ✗ Fi.CI.CHECKPATCH: warning for Add XYUV format support (rev5) Patchwork
2018-08-30 15:51 ` ✓ Fi.CI.BAT: success " Patchwork
2018-08-30 20:40 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-09-04 11:33 ` ✓ Fi.CI.BAT: success " Patchwork
2018-09-04 13:58 ` ✗ Fi.CI.IGT: failure " Patchwork

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.