[Qemu-devel] [PATCH v2 0/3] 40p: fix PCI interrupt routing

[Qemu-devel] [PATCH v2 0/3] 40p: fix PCI interrupt routing

[Mark Cave-Ayland]

According to the PReP specification section 6.1.6 "System Interrupt
Assignments", all PCI interrupts are routed via IRQ 15.

In the case of the 40p machine this isn't quite true in that it has a routing
quirk: the LSI SCSI device is always routed to IRQ 13. At least Linux and
NetBSD compare the model name presented by the firmware to "IBM PPS Model
6015", and if it matches will active this quirk.

There is also a slight issue in that whilst the legacy PReP machine is still
present in the codebase, the old IRQ routing must still be preserved. This is
done by introducing a new "is-legacy-prep" qdev property to the raven PCI host
bridge which preserves the old routing for -M prep until that code is finally
removed.

In order for guest OSs to make use of the fixed IRQ routing, the model name
in the residual data must be changed in OpenBIOS using the diff below:

diff --git a/arch/ppc/qemu/context.c b/arch/ppc/qemu/context.c
index 06e0122..5815895 100644
--- a/arch/ppc/qemu/context.c
+++ b/arch/ppc/qemu/context.c
@@ -111,7 +111,7 @@ static void *
 residual_build(uint32_t memsize, uint32_t load_base, uint32_t load_size)
 {
     residual_t *res;
-    const unsigned char model[] = "Qemu\0PPC\0";
+    const unsigned char model[] = "IBM PPS Model 6015\0";
     int i;
 
     res = malloc(sizeof(residual_t));

With the above OpenBIOS patch applied as well as this patchset, it is now
possible to boot the sandalfoot zImage all the way through to a working
userspace when using OpenBIOS.

(Note: this patchset requires the changes in my previous patchset "scsi:
replace lsi53c895a_create() and lsi53c810_create() functions)

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Based-on: <20180907125653.5010-1-mark.cave-ayland@ilande.co.uk>

Mark Cave-Ayland (3):
  raven: some minor IRQ-related tidy-ups
  40p: use OR gate to wire up raven PCI interrupts
  40p: add fixed IRQ routing for LSI SCSI device

 hw/pci-host/prep.c | 67 +++++++++++++++++++++++++++++++++++++++++++++++-------
 hw/ppc/prep.c      | 12 ++++++----
 2 files changed, 66 insertions(+), 13 deletions(-)

-- 
2.11.0

[Qemu-devel] [PATCH v2 1/3] raven: some minor IRQ-related tidy-ups

[Mark Cave-Ayland]

This really lays the groundwork for the upcoming patches: it renames the
irqs PREPPCIState struct member to pci_irqs (as soon there will be a
distinction) and then changes the raven IRQ opaque to use PREPPCIState
instead of just irqs array.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
 hw/pci-host/prep.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c
index 88f035c20b..9b36f19c97 100644
--- a/hw/pci-host/prep.c
+++ b/hw/pci-host/prep.c
@@ -55,7 +55,7 @@ typedef struct RavenPCIState {
 typedef struct PRePPCIState {
     PCIHostState parent_obj;
 
-    qemu_irq irq[PCI_NUM_PINS];
+    qemu_irq pci_irqs[PCI_NUM_PINS];
     PCIBus pci_bus;
     AddressSpace pci_io_as;
     MemoryRegion pci_io;
@@ -194,9 +194,9 @@ static int raven_map_irq(PCIDevice *pci_dev, int irq_num)
 
 static void raven_set_irq(void *opaque, int irq_num, int level)
 {
-    qemu_irq *pic = opaque;
+    PREPPCIState *s = opaque;
 
-    qemu_set_irq(pic[irq_num] , level);
+    qemu_set_irq(s->pci_irqs[irq_num], level);
 }
 
 static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque,
@@ -223,13 +223,12 @@ static void raven_pcihost_realizefn(DeviceState *d, Error **errp)
     int i;
 
     for (i = 0; i < PCI_NUM_PINS; i++) {
-        sysbus_init_irq(dev, &s->irq[i]);
+        sysbus_init_irq(dev, &s->pci_irqs[i]);
     }
 
     qdev_init_gpio_in(d, raven_change_gpio, 1);
 
-    pci_bus_irqs(&s->pci_bus, raven_set_irq, raven_map_irq, s->irq,
-                 PCI_NUM_PINS);
+    pci_bus_irqs(&s->pci_bus, raven_set_irq, raven_map_irq, s, PCI_NUM_PINS);
 
     memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, s,
                           "pci-conf-idx", 4);
-- 
2.11.0

[Qemu-devel] [PATCH v2 2/3] 40p: use OR gate to wire up raven PCI interrupts

[Mark Cave-Ayland]

According to the PReP specification section 6.1.6 "System Interrupt
Assignments", all PCI interrupts are routed via IRQ 15.

Instead of mapping each PCI IRQ separately, we introduce an OR gate within the
raven PCI host bridge and then wire the single output of the OR gate to the
interrupt controller.

Note that whilst the (now deprecated) PReP machine still exists we still need
to preserve the old IRQ routing. This is done by adding a new "is-legacy-prep"
property to the raven PCI host bridge which is set to true for the PReP
machine.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
 hw/pci-host/prep.c | 25 +++++++++++++++++++++++--
 hw/ppc/prep.c      |  4 +---
 2 files changed, 24 insertions(+), 5 deletions(-)

diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c
index 9b36f19c97..b1b6b16bad 100644
--- a/hw/pci-host/prep.c
+++ b/hw/pci-host/prep.c
@@ -32,6 +32,7 @@
 #include "hw/pci/pci_host.h"
 #include "hw/i386/pc.h"
 #include "hw/loader.h"
+#include "hw/or-irq.h"
 #include "exec/address-spaces.h"
 #include "elf.h"
 
@@ -55,6 +56,7 @@ typedef struct RavenPCIState {
 typedef struct PRePPCIState {
     PCIHostState parent_obj;
 
+    qemu_or_irq *or_irq;
     qemu_irq pci_irqs[PCI_NUM_PINS];
     PCIBus pci_bus;
     AddressSpace pci_io_as;
@@ -69,6 +71,7 @@ typedef struct PRePPCIState {
     RavenPCIState pci_dev;
 
     int contiguous_map;
+    bool is_legacy_prep;
 } PREPPCIState;
 
 #define BIOS_SIZE (1 * MiB)
@@ -222,8 +225,23 @@ static void raven_pcihost_realizefn(DeviceState *d, Error **errp)
     MemoryRegion *address_space_mem = get_system_memory();
     int i;
 
-    for (i = 0; i < PCI_NUM_PINS; i++) {
-        sysbus_init_irq(dev, &s->pci_irqs[i]);
+    if (s->is_legacy_prep) {
+        for (i = 0; i < PCI_NUM_PINS; i++) {
+            sysbus_init_irq(dev, &s->pci_irqs[i]);
+        }
+    } else {
+        /* According to PReP specification section 6.1.6 "System Interrupt
+         * Assignments", all PCI interrupts are routed via IRQ 15 */
+        s->or_irq = OR_IRQ(object_new(TYPE_OR_IRQ));
+        object_property_set_int(OBJECT(s->or_irq), PCI_NUM_PINS, "num-lines",
+                                &error_fatal);
+        object_property_set_bool(OBJECT(s->or_irq), true, "realized",
+                                 &error_fatal);
+        sysbus_init_irq(dev, &s->or_irq->out_irq);
+
+        for (i = 0; i < PCI_NUM_PINS; i++) {
+            s->pci_irqs[i] = qdev_get_gpio_in(DEVICE(s->or_irq), i);
+        }
     }
 
     qdev_init_gpio_in(d, raven_change_gpio, 1);
@@ -382,6 +400,9 @@ static Property raven_pcihost_properties[] = {
     DEFINE_PROP_UINT32("elf-machine", PREPPCIState, pci_dev.elf_machine,
                        EM_NONE),
     DEFINE_PROP_STRING("bios-name", PREPPCIState, pci_dev.bios_name),
+    /* Temporary workaround until legacy prep machine is removed */
+    DEFINE_PROP_BOOL("is-legacy-prep", PREPPCIState, is_legacy_prep,
+                     false),
     DEFINE_PROP_END_OF_LIST()
 };
 
diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
index b0ea20416e..615865e46c 100644
--- a/hw/ppc/prep.c
+++ b/hw/ppc/prep.c
@@ -502,6 +502,7 @@ static void ppc_prep_init(MachineState *machine)
     }
     qdev_prop_set_string(dev, "bios-name", bios_name);
     qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
+    qdev_prop_set_bit(dev, "is-legacy-prep", true);
     pcihost = PCI_HOST_BRIDGE(dev);
     object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL);
     qdev_init_nofail(dev);
@@ -669,9 +670,6 @@ static void ibm_40p_init(MachineState *machine)
     qdev_connect_gpio_out(dev, 0,
                           cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
     sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(dev, 15));
-    sysbus_connect_irq(pcihost, 1, qdev_get_gpio_in(dev, 13));
-    sysbus_connect_irq(pcihost, 2, qdev_get_gpio_in(dev, 15));
-    sysbus_connect_irq(pcihost, 3, qdev_get_gpio_in(dev, 13));
     isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
 
     /* Memory controller */
-- 
2.11.0

[Qemu-devel] [PATCH v2 3/3] 40p: add fixed IRQ routing for LSI SCSI device

[Mark Cave-Ayland]

Whilst the PReP specification describes how all PCI IRQs are routed via IRQ
15 on the interrupt controller, the real 40p machine has routing quirk in
that the LSI SCSI device is routed to IRQ 13.

This is implemented using a little hack: the existing IRQ routing code uses
(irq_num + (pci_dev->devfn >> 3)) & 1 to give the PCI interrupt pin, where
the "& 1" ensures that the only pins A and B (0 and 1) will ever be used.

Rather than fix the mask to "& 3" we leave the existing routing above as-is
and then force the LSI SCSI device to use pin C (2). This enables us to
route pin 2 permanantly to IRQ 13 since the LSI SCSI device will be its
only user.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
 hw/pci-host/prep.c | 35 +++++++++++++++++++++++++++++++++--
 hw/ppc/prep.c      | 10 +++++++---
 2 files changed, 40 insertions(+), 5 deletions(-)

diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c
index b1b6b16bad..87270605b5 100644
--- a/hw/pci-host/prep.c
+++ b/hw/pci-host/prep.c
@@ -58,6 +58,7 @@ typedef struct PRePPCIState {
 
     qemu_or_irq *or_irq;
     qemu_irq pci_irqs[PCI_NUM_PINS];
+    qemu_irq scsi_irq;
     PCIBus pci_bus;
     AddressSpace pci_io_as;
     MemoryRegion pci_io;
@@ -192,14 +193,41 @@ static const MemoryRegionOps raven_io_ops = {
 
 static int raven_map_irq(PCIDevice *pci_dev, int irq_num)
 {
-    return (irq_num + (pci_dev->devfn >> 3)) & 1;
+    switch (pci_dev->devfn) {
+    case PCI_DEVFN(1, 0):
+        /* Whilst legacy PReP machine exists we need to make
+         * sure that this fixed interrupt routing is 40p only */
+        if (strcmp(object_get_typename(OBJECT(pci_dev)),
+                                       "lsi53c810") == 0) {
+            /* LSI SCSI */
+            return 2;
+        } else {
+            /* Normal PCI IRQ mapping */
+            return (irq_num + (pci_dev->devfn >> 3)) & 1;
+        }
+    default:
+        /* Normal PCI IRQ mapping */
+        return (irq_num + (pci_dev->devfn >> 3)) & 1;
+    }
 }
 
 static void raven_set_irq(void *opaque, int irq_num, int level)
 {
     PREPPCIState *s = opaque;
 
-    qemu_set_irq(s->pci_irqs[irq_num], level);
+    if (s->is_legacy_prep) {
+        qemu_set_irq(s->pci_irqs[irq_num], level);
+    } else {
+        switch (irq_num) {
+        case 2:
+            /* LSI SCSI */
+            qemu_set_irq(s->scsi_irq, level);
+            break;
+        default:
+            /* Normal PCI IRQ mapping */
+            qemu_set_irq(s->pci_irqs[irq_num], level);
+        }
+    }
 }
 
 static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque,
@@ -242,6 +270,9 @@ static void raven_pcihost_realizefn(DeviceState *d, Error **errp)
         for (i = 0; i < PCI_NUM_PINS; i++) {
             s->pci_irqs[i] = qdev_get_gpio_in(DEVICE(s->or_irq), i);
         }
+
+        /* 40p LSI SCSI has fixed routing via IRQ 13 */
+        sysbus_init_irq(dev, &s->scsi_irq);
     }
 
     qdev_init_gpio_in(d, raven_change_gpio, 1);
diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
index 615865e46c..0412a56d98 100644
--- a/hw/ppc/prep.c
+++ b/hw/ppc/prep.c
@@ -626,6 +626,7 @@ static void ibm_40p_init(MachineState *machine)
     Nvram *m48t59 = NULL;
     PCIBus *pci_bus;
     ISABus *isa_bus;
+    PCIDevice *pci;
     void *fw_cfg;
     int i;
     uint32_t kernel_base = 0, initrd_base = 0;
@@ -670,6 +671,7 @@ static void ibm_40p_init(MachineState *machine)
     qdev_connect_gpio_out(dev, 0,
                           cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
     sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(dev, 15));
+    sysbus_connect_irq(pcihost, 1, qdev_get_gpio_in(dev, 13));
     isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
 
     /* Memory controller */
@@ -700,9 +702,11 @@ static void ibm_40p_init(MachineState *machine)
         qdev_prop_set_uint32(dev, "equipment", 0xc0);
         qdev_init_nofail(dev);
 
-        dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(1, 0),
-                                       "lsi53c810"));
-        lsi53c8xx_handle_legacy_cmdline(dev);
+        pci = PCI_DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(1, 0),
+                                           "lsi53c810"));
+        /* Interrupt pin C for fixed LSI SCSI IRQ routing */
+        pci->config[PCI_INTERRUPT_PIN] = 0x3;
+        lsi53c8xx_handle_legacy_cmdline(DEVICE(pci));
 
         /* XXX: s3-trio at PCI_DEVFN(2, 0) */
         pci_vga_init(pci_bus);
-- 
2.11.0

Re: [Qemu-devel] [PATCH v2 1/3] raven: some minor IRQ-related tidy-ups

[Philippe Mathieu-Daudé]

On 9/8/18 6:08 AM, Mark Cave-Ayland wrote:
> This really lays the groundwork for the upcoming patches: it renames the
> irqs PREPPCIState struct member to pci_irqs (as soon there will be a
> distinction) and then changes the raven IRQ opaque to use PREPPCIState
> instead of just irqs array.
> 
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> ---
>  hw/pci-host/prep.c | 11 +++++------
>  1 file changed, 5 insertions(+), 6 deletions(-)
> 
> diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c
> index 88f035c20b..9b36f19c97 100644
> --- a/hw/pci-host/prep.c
> +++ b/hw/pci-host/prep.c
> @@ -55,7 +55,7 @@ typedef struct RavenPCIState {
>  typedef struct PRePPCIState {
>      PCIHostState parent_obj;
>  
> -    qemu_irq irq[PCI_NUM_PINS];
> +    qemu_irq pci_irqs[PCI_NUM_PINS];
>      PCIBus pci_bus;
>      AddressSpace pci_io_as;
>      MemoryRegion pci_io;
> @@ -194,9 +194,9 @@ static int raven_map_irq(PCIDevice *pci_dev, int irq_num)
>  
>  static void raven_set_irq(void *opaque, int irq_num, int level)
>  {
> -    qemu_irq *pic = opaque;
> +    PREPPCIState *s = opaque;
>  
> -    qemu_set_irq(pic[irq_num] , level);
> +    qemu_set_irq(s->pci_irqs[irq_num], level);
>  }
>  
>  static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque,
> @@ -223,13 +223,12 @@ static void raven_pcihost_realizefn(DeviceState *d, Error **errp)
>      int i;
>  
>      for (i = 0; i < PCI_NUM_PINS; i++) {
> -        sysbus_init_irq(dev, &s->irq[i]);
> +        sysbus_init_irq(dev, &s->pci_irqs[i]);
>      }
>  
>      qdev_init_gpio_in(d, raven_change_gpio, 1);
>  
> -    pci_bus_irqs(&s->pci_bus, raven_set_irq, raven_map_irq, s->irq,
> -                 PCI_NUM_PINS);
> +    pci_bus_irqs(&s->pci_bus, raven_set_irq, raven_map_irq, s, PCI_NUM_PINS);
>  
>      memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, s,
>                            "pci-conf-idx", 4);
> 

Re: [Qemu-devel] [PATCH v2 2/3] 40p: use OR gate to wire up raven PCI interrupts

[Philippe Mathieu-Daudé]

On 9/8/18 6:08 AM, Mark Cave-Ayland wrote:
> According to the PReP specification section 6.1.6 "System Interrupt
> Assignments", all PCI interrupts are routed via IRQ 15.
> 
> Instead of mapping each PCI IRQ separately, we introduce an OR gate within the
> raven PCI host bridge and then wire the single output of the OR gate to the
> interrupt controller.

Neat!

> Note that whilst the (now deprecated) PReP machine still exists we still need
> to preserve the old IRQ routing. This is done by adding a new "is-legacy-prep"
> property to the raven PCI host bridge which is set to true for the PReP
> machine.
> 
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> ---
>  hw/pci-host/prep.c | 25 +++++++++++++++++++++++--
>  hw/ppc/prep.c      |  4 +---
>  2 files changed, 24 insertions(+), 5 deletions(-)
> 
> diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c
> index 9b36f19c97..b1b6b16bad 100644
> --- a/hw/pci-host/prep.c
> +++ b/hw/pci-host/prep.c
> @@ -32,6 +32,7 @@
>  #include "hw/pci/pci_host.h"
>  #include "hw/i386/pc.h"
>  #include "hw/loader.h"
> +#include "hw/or-irq.h"
>  #include "exec/address-spaces.h"
>  #include "elf.h"
>  
> @@ -55,6 +56,7 @@ typedef struct RavenPCIState {
>  typedef struct PRePPCIState {
>      PCIHostState parent_obj;
>  
> +    qemu_or_irq *or_irq;
>      qemu_irq pci_irqs[PCI_NUM_PINS];
>      PCIBus pci_bus;
>      AddressSpace pci_io_as;
> @@ -69,6 +71,7 @@ typedef struct PRePPCIState {
>      RavenPCIState pci_dev;
>  
>      int contiguous_map;
> +    bool is_legacy_prep;
>  } PREPPCIState;
>  
>  #define BIOS_SIZE (1 * MiB)
> @@ -222,8 +225,23 @@ static void raven_pcihost_realizefn(DeviceState *d, Error **errp)
>      MemoryRegion *address_space_mem = get_system_memory();
>      int i;
>  
> -    for (i = 0; i < PCI_NUM_PINS; i++) {
> -        sysbus_init_irq(dev, &s->pci_irqs[i]);
> +    if (s->is_legacy_prep) {
> +        for (i = 0; i < PCI_NUM_PINS; i++) {
> +            sysbus_init_irq(dev, &s->pci_irqs[i]);
> +        }
> +    } else {
> +        /* According to PReP specification section 6.1.6 "System Interrupt
> +         * Assignments", all PCI interrupts are routed via IRQ 15 */
> +        s->or_irq = OR_IRQ(object_new(TYPE_OR_IRQ));
> +        object_property_set_int(OBJECT(s->or_irq), PCI_NUM_PINS, "num-lines",
> +                                &error_fatal);
> +        object_property_set_bool(OBJECT(s->or_irq), true, "realized",
> +                                 &error_fatal);
> +        sysbus_init_irq(dev, &s->or_irq->out_irq);
> +
> +        for (i = 0; i < PCI_NUM_PINS; i++) {
> +            s->pci_irqs[i] = qdev_get_gpio_in(DEVICE(s->or_irq), i);
> +        }
>      }
>  
>      qdev_init_gpio_in(d, raven_change_gpio, 1);
> @@ -382,6 +400,9 @@ static Property raven_pcihost_properties[] = {
>      DEFINE_PROP_UINT32("elf-machine", PREPPCIState, pci_dev.elf_machine,
>                         EM_NONE),
>      DEFINE_PROP_STRING("bios-name", PREPPCIState, pci_dev.bios_name),
> +    /* Temporary workaround until legacy prep machine is removed */
> +    DEFINE_PROP_BOOL("is-legacy-prep", PREPPCIState, is_legacy_prep,
> +                     false),
>      DEFINE_PROP_END_OF_LIST()
>  };
>  
> diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
> index b0ea20416e..615865e46c 100644
> --- a/hw/ppc/prep.c
> +++ b/hw/ppc/prep.c
> @@ -502,6 +502,7 @@ static void ppc_prep_init(MachineState *machine)
>      }
>      qdev_prop_set_string(dev, "bios-name", bios_name);
>      qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
> +    qdev_prop_set_bit(dev, "is-legacy-prep", true);
>      pcihost = PCI_HOST_BRIDGE(dev);
>      object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL);
>      qdev_init_nofail(dev);
> @@ -669,9 +670,6 @@ static void ibm_40p_init(MachineState *machine)
>      qdev_connect_gpio_out(dev, 0,
>                            cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
>      sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(dev, 15));
> -    sysbus_connect_irq(pcihost, 1, qdev_get_gpio_in(dev, 13));
> -    sysbus_connect_irq(pcihost, 2, qdev_get_gpio_in(dev, 15));
> -    sysbus_connect_irq(pcihost, 3, qdev_get_gpio_in(dev, 13));
>      isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
>  
>      /* Memory controller */
> 

Re: [Qemu-devel] [PATCH v2 3/3] 40p: add fixed IRQ routing for LSI SCSI device

[Philippe Mathieu-Daudé]

On 9/8/18 6:08 AM, Mark Cave-Ayland wrote:
> Whilst the PReP specification describes how all PCI IRQs are routed via IRQ
> 15 on the interrupt controller, the real 40p machine has routing quirk in
> that the LSI SCSI device is routed to IRQ 13.
> 
> This is implemented using a little hack: the existing IRQ routing code uses
> (irq_num + (pci_dev->devfn >> 3)) & 1 to give the PCI interrupt pin, where
> the "& 1" ensures that the only pins A and B (0 and 1) will ever be used.
> 
> Rather than fix the mask to "& 3" we leave the existing routing above as-is
> and then force the LSI SCSI device to use pin C (2). This enables us to
> route pin 2 permanantly to IRQ 13 since the LSI SCSI device will be its
> only user.
> 
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> ---
>  hw/pci-host/prep.c | 35 +++++++++++++++++++++++++++++++++--
>  hw/ppc/prep.c      | 10 +++++++---
>  2 files changed, 40 insertions(+), 5 deletions(-)
> 
> diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c
> index b1b6b16bad..87270605b5 100644
> --- a/hw/pci-host/prep.c
> +++ b/hw/pci-host/prep.c
> @@ -58,6 +58,7 @@ typedef struct PRePPCIState {
>  
>      qemu_or_irq *or_irq;
>      qemu_irq pci_irqs[PCI_NUM_PINS];
> +    qemu_irq scsi_irq;
>      PCIBus pci_bus;
>      AddressSpace pci_io_as;
>      MemoryRegion pci_io;
> @@ -192,14 +193,41 @@ static const MemoryRegionOps raven_io_ops = {
>  
>  static int raven_map_irq(PCIDevice *pci_dev, int irq_num)
>  {
> -    return (irq_num + (pci_dev->devfn >> 3)) & 1;
> +    switch (pci_dev->devfn) {
> +    case PCI_DEVFN(1, 0):
> +        /* Whilst legacy PReP machine exists we need to make
> +         * sure that this fixed interrupt routing is 40p only */
> +        if (strcmp(object_get_typename(OBJECT(pci_dev)),
> +                                       "lsi53c810") == 0) {
> +            /* LSI SCSI */
> +            return 2;
> +        } else {
> +            /* Normal PCI IRQ mapping */
> +            return (irq_num + (pci_dev->devfn >> 3)) & 1;
> +        }
> +    default:
> +        /* Normal PCI IRQ mapping */
> +        return (irq_num + (pci_dev->devfn >> 3)) & 1;
> +    }
>  }
>  
>  static void raven_set_irq(void *opaque, int irq_num, int level)
>  {
>      PREPPCIState *s = opaque;
>  
> -    qemu_set_irq(s->pci_irqs[irq_num], level);
> +    if (s->is_legacy_prep) {
> +        qemu_set_irq(s->pci_irqs[irq_num], level);
> +    } else {
> +        switch (irq_num) {
> +        case 2:
> +            /* LSI SCSI */
> +            qemu_set_irq(s->scsi_irq, level);
> +            break;
> +        default:
> +            /* Normal PCI IRQ mapping */
> +            qemu_set_irq(s->pci_irqs[irq_num], level);
> +        }
> +    }
>  }
>  
>  static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque,
> @@ -242,6 +270,9 @@ static void raven_pcihost_realizefn(DeviceState *d, Error **errp)
>          for (i = 0; i < PCI_NUM_PINS; i++) {
>              s->pci_irqs[i] = qdev_get_gpio_in(DEVICE(s->or_irq), i);
>          }
> +
> +        /* 40p LSI SCSI has fixed routing via IRQ 13 */
> +        sysbus_init_irq(dev, &s->scsi_irq);
>      }
>  
>      qdev_init_gpio_in(d, raven_change_gpio, 1);
> diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
> index 615865e46c..0412a56d98 100644
> --- a/hw/ppc/prep.c
> +++ b/hw/ppc/prep.c
> @@ -626,6 +626,7 @@ static void ibm_40p_init(MachineState *machine)
>      Nvram *m48t59 = NULL;
>      PCIBus *pci_bus;
>      ISABus *isa_bus;
> +    PCIDevice *pci;
>      void *fw_cfg;
>      int i;
>      uint32_t kernel_base = 0, initrd_base = 0;
> @@ -670,6 +671,7 @@ static void ibm_40p_init(MachineState *machine)
>      qdev_connect_gpio_out(dev, 0,
>                            cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
>      sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(dev, 15));
> +    sysbus_connect_irq(pcihost, 1, qdev_get_gpio_in(dev, 13));
>      isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
>  
>      /* Memory controller */
> @@ -700,9 +702,11 @@ static void ibm_40p_init(MachineState *machine)
>          qdev_prop_set_uint32(dev, "equipment", 0xc0);
>          qdev_init_nofail(dev);
>  
> -        dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(1, 0),
> -                                       "lsi53c810"));
> -        lsi53c8xx_handle_legacy_cmdline(dev);
> +        pci = PCI_DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(1, 0),
> +                                           "lsi53c810"));
> +        /* Interrupt pin C for fixed LSI SCSI IRQ routing */
> +        pci->config[PCI_INTERRUPT_PIN] = 0x3;
> +        lsi53c8xx_handle_legacy_cmdline(DEVICE(pci));
>  
>          /* XXX: s3-trio at PCI_DEVFN(2, 0) */
>          pci_vga_init(pci_bus);
> 

Re: [Qemu-devel] [PATCH v2 0/3] 40p: fix PCI interrupt routing

[Hervé Poussineau]

Le 08/09/2018 à 11:08, Mark Cave-Ayland a écrit :
> According to the PReP specification section 6.1.6 "System Interrupt
> Assignments", all PCI interrupts are routed via IRQ 15.
> 
> In the case of the 40p machine this isn't quite true in that it has a routing
> quirk: the LSI SCSI device is always routed to IRQ 13. At least Linux and
> NetBSD compare the model name presented by the firmware to "IBM PPS Model
> 6015", and if it matches will active this quirk.
> 
> There is also a slight issue in that whilst the legacy PReP machine is still
> present in the codebase, the old IRQ routing must still be preserved. This is
> done by introducing a new "is-legacy-prep" qdev property to the raven PCI host
> bridge which preserves the old routing for -M prep until that code is finally
> removed.
> 

Reviewed-by: Hervé Poussineau <hpoussin@reactos.org>
Tested-by: Hervé Poussineau <hpoussin@reactos.org>

Re: [Qemu-devel] [PATCH v2 3/3] 40p: add fixed IRQ routing for LSI SCSI device

[David Gibson]

[-- Attachment #1: Type: text/plain, Size: 5689 bytes --]

On Sat, Sep 08, 2018 at 10:08:20AM +0100, Mark Cave-Ayland wrote:
> Whilst the PReP specification describes how all PCI IRQs are routed via IRQ
> 15 on the interrupt controller, the real 40p machine has routing quirk in
> that the LSI SCSI device is routed to IRQ 13.
> 
> This is implemented using a little hack: the existing IRQ routing code uses
> (irq_num + (pci_dev->devfn >> 3)) & 1 to give the PCI interrupt pin, where
> the "& 1" ensures that the only pins A and B (0 and 1) will ever be used.
> 
> Rather than fix the mask to "& 3" we leave the existing routing above as-is
> and then force the LSI SCSI device to use pin C (2). This enables us to
> route pin 2 permanantly to IRQ 13 since the LSI SCSI device will be its
> only user.
> 
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>

I don't think this is really the right approach.

As noted in an earlier mail, it's really common for on-board devices
on pre-express PCI boards to have their LSIs wired specially, rather
than via the PCI irq pins which are used for "slotted" devices.

I think we should explicitly model it like that: wiring the SCSI
device's irq directly to system IRQ 13, rather than wiring it via a
PCI LSI pin.

Wiring the SCSI to an otherwise unused pin, then routing that
specially to the system irq is confusing.  It also might be incorrect
if we tried to add a "slotted" device that actually used PINC (rare,
I'll grant you).

> ---
>  hw/pci-host/prep.c | 35 +++++++++++++++++++++++++++++++++--
>  hw/ppc/prep.c      | 10 +++++++---
>  2 files changed, 40 insertions(+), 5 deletions(-)
> 
> diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c
> index b1b6b16bad..87270605b5 100644
> --- a/hw/pci-host/prep.c
> +++ b/hw/pci-host/prep.c
> @@ -58,6 +58,7 @@ typedef struct PRePPCIState {
>  
>      qemu_or_irq *or_irq;
>      qemu_irq pci_irqs[PCI_NUM_PINS];
> +    qemu_irq scsi_irq;
>      PCIBus pci_bus;
>      AddressSpace pci_io_as;
>      MemoryRegion pci_io;
> @@ -192,14 +193,41 @@ static const MemoryRegionOps raven_io_ops = {
>  
>  static int raven_map_irq(PCIDevice *pci_dev, int irq_num)
>  {
> -    return (irq_num + (pci_dev->devfn >> 3)) & 1;
> +    switch (pci_dev->devfn) {
> +    case PCI_DEVFN(1, 0):
> +        /* Whilst legacy PReP machine exists we need to make
> +         * sure that this fixed interrupt routing is 40p only */
> +        if (strcmp(object_get_typename(OBJECT(pci_dev)),
> +                                       "lsi53c810") == 0) {
> +            /* LSI SCSI */
> +            return 2;
> +        } else {
> +            /* Normal PCI IRQ mapping */
> +            return (irq_num + (pci_dev->devfn >> 3)) & 1;
> +        }
> +    default:
> +        /* Normal PCI IRQ mapping */
> +        return (irq_num + (pci_dev->devfn >> 3)) & 1;
> +    }
>  }
>  
>  static void raven_set_irq(void *opaque, int irq_num, int level)
>  {
>      PREPPCIState *s = opaque;
>  
> -    qemu_set_irq(s->pci_irqs[irq_num], level);
> +    if (s->is_legacy_prep) {
> +        qemu_set_irq(s->pci_irqs[irq_num], level);
> +    } else {
> +        switch (irq_num) {
> +        case 2:
> +            /* LSI SCSI */
> +            qemu_set_irq(s->scsi_irq, level);
> +            break;
> +        default:
> +            /* Normal PCI IRQ mapping */
> +            qemu_set_irq(s->pci_irqs[irq_num], level);
> +        }
> +    }
>  }
>  
>  static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque,
> @@ -242,6 +270,9 @@ static void raven_pcihost_realizefn(DeviceState *d, Error **errp)
>          for (i = 0; i < PCI_NUM_PINS; i++) {
>              s->pci_irqs[i] = qdev_get_gpio_in(DEVICE(s->or_irq), i);
>          }
> +
> +        /* 40p LSI SCSI has fixed routing via IRQ 13 */
> +        sysbus_init_irq(dev, &s->scsi_irq);
>      }
>  
>      qdev_init_gpio_in(d, raven_change_gpio, 1);
> diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
> index 615865e46c..0412a56d98 100644
> --- a/hw/ppc/prep.c
> +++ b/hw/ppc/prep.c
> @@ -626,6 +626,7 @@ static void ibm_40p_init(MachineState *machine)
>      Nvram *m48t59 = NULL;
>      PCIBus *pci_bus;
>      ISABus *isa_bus;
> +    PCIDevice *pci;
>      void *fw_cfg;
>      int i;
>      uint32_t kernel_base = 0, initrd_base = 0;
> @@ -670,6 +671,7 @@ static void ibm_40p_init(MachineState *machine)
>      qdev_connect_gpio_out(dev, 0,
>                            cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
>      sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(dev, 15));
> +    sysbus_connect_irq(pcihost, 1, qdev_get_gpio_in(dev, 13));
>      isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
>  
>      /* Memory controller */
> @@ -700,9 +702,11 @@ static void ibm_40p_init(MachineState *machine)
>          qdev_prop_set_uint32(dev, "equipment", 0xc0);
>          qdev_init_nofail(dev);
>  
> -        dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(1, 0),
> -                                       "lsi53c810"));
> -        lsi53c8xx_handle_legacy_cmdline(dev);
> +        pci = PCI_DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(1, 0),
> +                                           "lsi53c810"));
> +        /* Interrupt pin C for fixed LSI SCSI IRQ routing */
> +        pci->config[PCI_INTERRUPT_PIN] = 0x3;
> +        lsi53c8xx_handle_legacy_cmdline(DEVICE(pci));
>  
>          /* XXX: s3-trio at PCI_DEVFN(2, 0) */
>          pci_vga_init(pci_bus);

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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Re: [Qemu-devel] [PATCH v2 0/3] 40p: fix PCI interrupt routing

[David Gibson]

[-- Attachment #1: Type: text/plain, Size: 2632 bytes --]

On Sat, Sep 08, 2018 at 10:08:17AM +0100, Mark Cave-Ayland wrote:
11;rgb:ffff/ffff/ffff> According to the PReP specification section 6.1.6 "System Interrupt
> Assignments", all PCI interrupts are routed via IRQ 15.
> 
> In the case of the 40p machine this isn't quite true in that it has a routing
> quirk: the LSI SCSI device is always routed to IRQ 13. At least Linux and
> NetBSD compare the model name presented by the firmware to "IBM PPS Model
> 6015", and if it matches will active this quirk.
> 
> There is also a slight issue in that whilst the legacy PReP machine is still
> present in the codebase, the old IRQ routing must still be preserved. This is
> done by introducing a new "is-legacy-prep" qdev property to the raven PCI host
> bridge which preserves the old routing for -M prep until that code is finally
> removed.
> 
> In order for guest OSs to make use of the fixed IRQ routing, the model name
> in the residual data must be changed in OpenBIOS using the diff
> below:

I've merged patches 1 & 2.  I don't think 3 has the right approach,
detailed comments there.

> 
> diff --git a/arch/ppc/qemu/context.c b/arch/ppc/qemu/context.c
> index 06e0122..5815895 100644
> --- a/arch/ppc/qemu/context.c
> +++ b/arch/ppc/qemu/context.c
> @@ -111,7 +111,7 @@ static void *
>  residual_build(uint32_t memsize, uint32_t load_base, uint32_t load_size)
>  {
>      residual_t *res;
> -    const unsigned char model[] = "Qemu\0PPC\0";
> +    const unsigned char model[] = "IBM PPS Model 6015\0";
>      int i;
>  
>      res = malloc(sizeof(residual_t));
> 
> With the above OpenBIOS patch applied as well as this patchset, it is now
> possible to boot the sandalfoot zImage all the way through to a working
> userspace when using OpenBIOS.
> 
> (Note: this patchset requires the changes in my previous patchset "scsi:
> replace lsi53c895a_create() and lsi53c810_create() functions)
> 
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> Based-on: <20180907125653.5010-1-mark.cave-ayland@ilande.co.uk>
> 
> Mark Cave-Ayland (3):
>   raven: some minor IRQ-related tidy-ups
>   40p: use OR gate to wire up raven PCI interrupts
>   40p: add fixed IRQ routing for LSI SCSI device
> 
>  hw/pci-host/prep.c | 67 +++++++++++++++++++++++++++++++++++++++++++++++-------
>  hw/ppc/prep.c      | 12 ++++++----
>  2 files changed, 66 insertions(+), 13 deletions(-)
> 

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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Re: [Qemu-devel] [PATCH v2 3/3] 40p: add fixed IRQ routing for LSI SCSI device

[Mark Cave-Ayland]

On 10/09/18 04:48, David Gibson wrote:

> On Sat, Sep 08, 2018 at 10:08:20AM +0100, Mark Cave-Ayland wrote:
>> Whilst the PReP specification describes how all PCI IRQs are routed via IRQ
>> 15 on the interrupt controller, the real 40p machine has routing quirk in
>> that the LSI SCSI device is routed to IRQ 13.
>>
>> This is implemented using a little hack: the existing IRQ routing code uses
>> (irq_num + (pci_dev->devfn >> 3)) & 1 to give the PCI interrupt pin, where
>> the "& 1" ensures that the only pins A and B (0 and 1) will ever be used.
>>
>> Rather than fix the mask to "& 3" we leave the existing routing above as-is
>> and then force the LSI SCSI device to use pin C (2). This enables us to
>> route pin 2 permanantly to IRQ 13 since the LSI SCSI device will be its
>> only user.
>>
>> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> 
> I don't think this is really the right approach.
> 
> As noted in an earlier mail, it's really common for on-board devices
> on pre-express PCI boards to have their LSIs wired specially, rather
> than via the PCI irq pins which are used for "slotted" devices.
> 
> I think we should explicitly model it like that: wiring the SCSI
> device's irq directly to system IRQ 13, rather than wiring it via a
> PCI LSI pin.
> 
> Wiring the SCSI to an otherwise unused pin, then routing that
> specially to the system irq is confusing.  It also might be incorrect
> if we tried to add a "slotted" device that actually used PINC (rare,
> I'll grant you).

Okay. I was hoping to get away with not altering the LSI SCSI device
itself, but after some experimentation I managed to come up with a
solution that is not too invasive and certainly more readable than this
attempt. Let me tidy up and post a v3.


ATB,

Mark.

Re: [Qemu-devel] [PATCH v2 3/3] 40p: add fixed IRQ routing for LSI SCSI device

[Artyom Tarasenko]

On Sat, Sep 8, 2018 at 11:11 AM Mark Cave-Ayland
<mark.cave-ayland@ilande.co.uk> wrote:
>
> Whilst the PReP specification describes how all PCI IRQs are routed via IRQ
> 15 on the interrupt controller, the real 40p machine has routing quirk in
> that the LSI SCSI device is routed to IRQ 13.

Is it a routing quirk or does 40p use both 15 and 13?
I used both in my AIX experiments and AIX seemed to be happy about it.
But maybe AIX simply doesn't care as long as the residual data is correct.

Artyom

> This is implemented using a little hack: the existing IRQ routing code uses
> (irq_num + (pci_dev->devfn >> 3)) & 1 to give the PCI interrupt pin, where
> the "& 1" ensures that the only pins A and B (0 and 1) will ever be used.
>
> Rather than fix the mask to "& 3" we leave the existing routing above as-is
> and then force the LSI SCSI device to use pin C (2). This enables us to
> route pin 2 permanantly to IRQ 13 since the LSI SCSI device will be its
> only user.
>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> ---
>  hw/pci-host/prep.c | 35 +++++++++++++++++++++++++++++++++--
>  hw/ppc/prep.c      | 10 +++++++---
>  2 files changed, 40 insertions(+), 5 deletions(-)
>
> diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c
> index b1b6b16bad..87270605b5 100644
> --- a/hw/pci-host/prep.c
> +++ b/hw/pci-host/prep.c
> @@ -58,6 +58,7 @@ typedef struct PRePPCIState {
>
>      qemu_or_irq *or_irq;
>      qemu_irq pci_irqs[PCI_NUM_PINS];
> +    qemu_irq scsi_irq;
>      PCIBus pci_bus;
>      AddressSpace pci_io_as;
>      MemoryRegion pci_io;
> @@ -192,14 +193,41 @@ static const MemoryRegionOps raven_io_ops = {
>
>  static int raven_map_irq(PCIDevice *pci_dev, int irq_num)
>  {
> -    return (irq_num + (pci_dev->devfn >> 3)) & 1;
> +    switch (pci_dev->devfn) {
> +    case PCI_DEVFN(1, 0):
> +        /* Whilst legacy PReP machine exists we need to make
> +         * sure that this fixed interrupt routing is 40p only */
> +        if (strcmp(object_get_typename(OBJECT(pci_dev)),
> +                                       "lsi53c810") == 0) {
> +            /* LSI SCSI */
> +            return 2;
> +        } else {
> +            /* Normal PCI IRQ mapping */
> +            return (irq_num + (pci_dev->devfn >> 3)) & 1;
> +        }
> +    default:
> +        /* Normal PCI IRQ mapping */
> +        return (irq_num + (pci_dev->devfn >> 3)) & 1;
> +    }
>  }
>
>  static void raven_set_irq(void *opaque, int irq_num, int level)
>  {
>      PREPPCIState *s = opaque;
>
> -    qemu_set_irq(s->pci_irqs[irq_num], level);
> +    if (s->is_legacy_prep) {
> +        qemu_set_irq(s->pci_irqs[irq_num], level);
> +    } else {
> +        switch (irq_num) {
> +        case 2:
> +            /* LSI SCSI */
> +            qemu_set_irq(s->scsi_irq, level);
> +            break;
> +        default:
> +            /* Normal PCI IRQ mapping */
> +            qemu_set_irq(s->pci_irqs[irq_num], level);
> +        }
> +    }
>  }
>
>  static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque,
> @@ -242,6 +270,9 @@ static void raven_pcihost_realizefn(DeviceState *d, Error **errp)
>          for (i = 0; i < PCI_NUM_PINS; i++) {
>              s->pci_irqs[i] = qdev_get_gpio_in(DEVICE(s->or_irq), i);
>          }
> +
> +        /* 40p LSI SCSI has fixed routing via IRQ 13 */
> +        sysbus_init_irq(dev, &s->scsi_irq);
>      }
>
>      qdev_init_gpio_in(d, raven_change_gpio, 1);
> diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
> index 615865e46c..0412a56d98 100644
> --- a/hw/ppc/prep.c
> +++ b/hw/ppc/prep.c
> @@ -626,6 +626,7 @@ static void ibm_40p_init(MachineState *machine)
>      Nvram *m48t59 = NULL;
>      PCIBus *pci_bus;
>      ISABus *isa_bus;
> +    PCIDevice *pci;
>      void *fw_cfg;
>      int i;
>      uint32_t kernel_base = 0, initrd_base = 0;
> @@ -670,6 +671,7 @@ static void ibm_40p_init(MachineState *machine)
>      qdev_connect_gpio_out(dev, 0,
>                            cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
>      sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(dev, 15));
> +    sysbus_connect_irq(pcihost, 1, qdev_get_gpio_in(dev, 13));
>      isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
>
>      /* Memory controller */
> @@ -700,9 +702,11 @@ static void ibm_40p_init(MachineState *machine)
>          qdev_prop_set_uint32(dev, "equipment", 0xc0);
>          qdev_init_nofail(dev);
>
> -        dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(1, 0),
> -                                       "lsi53c810"));
> -        lsi53c8xx_handle_legacy_cmdline(dev);
> +        pci = PCI_DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(1, 0),
> +                                           "lsi53c810"));
> +        /* Interrupt pin C for fixed LSI SCSI IRQ routing */
> +        pci->config[PCI_INTERRUPT_PIN] = 0x3;
> +        lsi53c8xx_handle_legacy_cmdline(DEVICE(pci));
>
>          /* XXX: s3-trio at PCI_DEVFN(2, 0) */
>          pci_vga_init(pci_bus);
> --
> 2.11.0
>
>


-- 
Regards,
Artyom Tarasenko

SPARC and PPC PReP under qemu blog: http://tyom.blogspot.com/search/label/qemu

Re: [Qemu-devel] [PATCH v2 3/3] 40p: add fixed IRQ routing for LSI SCSI device

[Mark Cave-Ayland]

On 13/09/18 15:21, Artyom Tarasenko wrote:

> On Sat, Sep 8, 2018 at 11:11 AM Mark Cave-Ayland
> <mark.cave-ayland@ilande.co.uk> wrote:
>>
>> Whilst the PReP specification describes how all PCI IRQs are routed via IRQ
>> 15 on the interrupt controller, the real 40p machine has routing quirk in
>> that the LSI SCSI device is routed to IRQ 13.
> 
> Is it a routing quirk or does 40p use both 15 and 13?
> I used both in my AIX experiments and AIX seemed to be happy about it.
> But maybe AIX simply doesn't care as long as the residual data is correct.
> 
> Artyom

If you boot the Linux sandalfoot zImage then you can see the LSI IRQ
change from 15 to 13 just by changing the model name in OpenBIOS to
match that of a real 40p (compare with
http://www.juneau-lug.org/sandalfoot.php). There's also similar code
that you can see in NetBSD.

My guess would be that AIX does the "right thing" and parses the
residual data correctly as expected.


ATB,

Mark.

Re: [Qemu-devel] [PATCH v2 3/3] 40p: add fixed IRQ routing for LSI SCSI device

[Artyom Tarasenko]

On Thu, Sep 13, 2018 at 5:30 PM Mark Cave-Ayland
<mark.cave-ayland@ilande.co.uk> wrote:
>
> On 13/09/18 15:21, Artyom Tarasenko wrote:
>
> > On Sat, Sep 8, 2018 at 11:11 AM Mark Cave-Ayland
> > <mark.cave-ayland@ilande.co.uk> wrote:
> >>
> >> Whilst the PReP specification describes how all PCI IRQs are routed via IRQ
> >> 15 on the interrupt controller, the real 40p machine has routing quirk in
> >> that the LSI SCSI device is routed to IRQ 13.
> >
> > Is it a routing quirk or does 40p use both 15 and 13?
> > I used both in my AIX experiments and AIX seemed to be happy about it.
> > But maybe AIX simply doesn't care as long as the residual data is correct.
> >
> > Artyom
>
> If you boot the Linux sandalfoot zImage then you can see the LSI IRQ
> change from 15 to 13 just by changing the model name in OpenBIOS to
> match that of a real 40p (compare with
> http://www.juneau-lug.org/sandalfoot.php). There's also similar code
> that you can see in NetBSD.
>
> My guess would be that AIX does the "right thing" and parses the
> residual data correctly as expected.

This does indeed make sense.

Reviewed-by: Artyom Tarasenko <atar4qemu@gmail.com>

-- 
Regards,
Artyom Tarasenko

SPARC and PPC PReP under qemu blog: http://tyom.blogspot.com/search/label/qemu