From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from kirsty.vergenet.net ([202.4.237.240]:36529 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726995AbeIQNRO (ORCPT ); Mon, 17 Sep 2018 09:17:14 -0400 Date: Mon, 17 Sep 2018 09:50:55 +0200 From: Simon Horman To: Laurent Pinchart Cc: dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, Ulrich Hecht , Kieran Bingham Subject: Re: [PATCH v2 13/16] arm64: dts: renesas: r8a77990: Add display output support Message-ID: <20180917075054.gnfepzxxaxzb46mg@verge.net.au> References: <20180914091046.483-1-laurent.pinchart+renesas@ideasonboard.com> <20180914091046.483-14-laurent.pinchart+renesas@ideasonboard.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20180914091046.483-14-laurent.pinchart+renesas@ideasonboard.com> Sender: linux-renesas-soc-owner@vger.kernel.org List-ID: On Fri, Sep 14, 2018 at 12:10:43PM +0300, Laurent Pinchart wrote: > The R8A77990 (E3) platform has one RGB output and two LVDS outputs > connected to the DU. Add the DT nodes for the DU, LVDS encoders and > supporting VSP and FCP. > > Signed-off-by: Laurent Pinchart > Tested-by: Jacopo Mondi > --- > arch/arm64/boot/dts/renesas/r8a77990.dtsi | 167 ++++++++++++++++++++++++++++++ > 1 file changed, 167 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi > index abb14af76c0e..600074ca3ee5 100644 > --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi > @@ -537,6 +537,173 @@ > resets = <&cpg 408>; > }; These nodes should be placed after the gic to preserve the sorting of nodes by bus address and then IP block. > + vspb0: vsp@fe960000 { > + compatible = "renesas,vsp2"; > + reg = <0 0xfe960000 0 0x8000>; > + interrupts = ; > + clocks = <&cpg CPG_MOD 626>; > + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; > + resets = <&cpg 626>; > + renesas,fcp = <&fcpvb0>; > + }; > + > + fcpvb0: fcp@fe96f000 { > + compatible = "renesas,fcpv"; > + reg = <0 0xfe96f000 0 0x200>; > + clocks = <&cpg CPG_MOD 607>; > + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; > + resets = <&cpg 607>; > + iommus = <&ipmmu_vp0 5>; > + }; > + > + vspi0: vsp@fe9a0000 { > + compatible = "renesas,vsp2"; > + reg = <0 0xfe9a0000 0 0x8000>; > + interrupts = ; > + clocks = <&cpg CPG_MOD 622>; R-Car Series, 3rd Generation, v1.00, Table Table 8A.21 indicates that this clock should be <&cpg CPG_MOD 631>. The clock above is (according to my reading of the documentation) correctly used for vspd1 below. > + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; > + resets = <&cpg 631>; > + renesas,fcp = <&fcpvi0>; > + }; > + > + fcpvi0: fcp@fe9af000 { > + compatible = "renesas,fcpv"; > + reg = <0 0xfe9af000 0 0x200>; > + clocks = <&cpg CPG_MOD 611>; > + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; > + resets = <&cpg 611>; > + iommus = <&ipmmu_vp0 8>; > + }; > + > + vspd0: vsp@fea20000 { > + compatible = "renesas,vsp2"; > + reg = <0 0xfea20000 0 0x7000>; > + interrupts = ; > + clocks = <&cpg CPG_MOD 623>; > + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; > + resets = <&cpg 623>; > + renesas,fcp = <&fcpvd0>; > + }; > + > + fcpvd0: fcp@fea27000 { > + compatible = "renesas,fcpv"; > + reg = <0 0xfea27000 0 0x200>; > + clocks = <&cpg CPG_MOD 603>; > + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; > + resets = <&cpg 603>; > + iommus = <&ipmmu_vi0 8>; > + }; > + > + vspd1: vsp@fea28000 { > + compatible = "renesas,vsp2"; > + reg = <0 0xfea28000 0 0x7000>; > + interrupts = ; > + clocks = <&cpg CPG_MOD 622>; > + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; > + resets = <&cpg 622>; > + renesas,fcp = <&fcpvd1>; > + }; > + > + fcpvd1: fcp@fea2f000 { > + compatible = "renesas,fcpv"; > + reg = <0 0xfea2f000 0 0x200>; > + clocks = <&cpg CPG_MOD 602>; > + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; > + resets = <&cpg 602>; > + iommus = <&ipmmu_vi0 9>; > + }; > + > + du: display@feb00000 { > + compatible = "renesas,du-r8a77990"; > + reg = <0 0xfeb00000 0 0x80000>; > + interrupts = , > + ; > + clocks = <&cpg CPG_MOD 724>, > + <&cpg CPG_MOD 723>; > + clock-names = "du.0", "du.1"; > + vsps = <&vspd0 0 &vspd1 0>; > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + du_out_rgb: endpoint { > + }; > + }; > + > + port@1 { > + reg = <1>; > + du_out_lvds0: endpoint { > + remote-endpoint = <&lvds0_in>; > + }; > + }; > + > + port@2 { > + reg = <2>; > + du_out_lvds1: endpoint { > + remote-endpoint = <&lvds1_in>; > + }; > + }; > + }; > + }; > + > + lvds0: lvds-encoder@feb90000 { > + compatible = "renesas,r8a77990-lvds"; > + reg = <0 0xfeb90000 0 0x20>; > + clocks = <&cpg CPG_MOD 727>; > + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; > + resets = <&cpg 727>; > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + lvds0_in: endpoint { > + remote-endpoint = <&du_out_lvds0>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + lvds0_out: endpoint { > + }; > + }; > + }; > + }; > + > + lvds1: lvds-encoder@feb90100 { > + compatible = "renesas,r8a77990-lvds"; > + reg = <0 0xfeb90100 0 0x20>; > + clocks = <&cpg CPG_MOD 727>; > + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; > + resets = <&cpg 726>; > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + lvds1_in: endpoint { > + remote-endpoint = <&du_out_lvds1>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + lvds1_out: endpoint { > + }; > + }; > + }; > + }; > + > prr: chipid@fff00044 { > compatible = "renesas,prr"; > reg = <0 0xfff00044 0 4>; > -- > Regards, > > Laurent Pinchart > From mboxrd@z Thu Jan 1 00:00:00 1970 From: Simon Horman Subject: Re: [PATCH v2 13/16] arm64: dts: renesas: r8a77990: Add display output support Date: Mon, 17 Sep 2018 09:50:55 +0200 Message-ID: <20180917075054.gnfepzxxaxzb46mg@verge.net.au> References: <20180914091046.483-1-laurent.pinchart+renesas@ideasonboard.com> <20180914091046.483-14-laurent.pinchart+renesas@ideasonboard.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from kirsty.vergenet.net (kirsty.vergenet.net [202.4.237.240]) by gabe.freedesktop.org (Postfix) with ESMTP id 9F6FB8914D for ; Mon, 17 Sep 2018 07:50:59 +0000 (UTC) Content-Disposition: inline In-Reply-To: <20180914091046.483-14-laurent.pinchart+renesas@ideasonboard.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Laurent Pinchart Cc: linux-renesas-soc@vger.kernel.org, Ulrich Hecht , Kieran Bingham , dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org T24gRnJpLCBTZXAgMTQsIDIwMTggYXQgMTI6MTA6NDNQTSArMDMwMCwgTGF1cmVudCBQaW5jaGFy dCB3cm90ZToKPiBUaGUgUjhBNzc5OTAgKEUzKSBwbGF0Zm9ybSBoYXMgb25lIFJHQiBvdXRwdXQg YW5kIHR3byBMVkRTIG91dHB1dHMKPiBjb25uZWN0ZWQgdG8gdGhlIERVLiBBZGQgdGhlIERUIG5v ZGVzIGZvciB0aGUgRFUsIExWRFMgZW5jb2RlcnMgYW5kCj4gc3VwcG9ydGluZyBWU1AgYW5kIEZD UC4KPiAKPiBTaWduZWQtb2ZmLWJ5OiBMYXVyZW50IFBpbmNoYXJ0IDxsYXVyZW50LnBpbmNoYXJ0 K3JlbmVzYXNAaWRlYXNvbmJvYXJkLmNvbT4KPiBUZXN0ZWQtYnk6IEphY29wbyBNb25kaSA8amFj b3BvK3JlbmVzYXNAam1vbmRpLm9yZz4KPiAtLS0KPiAgYXJjaC9hcm02NC9ib290L2R0cy9yZW5l c2FzL3I4YTc3OTkwLmR0c2kgfCAxNjcgKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrCj4g 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