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From: Bibby Hsieh <bibby.hsieh@mediatek.com>
To: David Airlie <airlied@linux.ie>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Daniel Vetter <daniel.vetter@ffwll.ch>,
	<dri-devel@lists.freedesktop.org>,
	<linux-mediatek@lists.infradead.org>
Cc: Yingjoe Chen <yingjoe.chen@mediatek.com>,
	Cawa Cheng <cawa.cheng@mediatek.com>,
	Daniel Kurtz <djkurtz@chromium.org>,
	Bibby Hsieh <bibby.hsieh@mediatek.com>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	YT Shen <yt.shen@mediatek.com>,
	Thierry Reding <thierry.reding@gmail.com>,
	CK Hu <ck.hu@mediatek.com>, Mao Huang <littlecvr@chromium.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	Sascha Hauer <kernel@pengutronix.de>,
	chunhui dai <chunhui.dai@mediatek.com>
Subject: [PATCH v3 03/12] drm/mediatek: adjust EDGE to match clock and data
Date: Fri, 21 Sep 2018 11:28:13 +0800	[thread overview]
Message-ID: <20180921032822.30771-4-bibby.hsieh@mediatek.com> (raw)
In-Reply-To: <20180921032822.30771-1-bibby.hsieh@mediatek.com>

From: chunhui dai <chunhui.dai@mediatek.com>

The default timing of DPI data and clock is not match.
We could adjust this bit to make them match.

Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c      | 8 ++++++++
 drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 1 +
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 74a32833bde1..1e7369e0d91c 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -121,6 +121,7 @@ struct mtk_dpi_yc_limit {
 
 struct mtk_dpi_conf {
 	u32 reg_h_fre_con;
+	bool edge_sel_en;
 };
 
 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
@@ -351,6 +352,12 @@ static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
 	mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
 }
 
+static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi)
+{
+	if (dpi->conf->edge_sel_en)
+		mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN);
+}
+
 static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
 					enum mtk_dpi_out_color_format format)
 {
@@ -536,6 +543,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
 	mtk_dpi_config_yc_map(dpi, dpi->yc_map);
 	mtk_dpi_config_color_format(dpi, dpi->color_format);
 	mtk_dpi_config_2n_h_fre(dpi);
+	mtk_dpi_config_disable_edge(dpi);
 	mtk_dpi_sw_reset(dpi, false);
 
 	return 0;
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
index 040444d7718d..d9db8c4cacd7 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
+++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
@@ -223,5 +223,6 @@
 #define ESAV_CODE2			(0xFFF << 0)
 #define ESAV_CODE3_MSB			BIT(16)
 
+#define EDGE_SEL_EN			BIT(5)
 #define H_FRE_2N			BIT(25)
 #endif /* __MTK_DPI_REGS_H */
-- 
2.12.5.2.gbdf23ab


WARNING: multiple messages have this Message-ID (diff)
From: Bibby Hsieh <bibby.hsieh@mediatek.com>
To: David Airlie <airlied@linux.ie>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Daniel Vetter <daniel.vetter@ffwll.ch>,
	dri-devel@lists.freedesktop.org,
	linux-mediatek@lists.infradead.org
Cc: chunhui dai <chunhui.dai@mediatek.com>,
	linux-kernel@vger.kernel.org,
	Cawa Cheng <cawa.cheng@mediatek.com>,
	Mao Huang <littlecvr@chromium.org>,
	Thierry Reding <thierry.reding@gmail.com>,
	Yingjoe Chen <yingjoe.chen@mediatek.com>,
	Sascha Hauer <kernel@pengutronix.de>,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 03/12] drm/mediatek: adjust EDGE to match clock and data
Date: Fri, 21 Sep 2018 11:28:13 +0800	[thread overview]
Message-ID: <20180921032822.30771-4-bibby.hsieh@mediatek.com> (raw)
In-Reply-To: <20180921032822.30771-1-bibby.hsieh@mediatek.com>

From: chunhui dai <chunhui.dai@mediatek.com>

The default timing of DPI data and clock is not match.
We could adjust this bit to make them match.

Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c      | 8 ++++++++
 drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 1 +
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 74a32833bde1..1e7369e0d91c 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -121,6 +121,7 @@ struct mtk_dpi_yc_limit {
 
 struct mtk_dpi_conf {
 	u32 reg_h_fre_con;
+	bool edge_sel_en;
 };
 
 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
@@ -351,6 +352,12 @@ static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
 	mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
 }
 
+static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi)
+{
+	if (dpi->conf->edge_sel_en)
+		mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN);
+}
+
 static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
 					enum mtk_dpi_out_color_format format)
 {
@@ -536,6 +543,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
 	mtk_dpi_config_yc_map(dpi, dpi->yc_map);
 	mtk_dpi_config_color_format(dpi, dpi->color_format);
 	mtk_dpi_config_2n_h_fre(dpi);
+	mtk_dpi_config_disable_edge(dpi);
 	mtk_dpi_sw_reset(dpi, false);
 
 	return 0;
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
index 040444d7718d..d9db8c4cacd7 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
+++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
@@ -223,5 +223,6 @@
 #define ESAV_CODE2			(0xFFF << 0)
 #define ESAV_CODE3_MSB			BIT(16)
 
+#define EDGE_SEL_EN			BIT(5)
 #define H_FRE_2N			BIT(25)
 #endif /* __MTK_DPI_REGS_H */
-- 
2.12.5.2.gbdf23ab

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

WARNING: multiple messages have this Message-ID (diff)
From: bibby.hsieh@mediatek.com (Bibby Hsieh)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 03/12] drm/mediatek: adjust EDGE to match clock and data
Date: Fri, 21 Sep 2018 11:28:13 +0800	[thread overview]
Message-ID: <20180921032822.30771-4-bibby.hsieh@mediatek.com> (raw)
In-Reply-To: <20180921032822.30771-1-bibby.hsieh@mediatek.com>

From: chunhui dai <chunhui.dai@mediatek.com>

The default timing of DPI data and clock is not match.
We could adjust this bit to make them match.

Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c      | 8 ++++++++
 drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 1 +
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 74a32833bde1..1e7369e0d91c 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -121,6 +121,7 @@ struct mtk_dpi_yc_limit {
 
 struct mtk_dpi_conf {
 	u32 reg_h_fre_con;
+	bool edge_sel_en;
 };
 
 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
@@ -351,6 +352,12 @@ static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
 	mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
 }
 
+static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi)
+{
+	if (dpi->conf->edge_sel_en)
+		mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN);
+}
+
 static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
 					enum mtk_dpi_out_color_format format)
 {
@@ -536,6 +543,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
 	mtk_dpi_config_yc_map(dpi, dpi->yc_map);
 	mtk_dpi_config_color_format(dpi, dpi->color_format);
 	mtk_dpi_config_2n_h_fre(dpi);
+	mtk_dpi_config_disable_edge(dpi);
 	mtk_dpi_sw_reset(dpi, false);
 
 	return 0;
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
index 040444d7718d..d9db8c4cacd7 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
+++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
@@ -223,5 +223,6 @@
 #define ESAV_CODE2			(0xFFF << 0)
 #define ESAV_CODE3_MSB			BIT(16)
 
+#define EDGE_SEL_EN			BIT(5)
 #define H_FRE_2N			BIT(25)
 #endif /* __MTK_DPI_REGS_H */
-- 
2.12.5.2.gbdf23ab

  parent reply	other threads:[~2018-09-21  3:29 UTC|newest]

Thread overview: 57+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-09-21  3:28 [PATCH v3 00/13] drm/mediatek: support hdmi output for mt2701 and mt7623 Bibby Hsieh
2018-09-21  3:28 ` Bibby Hsieh
2018-09-21  3:28 ` Bibby Hsieh
2018-09-21  3:28 ` [PATCH v3 01/12] drm/mediatek: add refcount for DPI power on/off Bibby Hsieh
2018-09-21  3:28   ` Bibby Hsieh
2018-09-21  3:28   ` Bibby Hsieh
2018-09-21  6:18   ` CK Hu
2018-09-21  6:18     ` CK Hu
2018-09-21  6:18     ` CK Hu
2018-09-21  3:28 ` [PATCH v3 02/12] drm/mediatek: move hardware register to node data Bibby Hsieh
2018-09-21  3:28   ` Bibby Hsieh
2018-09-21  3:28   ` Bibby Hsieh
2018-09-21  7:39   ` CK Hu
2018-09-21  7:39     ` CK Hu
2018-09-21  7:39     ` CK Hu
2018-09-21  3:28 ` Bibby Hsieh [this message]
2018-09-21  3:28   ` [PATCH v3 03/12] drm/mediatek: adjust EDGE to match clock and data Bibby Hsieh
2018-09-21  3:28   ` Bibby Hsieh
2018-09-21  3:28 ` [PATCH v3 04/12] drm/mediatek: add clock factor for different IC Bibby Hsieh
2018-09-21  3:28   ` Bibby Hsieh
2018-09-21  3:28   ` Bibby Hsieh
2018-09-21  9:03   ` CK Hu
2018-09-21  9:03     ` CK Hu
2018-09-21  9:03     ` CK Hu
2018-09-21  3:28 ` [PATCH v3 05/12] drm/mediatek: convert dpi driver to use drm_of_find_panel_or_bridge Bibby Hsieh
2018-09-21  3:28   ` Bibby Hsieh
2018-09-21  3:28   ` Bibby Hsieh
2018-09-21  9:47   ` CK Hu
2018-09-21  9:47     ` CK Hu
2018-09-21  9:47     ` CK Hu
2018-09-21  3:28 ` [PATCH v3 06/12] drm/mediatek: add dpi driver for mt2701 and mt7623 Bibby Hsieh
2018-09-21  3:28   ` Bibby Hsieh
2018-09-21  3:28   ` Bibby Hsieh
2018-09-21  9:50   ` CK Hu
2018-09-21  9:50     ` CK Hu
2018-09-21  9:50     ` CK Hu
2018-09-21  3:28 ` [PATCH v3 07/12] drm/mediatek: separate hdmi phy to different file Bibby Hsieh
2018-09-21  3:28   ` Bibby Hsieh
2018-09-21  3:28   ` Bibby Hsieh
2018-09-21  3:28 ` [PATCH v3 08/12] drm/mediatek: add support for SPDIF audio in HDMI Bibby Hsieh
2018-09-21  3:28   ` Bibby Hsieh
2018-09-21  3:28   ` Bibby Hsieh
2018-09-21  3:28 ` [PATCH v3 09/12] drm/mediatek: add hdmi driver for MT2701 and MT7623 Bibby Hsieh
2018-09-21  3:28   ` Bibby Hsieh
2018-09-21  3:28   ` Bibby Hsieh
2018-09-21 10:10   ` CK Hu
2018-09-21 10:10     ` CK Hu
2018-09-21 10:10     ` CK Hu
2018-09-21  3:28 ` [PATCH v3 10/12] drm/mediatek: implement connection from BLS to DPI0 Bibby Hsieh
2018-09-21  3:28   ` Bibby Hsieh
2018-09-21  3:28   ` Bibby Hsieh
2018-09-21  3:28 ` [PATCH v3 11/12] drm/mediatek: add a error return value when clock driver has been prepared Bibby Hsieh
2018-09-21  3:28   ` Bibby Hsieh
2018-09-21  3:28   ` Bibby Hsieh
2018-09-21  3:28 ` [PATCH v3 12/12] drm/mediatek: config component output by device node port Bibby Hsieh
2018-09-21  3:28   ` Bibby Hsieh
2018-09-21  3:28   ` Bibby Hsieh

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