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* [PATCH v4] drm/i915: Remove i915.enable_ppgtt override
@ 2018-09-25 11:48 Chris Wilson
  2018-09-25 12:06 ` ✗ Fi.CI.SPARSE: warning for " Patchwork
                   ` (8 more replies)
  0 siblings, 9 replies; 24+ messages in thread
From: Chris Wilson @ 2018-09-25 11:48 UTC (permalink / raw)
  To: intel-gfx; +Cc: Matthew Auld

Now that we are confident in providing full-ppgtt where supported,
remove the ability to override the context isolation.

v2: Remove faked aliasing-ppgtt for testing as it no longer is accepted.
v3: s/USES/HAS/ to match usage and reject attempts to load the module on
old GVT-g setups that do not provide support for full-ppgtt.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c               | 22 +++--
 drivers/gpu/drm/i915/i915_drv.h               | 14 +--
 drivers/gpu/drm/i915/i915_gem_context.c       |  2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c           | 88 ++-----------------
 drivers/gpu/drm/i915/i915_gpu_error.c         |  4 +-
 drivers/gpu/drm/i915/i915_params.c            |  4 -
 drivers/gpu/drm/i915/i915_params.h            |  1 -
 drivers/gpu/drm/i915/i915_pci.c               | 17 ++--
 drivers/gpu/drm/i915/intel_device_info.c      |  6 ++
 drivers/gpu/drm/i915/intel_device_info.h      | 11 ++-
 drivers/gpu/drm/i915/intel_lrc.c              | 13 ++-
 drivers/gpu/drm/i915/selftests/huge_pages.c   | 12 +--
 .../gpu/drm/i915/selftests/i915_gem_context.c | 59 +------------
 .../gpu/drm/i915/selftests/i915_gem_evict.c   |  2 +-
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |  4 +-
 15 files changed, 62 insertions(+), 197 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 44e2c0f5ec50..3efbbc71c3b4 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -345,7 +345,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
 		value = HAS_WT(dev_priv);
 		break;
 	case I915_PARAM_HAS_ALIASING_PPGTT:
-		value = USES_PPGTT(dev_priv);
+		value = INTEL_PPGTT(dev_priv);
 		break;
 	case I915_PARAM_HAS_SEMAPHORES:
 		value = HAS_LEGACY_SEMAPHORES(dev_priv);
@@ -1049,17 +1049,6 @@ static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
 
 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 {
-	/*
-	 * i915.enable_ppgtt is read-only, so do an early pass to validate the
-	 * user's requested state against the hardware/driver capabilities.  We
-	 * do this now so that we can print out any log messages once rather
-	 * than every time we check intel_enable_ppgtt().
-	 */
-	i915_modparams.enable_ppgtt =
-		intel_sanitize_enable_ppgtt(dev_priv,
-					    i915_modparams.enable_ppgtt);
-	DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
-
 	intel_gvt_sanitize_options(dev_priv);
 }
 
@@ -1374,6 +1363,15 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
 
 	intel_device_info_runtime_init(mkwrite_device_info(dev_priv));
 
+	if (HAS_PPGTT(dev_priv)) {
+		if (intel_vgpu_active(dev_priv) &&
+		    !intel_vgpu_has_full_48bit_ppgtt(dev_priv)) {
+			i915_report_error(dev_priv,
+					  "incompatible vGPU found, support for isolated ppGTT required\n");
+			return -ENXIO;
+		}
+	}
+
 	intel_sanitize_options(dev_priv);
 
 	i915_perf_init(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8624b4bdc242..f28b3c2a3cd2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2593,9 +2593,14 @@ intel_info(const struct drm_i915_private *dev_priv)
 
 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
 
-#define USES_PPGTT(dev_priv)		(i915_modparams.enable_ppgtt)
-#define USES_FULL_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt >= 2)
-#define USES_FULL_48BIT_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt == 3)
+#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt)
+#define HAS_PPGTT(dev_priv) \
+	(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
+#define HAS_FULL_PPGTT(dev_priv) \
+	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
+#define HAS_FULL_48BIT_PPGTT(dev_priv)	\
+	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL_4LVL)
+
 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
 	GEM_BUG_ON((sizes) == 0); \
 	((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
@@ -2743,9 +2748,6 @@ intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
 	return IS_BROXTON(dev_priv) && intel_vtd_active();
 }
 
-int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
-				int enable_ppgtt);
-
 /* i915_drv.c */
 void __printf(3, 4)
 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index f772593b99ab..15c92f75b1b8 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -414,7 +414,7 @@ i915_gem_create_context(struct drm_i915_private *dev_priv,
 	if (IS_ERR(ctx))
 		return ctx;
 
-	if (USES_FULL_PPGTT(dev_priv)) {
+	if (HAS_FULL_PPGTT(dev_priv)) {
 		struct i915_hw_ppgtt *ppgtt;
 
 		ppgtt = i915_ppgtt_create(dev_priv, file_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index f6c7ab413081..c9363504949f 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -133,55 +133,6 @@ static inline void i915_ggtt_invalidate(struct drm_i915_private *i915)
 	i915->ggtt.invalidate(i915);
 }
 
-int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
-			       	int enable_ppgtt)
-{
-	bool has_full_ppgtt;
-	bool has_full_48bit_ppgtt;
-
-	if (!dev_priv->info.has_aliasing_ppgtt)
-		return 0;
-
-	has_full_ppgtt = dev_priv->info.has_full_ppgtt;
-	has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt;
-
-	if (intel_vgpu_active(dev_priv)) {
-		/* GVT-g has no support for 32bit ppgtt */
-		has_full_ppgtt = false;
-		has_full_48bit_ppgtt = intel_vgpu_has_full_48bit_ppgtt(dev_priv);
-	}
-
-	/*
-	 * We don't allow disabling PPGTT for gen8+ as it's a requirement for
-	 * execlists, the sole mechanism available to submit work.
-	 */
-	if (enable_ppgtt == 0 && !HAS_EXECLISTS(dev_priv))
-		return 0;
-
-	if (enable_ppgtt == 1)
-		return 1;
-
-	if (enable_ppgtt == 2 && has_full_ppgtt)
-		return 2;
-
-	if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
-		return 3;
-
-	/* Disable ppgtt on SNB if VT-d is on. */
-	if (IS_GEN6(dev_priv) && intel_vtd_active()) {
-		DRM_INFO("Disabling PPGTT because VT-d is on\n");
-		return 0;
-	}
-
-	if (has_full_48bit_ppgtt)
-		return 3;
-
-	if (has_full_ppgtt)
-		return 2;
-
-	return 1;
-}
-
 static int ppgtt_bind_vma(struct i915_vma *vma,
 			  enum i915_cache_level cache_level,
 			  u32 unused)
@@ -1647,7 +1598,7 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
 	ppgtt->vm.i915 = i915;
 	ppgtt->vm.dma = &i915->drm.pdev->dev;
 
-	ppgtt->vm.total = USES_FULL_48BIT_PPGTT(i915) ?
+	ppgtt->vm.total = HAS_FULL_48BIT_PPGTT(i915) ?
 		1ULL << 48 :
 		1ULL << 32;
 
@@ -1782,19 +1733,6 @@ static inline void gen6_write_pde(const struct gen6_hw_ppgtt *ppgtt,
 		  ppgtt->pd_addr + pde);
 }
 
-static void gen8_ppgtt_enable(struct drm_i915_private *dev_priv)
-{
-	struct intel_engine_cs *engine;
-	enum intel_engine_id id;
-
-	for_each_engine(engine, dev_priv, id) {
-		u32 four_level = USES_FULL_48BIT_PPGTT(dev_priv) ?
-				 GEN8_GFX_PPGTT_48B : 0;
-		I915_WRITE(RING_MODE_GEN7(engine),
-			   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
-	}
-}
-
 static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv)
 {
 	struct intel_engine_cs *engine;
@@ -1834,7 +1772,8 @@ static void gen6_ppgtt_enable(struct drm_i915_private *dev_priv)
 	ecochk = I915_READ(GAM_ECOCHK);
 	I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
 
-	I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
+	if (HAS_PPGTT(dev_priv)) /* may be disabled for VT-d */
+		I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 }
 
 /* PPGTT support for Sandybdrige/Gen6 and later */
@@ -2237,23 +2176,10 @@ int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv)
 {
 	gtt_write_workarounds(dev_priv);
 
-	/* In the case of execlists, PPGTT is enabled by the context descriptor
-	 * and the PDPs are contained within the context itself.  We don't
-	 * need to do anything here. */
-	if (HAS_LOGICAL_RING_CONTEXTS(dev_priv))
-		return 0;
-
-	if (!USES_PPGTT(dev_priv))
-		return 0;
-
 	if (IS_GEN6(dev_priv))
 		gen6_ppgtt_enable(dev_priv);
 	else if (IS_GEN7(dev_priv))
 		gen7_ppgtt_enable(dev_priv);
-	else if (INTEL_GEN(dev_priv) >= 8)
-		gen8_ppgtt_enable(dev_priv);
-	else
-		MISSING_CASE(INTEL_GEN(dev_priv));
 
 	return 0;
 }
@@ -2952,7 +2878,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
 	/* And finally clear the reserved guard page */
 	ggtt->vm.clear_range(&ggtt->vm, ggtt->vm.total - PAGE_SIZE, PAGE_SIZE);
 
-	if (USES_PPGTT(dev_priv) && !USES_FULL_PPGTT(dev_priv)) {
+	if (INTEL_PPGTT(dev_priv) == INTEL_PPGTT_ALIASING) {
 		ret = i915_gem_init_aliasing_ppgtt(dev_priv);
 		if (ret)
 			goto err;
@@ -3275,7 +3201,7 @@ static void bdw_setup_private_ppat(struct intel_ppat *ppat)
 	ppat->match = bdw_private_pat_match;
 	ppat->clear_value = GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3);
 
-	if (!USES_PPGTT(ppat->i915)) {
+	if (!HAS_PPGTT(ppat->i915)) {
 		/* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
 		 * so RTL will always use the value corresponding to
 		 * pat_sel = 000".
@@ -3402,7 +3328,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
 	ggtt->vm.cleanup = gen6_gmch_remove;
 	ggtt->vm.insert_page = gen8_ggtt_insert_page;
 	ggtt->vm.clear_range = nop_clear_range;
-	if (!USES_FULL_PPGTT(dev_priv) || intel_scanout_needs_vtd_wa(dev_priv))
+	if (intel_scanout_needs_vtd_wa(dev_priv))
 		ggtt->vm.clear_range = gen8_ggtt_clear_range;
 
 	ggtt->vm.insert_entries = gen8_ggtt_insert_entries;
@@ -3609,7 +3535,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
 	/* Only VLV supports read-only GGTT mappings */
 	ggtt->vm.has_read_only = IS_VALLEYVIEW(dev_priv);
 
-	if (!HAS_LLC(dev_priv) && !USES_PPGTT(dev_priv))
+	if (!HAS_LLC(dev_priv) && !HAS_PPGTT(dev_priv))
 		ggtt->vm.mm.color_adjust = i915_gtt_color_adjust;
 	mutex_unlock(&dev_priv->drm.struct_mutex);
 
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 2835cacd0d08..3d5554f14dfd 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -474,7 +474,7 @@ static void error_print_engine(struct drm_i915_error_state_buf *m,
 			err_printf(m, "  SYNC_2: 0x%08x\n",
 				   ee->semaphore_mboxes[2]);
 	}
-	if (USES_PPGTT(m->i915)) {
+	if (HAS_PPGTT(m->i915)) {
 		err_printf(m, "  GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
 
 		if (INTEL_GEN(m->i915) >= 8) {
@@ -1230,7 +1230,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
 	ee->reset_count = i915_reset_engine_count(&dev_priv->gpu_error,
 						  engine);
 
-	if (USES_PPGTT(dev_priv)) {
+	if (HAS_PPGTT(dev_priv)) {
 		int i;
 
 		ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 295e981e4a39..bd6bd8879cab 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -82,10 +82,6 @@ i915_param_named_unsafe(enable_hangcheck, bool, 0644,
 	"WARNING: Disabling this can cause system wide hangs. "
 	"(default: true)");
 
-i915_param_named_unsafe(enable_ppgtt, int, 0400,
-	"Override PPGTT usage. "
-	"(-1=auto [default], 0=disabled, 1=aliasing, 2=full, 3=full with extended address space)");
-
 i915_param_named_unsafe(enable_psr, int, 0600,
 	"Enable PSR "
 	"(0=disabled, 1=enabled) "
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 6c4d4a21474b..7e56c516c815 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -41,7 +41,6 @@ struct drm_printer;
 	param(int, vbt_sdvo_panel_type, -1) \
 	param(int, enable_dc, -1) \
 	param(int, enable_fbc, -1) \
-	param(int, enable_ppgtt, -1) \
 	param(int, enable_psr, -1) \
 	param(int, disable_power_well, -1) \
 	param(int, enable_ips, 1) \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d6f7b9fe1d26..eeec902896b9 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -252,7 +252,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
 	.has_llc = 1, \
 	.has_rc6 = 1, \
 	.has_rc6p = 1, \
-	.has_aliasing_ppgtt = 1, \
+	.ppgtt = INTEL_PPGTT_ALIASING, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
 	CURSOR_OFFSETS
@@ -297,8 +297,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
 	.has_llc = 1, \
 	.has_rc6 = 1, \
 	.has_rc6p = 1, \
-	.has_aliasing_ppgtt = 1, \
-	.has_full_ppgtt = 1, \
+	.ppgtt = INTEL_PPGTT_FULL, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
 	IVB_CURSOR_OFFSETS
@@ -351,8 +350,7 @@ static const struct intel_device_info intel_valleyview_info = {
 	.has_rc6 = 1,
 	.has_gmch_display = 1,
 	.has_hotplug = 1,
-	.has_aliasing_ppgtt = 1,
-	.has_full_ppgtt = 1,
+	.ppgtt = INTEL_PPGTT_FULL,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
@@ -399,7 +397,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
 	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
 		      I915_GTT_PAGE_SIZE_2M, \
 	.has_logical_ring_contexts = 1, \
-	.has_full_48bit_ppgtt = 1, \
+	.ppgtt = INTEL_PPGTT_FULL_4LVL, \
 	.has_64bit_reloc = 1, \
 	.has_reset_engine = 1
 
@@ -443,8 +441,7 @@ static const struct intel_device_info intel_cherryview_info = {
 	.has_rc6 = 1,
 	.has_logical_ring_contexts = 1,
 	.has_gmch_display = 1,
-	.has_aliasing_ppgtt = 1,
-	.has_full_ppgtt = 1,
+	.ppgtt = INTEL_PPGTT_FULL,
 	.has_reset_engine = 1,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
@@ -518,9 +515,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
 	.has_logical_ring_contexts = 1, \
 	.has_logical_ring_preemption = 1, \
 	.has_guc = 1, \
-	.has_aliasing_ppgtt = 1, \
-	.has_full_ppgtt = 1, \
-	.has_full_48bit_ppgtt = 1, \
+	.ppgtt = INTEL_PPGTT_FULL_4LVL, \
 	.has_reset_engine = 1, \
 	.has_snoop = true, \
 	.has_coherent_ggtt = false, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 0ef0c6448d53..a841d181efd3 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -26,6 +26,7 @@
 
 #include "intel_device_info.h"
 #include "i915_drv.h"
+#include "i915_vgpu.h"
 
 #define PLATFORM_NAME(x) [INTEL_##x] = #x
 static const char * const platform_names[] = {
@@ -851,6 +852,11 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
 	else if (INTEL_GEN(dev_priv) >= 11)
 		gen11_sseu_info_init(dev_priv);
 
+	if (IS_GEN6(dev_priv) && intel_vtd_active()) {
+		DRM_INFO("Disabling ppGTT for VT-d support\n");
+		info->ppgtt = INTEL_PPGTT_NONE;
+	}
+
 	/* Initialize command stream timestamp frequency */
 	info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
 }
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 6eecd64734d5..6bab97687328 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -74,21 +74,25 @@ enum intel_platform {
 	INTEL_MAX_PLATFORMS
 };
 
+enum intel_ppgtt {
+	INTEL_PPGTT_NONE = 0,
+	INTEL_PPGTT_ALIASING,
+	INTEL_PPGTT_FULL,
+	INTEL_PPGTT_FULL_4LVL,
+};
+
 #define DEV_INFO_FOR_EACH_FLAG(func) \
 	func(is_mobile); \
 	func(is_lp); \
 	func(is_alpha_support); \
 	/* Keep has_* in alphabetical order */ \
 	func(has_64bit_reloc); \
-	func(has_aliasing_ppgtt); \
 	func(has_csr); \
 	func(has_ddi); \
 	func(has_dp_mst); \
 	func(has_reset_engine); \
 	func(has_fbc); \
 	func(has_fpga_dbg); \
-	func(has_full_ppgtt); \
-	func(has_full_48bit_ppgtt); \
 	func(has_gmch_display); \
 	func(has_guc); \
 	func(has_guc_ct); \
@@ -154,6 +158,7 @@ struct intel_device_info {
 	enum intel_platform platform;
 	u32 platform_mask;
 
+	enum intel_ppgtt ppgtt;
 	unsigned int page_sizes; /* page sizes supported by the HW */
 
 	u32 display_mmio_offset;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 4b28225320ff..3836a8a3761a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -418,9 +418,8 @@ execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
 
 static u64 execlists_update_context(struct i915_request *rq)
 {
+	struct i915_hw_ppgtt *ppgtt = rq->gem_context->ppgtt;
 	struct intel_context *ce = rq->hw_context;
-	struct i915_hw_ppgtt *ppgtt =
-		rq->gem_context->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
 	u32 *reg_state = ce->lrc_reg_state;
 
 	reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail);
@@ -1376,7 +1375,7 @@ execlists_context_pin(struct intel_engine_cs *engine,
 	struct intel_context *ce = to_intel_context(ctx, engine);
 
 	lockdep_assert_held(&ctx->i915->drm.struct_mutex);
-	GEM_BUG_ON(!(ctx->ppgtt ?: ctx->i915->mm.aliasing_ppgtt));
+	GEM_BUG_ON(!ctx->ppgtt);
 
 	if (likely(ce->pin_count++))
 		return ce;
@@ -2031,8 +2030,7 @@ static int gen8_emit_bb_start(struct i915_request *rq,
 	 * it is unsafe in case of lite-restore (because the ctx is
 	 * not idle). PML4 is allocated during ppgtt init so this is
 	 * not needed in 48-bit.*/
-	if (rq->gem_context->ppgtt &&
-	    (intel_engine_flag(rq->engine) & rq->gem_context->ppgtt->pd_dirty_rings) &&
+	if ((intel_engine_flag(rq->engine) & rq->gem_context->ppgtt->pd_dirty_rings) &&
 	    !i915_vm_is_48bit(&rq->gem_context->ppgtt->vm) &&
 	    !intel_vgpu_active(rq->i915)) {
 		ret = intel_logical_ring_emit_pdps(rq);
@@ -2634,7 +2632,6 @@ static void execlists_init_reg_state(u32 *regs,
 				     struct intel_ring *ring)
 {
 	struct drm_i915_private *dev_priv = engine->i915;
-	struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: dev_priv->mm.aliasing_ppgtt;
 	u32 base = engine->mmio_base;
 	bool rcs = engine->class == RENDER_CLASS;
 
@@ -2706,12 +2703,12 @@ static void execlists_init_reg_state(u32 *regs,
 	CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
 	CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
 
-	if (i915_vm_is_48bit(&ppgtt->vm)) {
+	if (i915_vm_is_48bit(&ctx->ppgtt->vm)) {
 		/* 64b PPGTT (48bit canonical)
 		 * PDP0_DESCRIPTOR contains the base address to PML4 and
 		 * other PDP Descriptors are ignored.
 		 */
-		ASSIGN_CTX_PML4(ppgtt, regs);
+		ASSIGN_CTX_PML4(ctx->ppgtt, regs);
 	}
 
 	if (rcs) {
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 8d03f64eabd7..09ea65a29d98 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1436,7 +1436,7 @@ static int igt_ppgtt_pin_update(void *arg)
 	 * huge-gtt-pages.
 	 */
 
-	if (!USES_FULL_48BIT_PPGTT(dev_priv)) {
+	if (!HAS_FULL_48BIT_PPGTT(dev_priv)) {
 		pr_info("48b PPGTT not supported, skipping\n");
 		return 0;
 	}
@@ -1687,10 +1687,9 @@ int i915_gem_huge_page_mock_selftests(void)
 		SUBTEST(igt_mock_ppgtt_huge_fill),
 		SUBTEST(igt_mock_ppgtt_64K),
 	};
-	int saved_ppgtt = i915_modparams.enable_ppgtt;
 	struct drm_i915_private *dev_priv;
-	struct pci_dev *pdev;
 	struct i915_hw_ppgtt *ppgtt;
+	struct pci_dev *pdev;
 	int err;
 
 	dev_priv = mock_gem_device();
@@ -1698,7 +1697,7 @@ int i915_gem_huge_page_mock_selftests(void)
 		return -ENOMEM;
 
 	/* Pretend to be a device which supports the 48b PPGTT */
-	i915_modparams.enable_ppgtt = 3;
+	mkwrite_device_info(dev_priv)->ppgtt = INTEL_PPGTT_FULL_4LVL;
 
 	pdev = dev_priv->drm.pdev;
 	dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(39));
@@ -1731,9 +1730,6 @@ int i915_gem_huge_page_mock_selftests(void)
 
 out_unlock:
 	mutex_unlock(&dev_priv->drm.struct_mutex);
-
-	i915_modparams.enable_ppgtt = saved_ppgtt;
-
 	drm_dev_put(&dev_priv->drm);
 
 	return err;
@@ -1753,7 +1749,7 @@ int i915_gem_huge_page_live_selftests(struct drm_i915_private *dev_priv)
 	struct i915_gem_context *ctx;
 	int err;
 
-	if (!USES_PPGTT(dev_priv)) {
+	if (!HAS_PPGTT(dev_priv)) {
 		pr_info("PPGTT not supported, skipping live-selftests\n");
 		return 0;
 	}
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
index 76df25aa90c9..913c0f83f86a 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
@@ -535,7 +535,6 @@ static int igt_ctx_exec(void *arg)
 	IGT_TIMEOUT(end_time);
 	LIST_HEAD(objects);
 	unsigned long ncontexts, ndwords, dw;
-	bool first_shared_gtt = true;
 	int err = -ENODEV;
 
 	/*
@@ -561,12 +560,7 @@ static int igt_ctx_exec(void *arg)
 		struct i915_gem_context *ctx;
 		unsigned int id;
 
-		if (first_shared_gtt) {
-			ctx = __create_hw_context(i915, file->driver_priv);
-			first_shared_gtt = false;
-		} else {
-			ctx = i915_gem_create_context(i915, file->driver_priv);
-		}
+		ctx = i915_gem_create_context(i915, file->driver_priv);
 		if (IS_ERR(ctx)) {
 			err = PTR_ERR(ctx);
 			goto out_unlock;
@@ -865,33 +859,6 @@ static int igt_switch_to_kernel_context(void *arg)
 	return err;
 }
 
-static int fake_aliasing_ppgtt_enable(struct drm_i915_private *i915)
-{
-	struct drm_i915_gem_object *obj;
-	int err;
-
-	err = i915_gem_init_aliasing_ppgtt(i915);
-	if (err)
-		return err;
-
-	list_for_each_entry(obj, &i915->mm.bound_list, mm.link) {
-		struct i915_vma *vma;
-
-		vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
-		if (IS_ERR(vma))
-			continue;
-
-		vma->flags &= ~I915_VMA_LOCAL_BIND;
-	}
-
-	return 0;
-}
-
-static void fake_aliasing_ppgtt_disable(struct drm_i915_private *i915)
-{
-	i915_gem_fini_aliasing_ppgtt(i915);
-}
-
 int i915_gem_context_mock_selftests(void)
 {
 	static const struct i915_subtest tests[] = {
@@ -918,31 +885,9 @@ int i915_gem_context_live_selftests(struct drm_i915_private *dev_priv)
 		SUBTEST(igt_ctx_exec),
 		SUBTEST(igt_ctx_readonly),
 	};
-	bool fake_alias = false;
-	int err;
 
 	if (i915_terminally_wedged(&dev_priv->gpu_error))
 		return 0;
 
-	/* Install a fake aliasing gtt for exercise */
-	if (USES_PPGTT(dev_priv) && !dev_priv->mm.aliasing_ppgtt) {
-		mutex_lock(&dev_priv->drm.struct_mutex);
-		err = fake_aliasing_ppgtt_enable(dev_priv);
-		mutex_unlock(&dev_priv->drm.struct_mutex);
-		if (err)
-			return err;
-
-		GEM_BUG_ON(!dev_priv->mm.aliasing_ppgtt);
-		fake_alias = true;
-	}
-
-	err = i915_subtests(tests, dev_priv);
-
-	if (fake_alias) {
-		mutex_lock(&dev_priv->drm.struct_mutex);
-		fake_aliasing_ppgtt_disable(dev_priv);
-		mutex_unlock(&dev_priv->drm.struct_mutex);
-	}
-
-	return err;
+	return i915_subtests(tests, dev_priv);
 }
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
index 128ad1cf0647..4365979d8222 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
@@ -351,7 +351,7 @@ static int igt_evict_contexts(void *arg)
 	 * where the GTT space of the request is separate from the GGTT
 	 * allocation required to build the request.
 	 */
-	if (!USES_FULL_PPGTT(i915))
+	if (!HAS_FULL_PPGTT(i915))
 		return 0;
 
 	mutex_lock(&i915->drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 8e2e269db97e..17b5aaaa7a50 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -153,7 +153,7 @@ static int igt_ppgtt_alloc(void *arg)
 
 	/* Allocate a ppggt and try to fill the entire range */
 
-	if (!USES_PPGTT(dev_priv))
+	if (!HAS_PPGTT(dev_priv))
 		return 0;
 
 	ppgtt = __hw_ppgtt_create(dev_priv);
@@ -1001,7 +1001,7 @@ static int exercise_ppgtt(struct drm_i915_private *dev_priv,
 	IGT_TIMEOUT(end_time);
 	int err;
 
-	if (!USES_FULL_PPGTT(dev_priv))
+	if (!HAS_FULL_PPGTT(dev_priv))
 		return 0;
 
 	file = mock_file(dev_priv);
-- 
2.19.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 24+ messages in thread
* ✗ Fi.CI.SPARSE: warning for drm/i915: Remove i915.enable_ppgtt override
  2018-09-25 11:48 [PATCH v4] drm/i915: Remove i915.enable_ppgtt override Chris Wilson
@ 2018-09-25 12:06 ` Patchwork
  2018-09-25 12:28 ` ✗ Fi.CI.BAT: failure " Patchwork
                   ` (7 subsequent siblings)
  8 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2018-09-25 12:06 UTC (permalink / raw)
  To: Chris Wilson; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Remove i915.enable_ppgtt override
URL   : https://patchwork.freedesktop.org/series/50143/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915: Remove i915.enable_ppgtt override
+drivers/gpu/drm/i915/i915_gem_gtt.c:348:14: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_gem_gtt.c:348:14: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/i915_gem_gtt.c:348:14: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/i915_gem_gtt.c:348:14: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3718:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3720:16: warning: expression using sizeof(void)

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915: Remove i915.enable_ppgtt override
  2018-09-25 11:48 [PATCH v4] drm/i915: Remove i915.enable_ppgtt override Chris Wilson
  2018-09-25 12:06 ` ✗ Fi.CI.SPARSE: warning for " Patchwork
@ 2018-09-25 12:28 ` Patchwork
  2018-09-25 13:14 ` Patchwork
                   ` (6 subsequent siblings)
  8 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2018-09-25 12:28 UTC (permalink / raw)
  To: Chris Wilson; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Remove i915.enable_ppgtt override
URL   : https://patchwork.freedesktop.org/series/50143/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4873 -> Patchwork_10276 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_10276 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10276, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/50143/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10276:

  === IGT changes ===

    ==== Possible regressions ====

    igt@kms_flip@basic-flip-vs-wf_vblank:
      fi-icl-u:           NOTRUN -> DMESG-WARN +47

    igt@pm_rpm@basic-pci-d3-state:
      fi-cnl-u:           PASS -> FAIL

    
    ==== Warnings ====

    igt@gem_exec_suspend@basic-s3:
      fi-icl-u:           INCOMPLETE (fdo#107901, fdo#107713) -> DMESG-WARN

    
== Known issues ==

  Here are the changes found in Patchwork_10276 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_exec_suspend@basic-s3:
      fi-kbl-soraka:      NOTRUN -> INCOMPLETE (fdo#107556, fdo#107774)

    igt@gem_exec_suspend@basic-s4-devices:
      fi-bdw-samus:       PASS -> INCOMPLETE (fdo#107773)

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-byt-clapper:     PASS -> FAIL (fdo#103191, fdo#107362)

    
    ==== Possible fixes ====

    igt@drv_module_reload@basic-reload:
      fi-blb-e6850:       INCOMPLETE (fdo#107718) -> PASS

    igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
      fi-byt-clapper:     FAIL (fdo#107362) -> PASS

    igt@kms_psr@primary_page_flip:
      fi-cnl-u:           FAIL (fdo#107336) -> PASS

    
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107556 https://bugs.freedesktop.org/show_bug.cgi?id=107556
  fdo#107713 https://bugs.freedesktop.org/show_bug.cgi?id=107713
  fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
  fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773
  fdo#107774 https://bugs.freedesktop.org/show_bug.cgi?id=107774
  fdo#107901 https://bugs.freedesktop.org/show_bug.cgi?id=107901


== Participating hosts (46 -> 43) ==

  Additional (2): fi-kbl-soraka fi-snb-2520m 
  Missing    (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u 


== Build changes ==

    * Linux: CI_DRM_4873 -> Patchwork_10276

  CI_DRM_4873: 8530ac87ef4408d89a603a3f592161670c52c3c3 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4649: 19b0c74d20d9b53d4c82be14af0909a3b6846010 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10276: 731b0da6a1a58cf37f99d8346c3f298992a9ae10 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

731b0da6a1a5 drm/i915: Remove i915.enable_ppgtt override

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10276/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915: Remove i915.enable_ppgtt override
  2018-09-25 11:48 [PATCH v4] drm/i915: Remove i915.enable_ppgtt override Chris Wilson
  2018-09-25 12:06 ` ✗ Fi.CI.SPARSE: warning for " Patchwork
  2018-09-25 12:28 ` ✗ Fi.CI.BAT: failure " Patchwork
@ 2018-09-25 13:14 ` Patchwork
  2018-09-25 13:22 ` [PATCH v4] " Joonas Lahtinen
                   ` (5 subsequent siblings)
  8 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2018-09-25 13:14 UTC (permalink / raw)
  To: Chris Wilson; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Remove i915.enable_ppgtt override
URL   : https://patchwork.freedesktop.org/series/50143/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4873 -> Patchwork_10277 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_10277 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10277, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/50143/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10277:

  === IGT changes ===

    ==== Possible regressions ====

    igt@kms_flip@basic-flip-vs-wf_vblank:
      fi-icl-u:           NOTRUN -> DMESG-WARN +47

    
    ==== Warnings ====

    igt@gem_exec_suspend@basic-s3:
      fi-icl-u:           INCOMPLETE (fdo#107713, fdo#107901) -> DMESG-WARN

    
== Known issues ==

  Here are the changes found in Patchwork_10277 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_exec_suspend@basic-s3:
      fi-kbl-soraka:      NOTRUN -> INCOMPLETE (fdo#107556, fdo#107774)

    igt@kms_frontbuffer_tracking@basic:
      fi-byt-clapper:     PASS -> FAIL (fdo#103167)

    igt@kms_psr@primary_page_flip:
      fi-kbl-r:           PASS -> FAIL (fdo#107336)

    
    ==== Possible fixes ====

    igt@drv_module_reload@basic-reload:
      fi-blb-e6850:       INCOMPLETE (fdo#107718) -> PASS

    igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
      fi-byt-clapper:     FAIL (fdo#107362) -> PASS

    igt@kms_psr@primary_page_flip:
      fi-cnl-u:           FAIL (fdo#107336) -> PASS

    
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107556 https://bugs.freedesktop.org/show_bug.cgi?id=107556
  fdo#107713 https://bugs.freedesktop.org/show_bug.cgi?id=107713
  fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
  fdo#107774 https://bugs.freedesktop.org/show_bug.cgi?id=107774
  fdo#107901 https://bugs.freedesktop.org/show_bug.cgi?id=107901


== Participating hosts (46 -> 43) ==

  Additional (2): fi-kbl-soraka fi-snb-2520m 
  Missing    (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u 


== Build changes ==

    * Linux: CI_DRM_4873 -> Patchwork_10277

  CI_DRM_4873: 8530ac87ef4408d89a603a3f592161670c52c3c3 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4649: 19b0c74d20d9b53d4c82be14af0909a3b6846010 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10277: aef925bf186764d9f8ca816a0be9fb82151bbcf1 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

aef925bf1867 drm/i915: Remove i915.enable_ppgtt override

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10277/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v4] drm/i915: Remove i915.enable_ppgtt override
  2018-09-25 11:48 [PATCH v4] drm/i915: Remove i915.enable_ppgtt override Chris Wilson
                   ` (2 preceding siblings ...)
  2018-09-25 13:14 ` Patchwork
@ 2018-09-25 13:22 ` Joonas Lahtinen
  2018-09-25 18:01   ` Zhi Wang
  2018-09-25 13:27 ` Joonas Lahtinen
                   ` (4 subsequent siblings)
  8 siblings, 1 reply; 24+ messages in thread
From: Joonas Lahtinen @ 2018-09-25 13:22 UTC (permalink / raw)
  To: Chris Wilson, intel-gfx, Zhi Wang, Zhenyu Wang; +Cc: Matthew Auld

+ Zhi and Zhenyu

For me the patch looks ok.

It refuses to load GVT on systems where 48-bit is not supported, for not
worsening the system security when virtualization is enabled (as anybody
would probably expect virtualization to improve that). Please see code.

Do we have such systems in the wild? Should we instruct the user to
updating the hypervisor to specific kernel version when they hit the
error?

Regards, Joonas

Quoting Chris Wilson (2018-09-25 14:48:20)
> Now that we are confident in providing full-ppgtt where supported,
> remove the ability to override the context isolation.
> 
> v2: Remove faked aliasing-ppgtt for testing as it no longer is accepted.
> v3: s/USES/HAS/ to match usage and reject attempts to load the module on
> old GVT-g setups that do not provide support for full-ppgtt.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.c               | 22 +++--
>  drivers/gpu/drm/i915/i915_drv.h               | 14 +--
>  drivers/gpu/drm/i915/i915_gem_context.c       |  2 +-
>  drivers/gpu/drm/i915/i915_gem_gtt.c           | 88 ++-----------------
>  drivers/gpu/drm/i915/i915_gpu_error.c         |  4 +-
>  drivers/gpu/drm/i915/i915_params.c            |  4 -
>  drivers/gpu/drm/i915/i915_params.h            |  1 -
>  drivers/gpu/drm/i915/i915_pci.c               | 17 ++--
>  drivers/gpu/drm/i915/intel_device_info.c      |  6 ++
>  drivers/gpu/drm/i915/intel_device_info.h      | 11 ++-
>  drivers/gpu/drm/i915/intel_lrc.c              | 13 ++-
>  drivers/gpu/drm/i915/selftests/huge_pages.c   | 12 +--
>  .../gpu/drm/i915/selftests/i915_gem_context.c | 59 +------------
>  .../gpu/drm/i915/selftests/i915_gem_evict.c   |  2 +-
>  drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |  4 +-
>  15 files changed, 62 insertions(+), 197 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 44e2c0f5ec50..3efbbc71c3b4 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -345,7 +345,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
>                 value = HAS_WT(dev_priv);
>                 break;
>         case I915_PARAM_HAS_ALIASING_PPGTT:
> -               value = USES_PPGTT(dev_priv);
> +               value = INTEL_PPGTT(dev_priv);
>                 break;
>         case I915_PARAM_HAS_SEMAPHORES:
>                 value = HAS_LEGACY_SEMAPHORES(dev_priv);
> @@ -1049,17 +1049,6 @@ static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
>  
>  static void intel_sanitize_options(struct drm_i915_private *dev_priv)
>  {
> -       /*
> -        * i915.enable_ppgtt is read-only, so do an early pass to validate the
> -        * user's requested state against the hardware/driver capabilities.  We
> -        * do this now so that we can print out any log messages once rather
> -        * than every time we check intel_enable_ppgtt().
> -        */
> -       i915_modparams.enable_ppgtt =
> -               intel_sanitize_enable_ppgtt(dev_priv,
> -                                           i915_modparams.enable_ppgtt);
> -       DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
> -
>         intel_gvt_sanitize_options(dev_priv);
>  }
>  
> @@ -1374,6 +1363,15 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
>  
>         intel_device_info_runtime_init(mkwrite_device_info(dev_priv));
>  
> +       if (HAS_PPGTT(dev_priv)) {
> +               if (intel_vgpu_active(dev_priv) &&
> +                   !intel_vgpu_has_full_48bit_ppgtt(dev_priv)) {
> +                       i915_report_error(dev_priv,
> +                                         "incompatible vGPU found, support for isolated ppGTT required\n");
> +                       return -ENXIO;
> +               }
> +       }
> +
>         intel_sanitize_options(dev_priv);
>  
>         i915_perf_init(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8624b4bdc242..f28b3c2a3cd2 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2593,9 +2593,14 @@ intel_info(const struct drm_i915_private *dev_priv)
>  
>  #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
>  
> -#define USES_PPGTT(dev_priv)           (i915_modparams.enable_ppgtt)
> -#define USES_FULL_PPGTT(dev_priv)      (i915_modparams.enable_ppgtt >= 2)
> -#define USES_FULL_48BIT_PPGTT(dev_priv)        (i915_modparams.enable_ppgtt == 3)
> +#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt)
> +#define HAS_PPGTT(dev_priv) \
> +       (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
> +#define HAS_FULL_PPGTT(dev_priv) \
> +       (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
> +#define HAS_FULL_48BIT_PPGTT(dev_priv) \
> +       (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL_4LVL)
> +
>  #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
>         GEM_BUG_ON((sizes) == 0); \
>         ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
> @@ -2743,9 +2748,6 @@ intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
>         return IS_BROXTON(dev_priv) && intel_vtd_active();
>  }
>  
> -int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
> -                               int enable_ppgtt);
> -
>  /* i915_drv.c */
>  void __printf(3, 4)
>  __i915_printk(struct drm_i915_private *dev_priv, const char *level,
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index f772593b99ab..15c92f75b1b8 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -414,7 +414,7 @@ i915_gem_create_context(struct drm_i915_private *dev_priv,
>         if (IS_ERR(ctx))
>                 return ctx;
>  
> -       if (USES_FULL_PPGTT(dev_priv)) {
> +       if (HAS_FULL_PPGTT(dev_priv)) {
>                 struct i915_hw_ppgtt *ppgtt;
>  
>                 ppgtt = i915_ppgtt_create(dev_priv, file_priv);
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index f6c7ab413081..c9363504949f 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -133,55 +133,6 @@ static inline void i915_ggtt_invalidate(struct drm_i915_private *i915)
>         i915->ggtt.invalidate(i915);
>  }
>  
> -int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
> -                               int enable_ppgtt)
> -{
> -       bool has_full_ppgtt;
> -       bool has_full_48bit_ppgtt;
> -
> -       if (!dev_priv->info.has_aliasing_ppgtt)
> -               return 0;
> -
> -       has_full_ppgtt = dev_priv->info.has_full_ppgtt;
> -       has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt;
> -
> -       if (intel_vgpu_active(dev_priv)) {
> -               /* GVT-g has no support for 32bit ppgtt */
> -               has_full_ppgtt = false;
> -               has_full_48bit_ppgtt = intel_vgpu_has_full_48bit_ppgtt(dev_priv);
> -       }
> -
> -       /*
> -        * We don't allow disabling PPGTT for gen8+ as it's a requirement for
> -        * execlists, the sole mechanism available to submit work.
> -        */
> -       if (enable_ppgtt == 0 && !HAS_EXECLISTS(dev_priv))
> -               return 0;
> -
> -       if (enable_ppgtt == 1)
> -               return 1;
> -
> -       if (enable_ppgtt == 2 && has_full_ppgtt)
> -               return 2;
> -
> -       if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
> -               return 3;
> -
> -       /* Disable ppgtt on SNB if VT-d is on. */
> -       if (IS_GEN6(dev_priv) && intel_vtd_active()) {
> -               DRM_INFO("Disabling PPGTT because VT-d is on\n");
> -               return 0;
> -       }
> -
> -       if (has_full_48bit_ppgtt)
> -               return 3;
> -
> -       if (has_full_ppgtt)
> -               return 2;
> -
> -       return 1;
> -}
> -
>  static int ppgtt_bind_vma(struct i915_vma *vma,
>                           enum i915_cache_level cache_level,
>                           u32 unused)
> @@ -1647,7 +1598,7 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
>         ppgtt->vm.i915 = i915;
>         ppgtt->vm.dma = &i915->drm.pdev->dev;
>  
> -       ppgtt->vm.total = USES_FULL_48BIT_PPGTT(i915) ?
> +       ppgtt->vm.total = HAS_FULL_48BIT_PPGTT(i915) ?
>                 1ULL << 48 :
>                 1ULL << 32;
>  
> @@ -1782,19 +1733,6 @@ static inline void gen6_write_pde(const struct gen6_hw_ppgtt *ppgtt,
>                   ppgtt->pd_addr + pde);
>  }
>  
> -static void gen8_ppgtt_enable(struct drm_i915_private *dev_priv)
> -{
> -       struct intel_engine_cs *engine;
> -       enum intel_engine_id id;
> -
> -       for_each_engine(engine, dev_priv, id) {
> -               u32 four_level = USES_FULL_48BIT_PPGTT(dev_priv) ?
> -                                GEN8_GFX_PPGTT_48B : 0;
> -               I915_WRITE(RING_MODE_GEN7(engine),
> -                          _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
> -       }
> -}
> -
>  static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv)
>  {
>         struct intel_engine_cs *engine;
> @@ -1834,7 +1772,8 @@ static void gen6_ppgtt_enable(struct drm_i915_private *dev_priv)
>         ecochk = I915_READ(GAM_ECOCHK);
>         I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
>  
> -       I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
> +       if (HAS_PPGTT(dev_priv)) /* may be disabled for VT-d */
> +               I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
>  }
>  
>  /* PPGTT support for Sandybdrige/Gen6 and later */
> @@ -2237,23 +2176,10 @@ int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv)
>  {
>         gtt_write_workarounds(dev_priv);
>  
> -       /* In the case of execlists, PPGTT is enabled by the context descriptor
> -        * and the PDPs are contained within the context itself.  We don't
> -        * need to do anything here. */
> -       if (HAS_LOGICAL_RING_CONTEXTS(dev_priv))
> -               return 0;
> -
> -       if (!USES_PPGTT(dev_priv))
> -               return 0;
> -
>         if (IS_GEN6(dev_priv))
>                 gen6_ppgtt_enable(dev_priv);
>         else if (IS_GEN7(dev_priv))
>                 gen7_ppgtt_enable(dev_priv);
> -       else if (INTEL_GEN(dev_priv) >= 8)
> -               gen8_ppgtt_enable(dev_priv);
> -       else
> -               MISSING_CASE(INTEL_GEN(dev_priv));
>  
>         return 0;
>  }
> @@ -2952,7 +2878,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
>         /* And finally clear the reserved guard page */
>         ggtt->vm.clear_range(&ggtt->vm, ggtt->vm.total - PAGE_SIZE, PAGE_SIZE);
>  
> -       if (USES_PPGTT(dev_priv) && !USES_FULL_PPGTT(dev_priv)) {
> +       if (INTEL_PPGTT(dev_priv) == INTEL_PPGTT_ALIASING) {
>                 ret = i915_gem_init_aliasing_ppgtt(dev_priv);
>                 if (ret)
>                         goto err;
> @@ -3275,7 +3201,7 @@ static void bdw_setup_private_ppat(struct intel_ppat *ppat)
>         ppat->match = bdw_private_pat_match;
>         ppat->clear_value = GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3);
>  
> -       if (!USES_PPGTT(ppat->i915)) {
> +       if (!HAS_PPGTT(ppat->i915)) {
>                 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
>                  * so RTL will always use the value corresponding to
>                  * pat_sel = 000".
> @@ -3402,7 +3328,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
>         ggtt->vm.cleanup = gen6_gmch_remove;
>         ggtt->vm.insert_page = gen8_ggtt_insert_page;
>         ggtt->vm.clear_range = nop_clear_range;
> -       if (!USES_FULL_PPGTT(dev_priv) || intel_scanout_needs_vtd_wa(dev_priv))
> +       if (intel_scanout_needs_vtd_wa(dev_priv))
>                 ggtt->vm.clear_range = gen8_ggtt_clear_range;
>  
>         ggtt->vm.insert_entries = gen8_ggtt_insert_entries;
> @@ -3609,7 +3535,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
>         /* Only VLV supports read-only GGTT mappings */
>         ggtt->vm.has_read_only = IS_VALLEYVIEW(dev_priv);
>  
> -       if (!HAS_LLC(dev_priv) && !USES_PPGTT(dev_priv))
> +       if (!HAS_LLC(dev_priv) && !HAS_PPGTT(dev_priv))
>                 ggtt->vm.mm.color_adjust = i915_gtt_color_adjust;
>         mutex_unlock(&dev_priv->drm.struct_mutex);
>  
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 2835cacd0d08..3d5554f14dfd 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -474,7 +474,7 @@ static void error_print_engine(struct drm_i915_error_state_buf *m,
>                         err_printf(m, "  SYNC_2: 0x%08x\n",
>                                    ee->semaphore_mboxes[2]);
>         }
> -       if (USES_PPGTT(m->i915)) {
> +       if (HAS_PPGTT(m->i915)) {
>                 err_printf(m, "  GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
>  
>                 if (INTEL_GEN(m->i915) >= 8) {
> @@ -1230,7 +1230,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
>         ee->reset_count = i915_reset_engine_count(&dev_priv->gpu_error,
>                                                   engine);
>  
> -       if (USES_PPGTT(dev_priv)) {
> +       if (HAS_PPGTT(dev_priv)) {
>                 int i;
>  
>                 ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
> diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
> index 295e981e4a39..bd6bd8879cab 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -82,10 +82,6 @@ i915_param_named_unsafe(enable_hangcheck, bool, 0644,
>         "WARNING: Disabling this can cause system wide hangs. "
>         "(default: true)");
>  
> -i915_param_named_unsafe(enable_ppgtt, int, 0400,
> -       "Override PPGTT usage. "
> -       "(-1=auto [default], 0=disabled, 1=aliasing, 2=full, 3=full with extended address space)");
> -
>  i915_param_named_unsafe(enable_psr, int, 0600,
>         "Enable PSR "
>         "(0=disabled, 1=enabled) "
> diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
> index 6c4d4a21474b..7e56c516c815 100644
> --- a/drivers/gpu/drm/i915/i915_params.h
> +++ b/drivers/gpu/drm/i915/i915_params.h
> @@ -41,7 +41,6 @@ struct drm_printer;
>         param(int, vbt_sdvo_panel_type, -1) \
>         param(int, enable_dc, -1) \
>         param(int, enable_fbc, -1) \
> -       param(int, enable_ppgtt, -1) \
>         param(int, enable_psr, -1) \
>         param(int, disable_power_well, -1) \
>         param(int, enable_ips, 1) \
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index d6f7b9fe1d26..eeec902896b9 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -252,7 +252,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
>         .has_llc = 1, \
>         .has_rc6 = 1, \
>         .has_rc6p = 1, \
> -       .has_aliasing_ppgtt = 1, \
> +       .ppgtt = INTEL_PPGTT_ALIASING, \
>         GEN_DEFAULT_PIPEOFFSETS, \
>         GEN_DEFAULT_PAGE_SIZES, \
>         CURSOR_OFFSETS
> @@ -297,8 +297,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
>         .has_llc = 1, \
>         .has_rc6 = 1, \
>         .has_rc6p = 1, \
> -       .has_aliasing_ppgtt = 1, \
> -       .has_full_ppgtt = 1, \
> +       .ppgtt = INTEL_PPGTT_FULL, \
>         GEN_DEFAULT_PIPEOFFSETS, \
>         GEN_DEFAULT_PAGE_SIZES, \
>         IVB_CURSOR_OFFSETS
> @@ -351,8 +350,7 @@ static const struct intel_device_info intel_valleyview_info = {
>         .has_rc6 = 1,
>         .has_gmch_display = 1,
>         .has_hotplug = 1,
> -       .has_aliasing_ppgtt = 1,
> -       .has_full_ppgtt = 1,
> +       .ppgtt = INTEL_PPGTT_FULL,
>         .has_snoop = true,
>         .has_coherent_ggtt = false,
>         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
> @@ -399,7 +397,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
>         .page_sizes = I915_GTT_PAGE_SIZE_4K | \
>                       I915_GTT_PAGE_SIZE_2M, \
>         .has_logical_ring_contexts = 1, \
> -       .has_full_48bit_ppgtt = 1, \
> +       .ppgtt = INTEL_PPGTT_FULL_4LVL, \
>         .has_64bit_reloc = 1, \
>         .has_reset_engine = 1
>  
> @@ -443,8 +441,7 @@ static const struct intel_device_info intel_cherryview_info = {
>         .has_rc6 = 1,
>         .has_logical_ring_contexts = 1,
>         .has_gmch_display = 1,
> -       .has_aliasing_ppgtt = 1,
> -       .has_full_ppgtt = 1,
> +       .ppgtt = INTEL_PPGTT_FULL,
>         .has_reset_engine = 1,
>         .has_snoop = true,
>         .has_coherent_ggtt = false,
> @@ -518,9 +515,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
>         .has_logical_ring_contexts = 1, \
>         .has_logical_ring_preemption = 1, \
>         .has_guc = 1, \
> -       .has_aliasing_ppgtt = 1, \
> -       .has_full_ppgtt = 1, \
> -       .has_full_48bit_ppgtt = 1, \
> +       .ppgtt = INTEL_PPGTT_FULL_4LVL, \
>         .has_reset_engine = 1, \
>         .has_snoop = true, \
>         .has_coherent_ggtt = false, \
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 0ef0c6448d53..a841d181efd3 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -26,6 +26,7 @@
>  
>  #include "intel_device_info.h"
>  #include "i915_drv.h"
> +#include "i915_vgpu.h"
>  
>  #define PLATFORM_NAME(x) [INTEL_##x] = #x
>  static const char * const platform_names[] = {
> @@ -851,6 +852,11 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
>         else if (INTEL_GEN(dev_priv) >= 11)
>                 gen11_sseu_info_init(dev_priv);
>  
> +       if (IS_GEN6(dev_priv) && intel_vtd_active()) {
> +               DRM_INFO("Disabling ppGTT for VT-d support\n");
> +               info->ppgtt = INTEL_PPGTT_NONE;
> +       }
> +
>         /* Initialize command stream timestamp frequency */
>         info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
>  }
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 6eecd64734d5..6bab97687328 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -74,21 +74,25 @@ enum intel_platform {
>         INTEL_MAX_PLATFORMS
>  };
>  
> +enum intel_ppgtt {
> +       INTEL_PPGTT_NONE = 0,
> +       INTEL_PPGTT_ALIASING,
> +       INTEL_PPGTT_FULL,
> +       INTEL_PPGTT_FULL_4LVL,
> +};
> +
>  #define DEV_INFO_FOR_EACH_FLAG(func) \
>         func(is_mobile); \
>         func(is_lp); \
>         func(is_alpha_support); \
>         /* Keep has_* in alphabetical order */ \
>         func(has_64bit_reloc); \
> -       func(has_aliasing_ppgtt); \
>         func(has_csr); \
>         func(has_ddi); \
>         func(has_dp_mst); \
>         func(has_reset_engine); \
>         func(has_fbc); \
>         func(has_fpga_dbg); \
> -       func(has_full_ppgtt); \
> -       func(has_full_48bit_ppgtt); \
>         func(has_gmch_display); \
>         func(has_guc); \
>         func(has_guc_ct); \
> @@ -154,6 +158,7 @@ struct intel_device_info {
>         enum intel_platform platform;
>         u32 platform_mask;
>  
> +       enum intel_ppgtt ppgtt;
>         unsigned int page_sizes; /* page sizes supported by the HW */
>  
>         u32 display_mmio_offset;
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 4b28225320ff..3836a8a3761a 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -418,9 +418,8 @@ execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
>  
>  static u64 execlists_update_context(struct i915_request *rq)
>  {
> +       struct i915_hw_ppgtt *ppgtt = rq->gem_context->ppgtt;
>         struct intel_context *ce = rq->hw_context;
> -       struct i915_hw_ppgtt *ppgtt =
> -               rq->gem_context->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
>         u32 *reg_state = ce->lrc_reg_state;
>  
>         reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail);
> @@ -1376,7 +1375,7 @@ execlists_context_pin(struct intel_engine_cs *engine,
>         struct intel_context *ce = to_intel_context(ctx, engine);
>  
>         lockdep_assert_held(&ctx->i915->drm.struct_mutex);
> -       GEM_BUG_ON(!(ctx->ppgtt ?: ctx->i915->mm.aliasing_ppgtt));
> +       GEM_BUG_ON(!ctx->ppgtt);
>  
>         if (likely(ce->pin_count++))
>                 return ce;
> @@ -2031,8 +2030,7 @@ static int gen8_emit_bb_start(struct i915_request *rq,
>          * it is unsafe in case of lite-restore (because the ctx is
>          * not idle). PML4 is allocated during ppgtt init so this is
>          * not needed in 48-bit.*/
> -       if (rq->gem_context->ppgtt &&
> -           (intel_engine_flag(rq->engine) & rq->gem_context->ppgtt->pd_dirty_rings) &&
> +       if ((intel_engine_flag(rq->engine) & rq->gem_context->ppgtt->pd_dirty_rings) &&
>             !i915_vm_is_48bit(&rq->gem_context->ppgtt->vm) &&
>             !intel_vgpu_active(rq->i915)) {
>                 ret = intel_logical_ring_emit_pdps(rq);
> @@ -2634,7 +2632,6 @@ static void execlists_init_reg_state(u32 *regs,
>                                      struct intel_ring *ring)
>  {
>         struct drm_i915_private *dev_priv = engine->i915;
> -       struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: dev_priv->mm.aliasing_ppgtt;
>         u32 base = engine->mmio_base;
>         bool rcs = engine->class == RENDER_CLASS;
>  
> @@ -2706,12 +2703,12 @@ static void execlists_init_reg_state(u32 *regs,
>         CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
>         CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
>  
> -       if (i915_vm_is_48bit(&ppgtt->vm)) {
> +       if (i915_vm_is_48bit(&ctx->ppgtt->vm)) {
>                 /* 64b PPGTT (48bit canonical)
>                  * PDP0_DESCRIPTOR contains the base address to PML4 and
>                  * other PDP Descriptors are ignored.
>                  */
> -               ASSIGN_CTX_PML4(ppgtt, regs);
> +               ASSIGN_CTX_PML4(ctx->ppgtt, regs);
>         }
>  
>         if (rcs) {
> diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
> index 8d03f64eabd7..09ea65a29d98 100644
> --- a/drivers/gpu/drm/i915/selftests/huge_pages.c
> +++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
> @@ -1436,7 +1436,7 @@ static int igt_ppgtt_pin_update(void *arg)
>          * huge-gtt-pages.
>          */
>  
> -       if (!USES_FULL_48BIT_PPGTT(dev_priv)) {
> +       if (!HAS_FULL_48BIT_PPGTT(dev_priv)) {
>                 pr_info("48b PPGTT not supported, skipping\n");
>                 return 0;
>         }
> @@ -1687,10 +1687,9 @@ int i915_gem_huge_page_mock_selftests(void)
>                 SUBTEST(igt_mock_ppgtt_huge_fill),
>                 SUBTEST(igt_mock_ppgtt_64K),
>         };
> -       int saved_ppgtt = i915_modparams.enable_ppgtt;
>         struct drm_i915_private *dev_priv;
> -       struct pci_dev *pdev;
>         struct i915_hw_ppgtt *ppgtt;
> +       struct pci_dev *pdev;
>         int err;
>  
>         dev_priv = mock_gem_device();
> @@ -1698,7 +1697,7 @@ int i915_gem_huge_page_mock_selftests(void)
>                 return -ENOMEM;
>  
>         /* Pretend to be a device which supports the 48b PPGTT */
> -       i915_modparams.enable_ppgtt = 3;
> +       mkwrite_device_info(dev_priv)->ppgtt = INTEL_PPGTT_FULL_4LVL;
>  
>         pdev = dev_priv->drm.pdev;
>         dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(39));
> @@ -1731,9 +1730,6 @@ int i915_gem_huge_page_mock_selftests(void)
>  
>  out_unlock:
>         mutex_unlock(&dev_priv->drm.struct_mutex);
> -
> -       i915_modparams.enable_ppgtt = saved_ppgtt;
> -
>         drm_dev_put(&dev_priv->drm);
>  
>         return err;
> @@ -1753,7 +1749,7 @@ int i915_gem_huge_page_live_selftests(struct drm_i915_private *dev_priv)
>         struct i915_gem_context *ctx;
>         int err;
>  
> -       if (!USES_PPGTT(dev_priv)) {
> +       if (!HAS_PPGTT(dev_priv)) {
>                 pr_info("PPGTT not supported, skipping live-selftests\n");
>                 return 0;
>         }
> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> index 76df25aa90c9..913c0f83f86a 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> @@ -535,7 +535,6 @@ static int igt_ctx_exec(void *arg)
>         IGT_TIMEOUT(end_time);
>         LIST_HEAD(objects);
>         unsigned long ncontexts, ndwords, dw;
> -       bool first_shared_gtt = true;
>         int err = -ENODEV;
>  
>         /*
> @@ -561,12 +560,7 @@ static int igt_ctx_exec(void *arg)
>                 struct i915_gem_context *ctx;
>                 unsigned int id;
>  
> -               if (first_shared_gtt) {
> -                       ctx = __create_hw_context(i915, file->driver_priv);
> -                       first_shared_gtt = false;
> -               } else {
> -                       ctx = i915_gem_create_context(i915, file->driver_priv);
> -               }
> +               ctx = i915_gem_create_context(i915, file->driver_priv);
>                 if (IS_ERR(ctx)) {
>                         err = PTR_ERR(ctx);
>                         goto out_unlock;
> @@ -865,33 +859,6 @@ static int igt_switch_to_kernel_context(void *arg)
>         return err;
>  }
>  
> -static int fake_aliasing_ppgtt_enable(struct drm_i915_private *i915)
> -{
> -       struct drm_i915_gem_object *obj;
> -       int err;
> -
> -       err = i915_gem_init_aliasing_ppgtt(i915);
> -       if (err)
> -               return err;
> -
> -       list_for_each_entry(obj, &i915->mm.bound_list, mm.link) {
> -               struct i915_vma *vma;
> -
> -               vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
> -               if (IS_ERR(vma))
> -                       continue;
> -
> -               vma->flags &= ~I915_VMA_LOCAL_BIND;
> -       }
> -
> -       return 0;
> -}
> -
> -static void fake_aliasing_ppgtt_disable(struct drm_i915_private *i915)
> -{
> -       i915_gem_fini_aliasing_ppgtt(i915);
> -}
> -
>  int i915_gem_context_mock_selftests(void)
>  {
>         static const struct i915_subtest tests[] = {
> @@ -918,31 +885,9 @@ int i915_gem_context_live_selftests(struct drm_i915_private *dev_priv)
>                 SUBTEST(igt_ctx_exec),
>                 SUBTEST(igt_ctx_readonly),
>         };
> -       bool fake_alias = false;
> -       int err;
>  
>         if (i915_terminally_wedged(&dev_priv->gpu_error))
>                 return 0;
>  
> -       /* Install a fake aliasing gtt for exercise */
> -       if (USES_PPGTT(dev_priv) && !dev_priv->mm.aliasing_ppgtt) {
> -               mutex_lock(&dev_priv->drm.struct_mutex);
> -               err = fake_aliasing_ppgtt_enable(dev_priv);
> -               mutex_unlock(&dev_priv->drm.struct_mutex);
> -               if (err)
> -                       return err;
> -
> -               GEM_BUG_ON(!dev_priv->mm.aliasing_ppgtt);
> -               fake_alias = true;
> -       }
> -
> -       err = i915_subtests(tests, dev_priv);
> -
> -       if (fake_alias) {
> -               mutex_lock(&dev_priv->drm.struct_mutex);
> -               fake_aliasing_ppgtt_disable(dev_priv);
> -               mutex_unlock(&dev_priv->drm.struct_mutex);
> -       }
> -
> -       return err;
> +       return i915_subtests(tests, dev_priv);
>  }
> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
> index 128ad1cf0647..4365979d8222 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
> @@ -351,7 +351,7 @@ static int igt_evict_contexts(void *arg)
>          * where the GTT space of the request is separate from the GGTT
>          * allocation required to build the request.
>          */
> -       if (!USES_FULL_PPGTT(i915))
> +       if (!HAS_FULL_PPGTT(i915))
>                 return 0;
>  
>         mutex_lock(&i915->drm.struct_mutex);
> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> index 8e2e269db97e..17b5aaaa7a50 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> @@ -153,7 +153,7 @@ static int igt_ppgtt_alloc(void *arg)
>  
>         /* Allocate a ppggt and try to fill the entire range */
>  
> -       if (!USES_PPGTT(dev_priv))
> +       if (!HAS_PPGTT(dev_priv))
>                 return 0;
>  
>         ppgtt = __hw_ppgtt_create(dev_priv);
> @@ -1001,7 +1001,7 @@ static int exercise_ppgtt(struct drm_i915_private *dev_priv,
>         IGT_TIMEOUT(end_time);
>         int err;
>  
> -       if (!USES_FULL_PPGTT(dev_priv))
> +       if (!HAS_FULL_PPGTT(dev_priv))
>                 return 0;
>  
>         file = mock_file(dev_priv);
> -- 
> 2.19.0
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v4] drm/i915: Remove i915.enable_ppgtt override
  2018-09-25 11:48 [PATCH v4] drm/i915: Remove i915.enable_ppgtt override Chris Wilson
                   ` (3 preceding siblings ...)
  2018-09-25 13:22 ` [PATCH v4] " Joonas Lahtinen
@ 2018-09-25 13:27 ` Joonas Lahtinen
  2018-09-26 13:16   ` Joonas Lahtinen
  2018-09-26 20:12 ` [PATCH v5] " Chris Wilson
                   ` (3 subsequent siblings)
  8 siblings, 1 reply; 24+ messages in thread
From: Joonas Lahtinen @ 2018-09-25 13:27 UTC (permalink / raw)
  To: Chris Wilson, intel-gfx; +Cc: Matthew Auld

Quoting Chris Wilson (2018-09-25 14:48:20)
> Now that we are confident in providing full-ppgtt where supported,
> remove the ability to override the context isolation.
> 
> v2: Remove faked aliasing-ppgtt for testing as it no longer is accepted.
> v3: s/USES/HAS/ to match usage and reject attempts to load the module on
> old GVT-g setups that do not provide support for full-ppgtt.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>

<SNIP>

> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -345,7 +345,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
>                 value = HAS_WT(dev_priv);
>                 break;
>         case I915_PARAM_HAS_ALIASING_PPGTT:
> -               value = USES_PPGTT(dev_priv);
> +               value = INTEL_PPGTT(dev_priv);
>                 break;

Luckily nobody has decided to renumber the modparam values for the sake
of our uAPI :P

Maybe best to have the values in uapi header and then add a translation
here to avoid such a problem in the future. I'd prefer to limit to just
relying the information of 0 (none), 1 (aliasing) or 2 (full) unless
somebody has slipped in code to userspace that relies on detecting the
48-bits from here instead the right place...

Regards, Joonas
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v4] drm/i915: Remove i915.enable_ppgtt override
  2018-09-25 13:22 ` [PATCH v4] " Joonas Lahtinen
@ 2018-09-25 18:01   ` Zhi Wang
  2018-09-26  1:06     ` He, Min
  0 siblings, 1 reply; 24+ messages in thread
From: Zhi Wang @ 2018-09-25 18:01 UTC (permalink / raw)
  To: Joonas Lahtinen, Chris Wilson, intel-gfx, Zhenyu Wang; +Cc: Matthew Auld

Hi Min:

I remembered the IOTG guest kernel is using aliasing-ppgtt in the last 
technical sharing (probably I didn't remember it correctly). Can you 
confirm?

Also, thanks Joonas for the reminding. :)

thanks,
Zhi.

On 09/25/18 09:22, Joonas Lahtinen wrote:
> + Zhi and Zhenyu
> 
> For me the patch looks ok.
> 
> It refuses to load GVT on systems where 48-bit is not supported, for not
> worsening the system security when virtualization is enabled (as anybody
> would probably expect virtualization to improve that). Please see code.
> 
> Do we have such systems in the wild? Should we instruct the user to
> updating the hypervisor to specific kernel version when they hit the
> error?
> 
> Regards, Joonas
> 
> Quoting Chris Wilson (2018-09-25 14:48:20)
>> Now that we are confident in providing full-ppgtt where supported,
>> remove the ability to override the context isolation.
>>
>> v2: Remove faked aliasing-ppgtt for testing as it no longer is accepted.
>> v3: s/USES/HAS/ to match usage and reject attempts to load the module on
>> old GVT-g setups that do not provide support for full-ppgtt.
>>
>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> Cc: Matthew Auld <matthew.auld@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_drv.c               | 22 +++--
>>   drivers/gpu/drm/i915/i915_drv.h               | 14 +--
>>   drivers/gpu/drm/i915/i915_gem_context.c       |  2 +-
>>   drivers/gpu/drm/i915/i915_gem_gtt.c           | 88 ++-----------------
>>   drivers/gpu/drm/i915/i915_gpu_error.c         |  4 +-
>>   drivers/gpu/drm/i915/i915_params.c            |  4 -
>>   drivers/gpu/drm/i915/i915_params.h            |  1 -
>>   drivers/gpu/drm/i915/i915_pci.c               | 17 ++--
>>   drivers/gpu/drm/i915/intel_device_info.c      |  6 ++
>>   drivers/gpu/drm/i915/intel_device_info.h      | 11 ++-
>>   drivers/gpu/drm/i915/intel_lrc.c              | 13 ++-
>>   drivers/gpu/drm/i915/selftests/huge_pages.c   | 12 +--
>>   .../gpu/drm/i915/selftests/i915_gem_context.c | 59 +------------
>>   .../gpu/drm/i915/selftests/i915_gem_evict.c   |  2 +-
>>   drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |  4 +-
>>   15 files changed, 62 insertions(+), 197 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>> index 44e2c0f5ec50..3efbbc71c3b4 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -345,7 +345,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
>>                  value = HAS_WT(dev_priv);
>>                  break;
>>          case I915_PARAM_HAS_ALIASING_PPGTT:
>> -               value = USES_PPGTT(dev_priv);
>> +               value = INTEL_PPGTT(dev_priv);
>>                  break;
>>          case I915_PARAM_HAS_SEMAPHORES:
>>                  value = HAS_LEGACY_SEMAPHORES(dev_priv);
>> @@ -1049,17 +1049,6 @@ static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
>>   
>>   static void intel_sanitize_options(struct drm_i915_private *dev_priv)
>>   {
>> -       /*
>> -        * i915.enable_ppgtt is read-only, so do an early pass to validate the
>> -        * user's requested state against the hardware/driver capabilities.  We
>> -        * do this now so that we can print out any log messages once rather
>> -        * than every time we check intel_enable_ppgtt().
>> -        */
>> -       i915_modparams.enable_ppgtt =
>> -               intel_sanitize_enable_ppgtt(dev_priv,
>> -                                           i915_modparams.enable_ppgtt);
>> -       DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
>> -
>>          intel_gvt_sanitize_options(dev_priv);
>>   }
>>   
>> @@ -1374,6 +1363,15 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
>>   
>>          intel_device_info_runtime_init(mkwrite_device_info(dev_priv));
>>   
>> +       if (HAS_PPGTT(dev_priv)) {
>> +               if (intel_vgpu_active(dev_priv) &&
>> +                   !intel_vgpu_has_full_48bit_ppgtt(dev_priv)) {
>> +                       i915_report_error(dev_priv,
>> +                                         "incompatible vGPU found, support for isolated ppGTT required\n");
>> +                       return -ENXIO;
>> +               }
>> +       }
>> +
>>          intel_sanitize_options(dev_priv);
>>   
>>          i915_perf_init(dev_priv);
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 8624b4bdc242..f28b3c2a3cd2 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -2593,9 +2593,14 @@ intel_info(const struct drm_i915_private *dev_priv)
>>   
>>   #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
>>   
>> -#define USES_PPGTT(dev_priv)           (i915_modparams.enable_ppgtt)
>> -#define USES_FULL_PPGTT(dev_priv)      (i915_modparams.enable_ppgtt >= 2)
>> -#define USES_FULL_48BIT_PPGTT(dev_priv)        (i915_modparams.enable_ppgtt == 3)
>> +#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt)
>> +#define HAS_PPGTT(dev_priv) \
>> +       (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
>> +#define HAS_FULL_PPGTT(dev_priv) \
>> +       (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
>> +#define HAS_FULL_48BIT_PPGTT(dev_priv) \
>> +       (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL_4LVL)
>> +
>>   #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
>>          GEM_BUG_ON((sizes) == 0); \
>>          ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
>> @@ -2743,9 +2748,6 @@ intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
>>          return IS_BROXTON(dev_priv) && intel_vtd_active();
>>   }
>>   
>> -int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
>> -                               int enable_ppgtt);
>> -
>>   /* i915_drv.c */
>>   void __printf(3, 4)
>>   __i915_printk(struct drm_i915_private *dev_priv, const char *level,
>> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
>> index f772593b99ab..15c92f75b1b8 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_context.c
>> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
>> @@ -414,7 +414,7 @@ i915_gem_create_context(struct drm_i915_private *dev_priv,
>>          if (IS_ERR(ctx))
>>                  return ctx;
>>   
>> -       if (USES_FULL_PPGTT(dev_priv)) {
>> +       if (HAS_FULL_PPGTT(dev_priv)) {
>>                  struct i915_hw_ppgtt *ppgtt;
>>   
>>                  ppgtt = i915_ppgtt_create(dev_priv, file_priv);
>> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> index f6c7ab413081..c9363504949f 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
>> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> @@ -133,55 +133,6 @@ static inline void i915_ggtt_invalidate(struct drm_i915_private *i915)
>>          i915->ggtt.invalidate(i915);
>>   }
>>   
>> -int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
>> -                               int enable_ppgtt)
>> -{
>> -       bool has_full_ppgtt;
>> -       bool has_full_48bit_ppgtt;
>> -
>> -       if (!dev_priv->info.has_aliasing_ppgtt)
>> -               return 0;
>> -
>> -       has_full_ppgtt = dev_priv->info.has_full_ppgtt;
>> -       has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt;
>> -
>> -       if (intel_vgpu_active(dev_priv)) {
>> -               /* GVT-g has no support for 32bit ppgtt */
>> -               has_full_ppgtt = false;
>> -               has_full_48bit_ppgtt = intel_vgpu_has_full_48bit_ppgtt(dev_priv);
>> -       }
>> -
>> -       /*
>> -        * We don't allow disabling PPGTT for gen8+ as it's a requirement for
>> -        * execlists, the sole mechanism available to submit work.
>> -        */
>> -       if (enable_ppgtt == 0 && !HAS_EXECLISTS(dev_priv))
>> -               return 0;
>> -
>> -       if (enable_ppgtt == 1)
>> -               return 1;
>> -
>> -       if (enable_ppgtt == 2 && has_full_ppgtt)
>> -               return 2;
>> -
>> -       if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
>> -               return 3;
>> -
>> -       /* Disable ppgtt on SNB if VT-d is on. */
>> -       if (IS_GEN6(dev_priv) && intel_vtd_active()) {
>> -               DRM_INFO("Disabling PPGTT because VT-d is on\n");
>> -               return 0;
>> -       }
>> -
>> -       if (has_full_48bit_ppgtt)
>> -               return 3;
>> -
>> -       if (has_full_ppgtt)
>> -               return 2;
>> -
>> -       return 1;
>> -}
>> -
>>   static int ppgtt_bind_vma(struct i915_vma *vma,
>>                            enum i915_cache_level cache_level,
>>                            u32 unused)
>> @@ -1647,7 +1598,7 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
>>          ppgtt->vm.i915 = i915;
>>          ppgtt->vm.dma = &i915->drm.pdev->dev;
>>   
>> -       ppgtt->vm.total = USES_FULL_48BIT_PPGTT(i915) ?
>> +       ppgtt->vm.total = HAS_FULL_48BIT_PPGTT(i915) ?
>>                  1ULL << 48 :
>>                  1ULL << 32;
>>   
>> @@ -1782,19 +1733,6 @@ static inline void gen6_write_pde(const struct gen6_hw_ppgtt *ppgtt,
>>                    ppgtt->pd_addr + pde);
>>   }
>>   
>> -static void gen8_ppgtt_enable(struct drm_i915_private *dev_priv)
>> -{
>> -       struct intel_engine_cs *engine;
>> -       enum intel_engine_id id;
>> -
>> -       for_each_engine(engine, dev_priv, id) {
>> -               u32 four_level = USES_FULL_48BIT_PPGTT(dev_priv) ?
>> -                                GEN8_GFX_PPGTT_48B : 0;
>> -               I915_WRITE(RING_MODE_GEN7(engine),
>> -                          _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
>> -       }
>> -}
>> -
>>   static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv)
>>   {
>>          struct intel_engine_cs *engine;
>> @@ -1834,7 +1772,8 @@ static void gen6_ppgtt_enable(struct drm_i915_private *dev_priv)
>>          ecochk = I915_READ(GAM_ECOCHK);
>>          I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
>>   
>> -       I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
>> +       if (HAS_PPGTT(dev_priv)) /* may be disabled for VT-d */
>> +               I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
>>   }
>>   
>>   /* PPGTT support for Sandybdrige/Gen6 and later */
>> @@ -2237,23 +2176,10 @@ int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv)
>>   {
>>          gtt_write_workarounds(dev_priv);
>>   
>> -       /* In the case of execlists, PPGTT is enabled by the context descriptor
>> -        * and the PDPs are contained within the context itself.  We don't
>> -        * need to do anything here. */
>> -       if (HAS_LOGICAL_RING_CONTEXTS(dev_priv))
>> -               return 0;
>> -
>> -       if (!USES_PPGTT(dev_priv))
>> -               return 0;
>> -
>>          if (IS_GEN6(dev_priv))
>>                  gen6_ppgtt_enable(dev_priv);
>>          else if (IS_GEN7(dev_priv))
>>                  gen7_ppgtt_enable(dev_priv);
>> -       else if (INTEL_GEN(dev_priv) >= 8)
>> -               gen8_ppgtt_enable(dev_priv);
>> -       else
>> -               MISSING_CASE(INTEL_GEN(dev_priv));
>>   
>>          return 0;
>>   }
>> @@ -2952,7 +2878,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
>>          /* And finally clear the reserved guard page */
>>          ggtt->vm.clear_range(&ggtt->vm, ggtt->vm.total - PAGE_SIZE, PAGE_SIZE);
>>   
>> -       if (USES_PPGTT(dev_priv) && !USES_FULL_PPGTT(dev_priv)) {
>> +       if (INTEL_PPGTT(dev_priv) == INTEL_PPGTT_ALIASING) {
>>                  ret = i915_gem_init_aliasing_ppgtt(dev_priv);
>>                  if (ret)
>>                          goto err;
>> @@ -3275,7 +3201,7 @@ static void bdw_setup_private_ppat(struct intel_ppat *ppat)
>>          ppat->match = bdw_private_pat_match;
>>          ppat->clear_value = GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3);
>>   
>> -       if (!USES_PPGTT(ppat->i915)) {
>> +       if (!HAS_PPGTT(ppat->i915)) {
>>                  /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
>>                   * so RTL will always use the value corresponding to
>>                   * pat_sel = 000".
>> @@ -3402,7 +3328,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
>>          ggtt->vm.cleanup = gen6_gmch_remove;
>>          ggtt->vm.insert_page = gen8_ggtt_insert_page;
>>          ggtt->vm.clear_range = nop_clear_range;
>> -       if (!USES_FULL_PPGTT(dev_priv) || intel_scanout_needs_vtd_wa(dev_priv))
>> +       if (intel_scanout_needs_vtd_wa(dev_priv))
>>                  ggtt->vm.clear_range = gen8_ggtt_clear_range;
>>   
>>          ggtt->vm.insert_entries = gen8_ggtt_insert_entries;
>> @@ -3609,7 +3535,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
>>          /* Only VLV supports read-only GGTT mappings */
>>          ggtt->vm.has_read_only = IS_VALLEYVIEW(dev_priv);
>>   
>> -       if (!HAS_LLC(dev_priv) && !USES_PPGTT(dev_priv))
>> +       if (!HAS_LLC(dev_priv) && !HAS_PPGTT(dev_priv))
>>                  ggtt->vm.mm.color_adjust = i915_gtt_color_adjust;
>>          mutex_unlock(&dev_priv->drm.struct_mutex);
>>   
>> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
>> index 2835cacd0d08..3d5554f14dfd 100644
>> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
>> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
>> @@ -474,7 +474,7 @@ static void error_print_engine(struct drm_i915_error_state_buf *m,
>>                          err_printf(m, "  SYNC_2: 0x%08x\n",
>>                                     ee->semaphore_mboxes[2]);
>>          }
>> -       if (USES_PPGTT(m->i915)) {
>> +       if (HAS_PPGTT(m->i915)) {
>>                  err_printf(m, "  GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
>>   
>>                  if (INTEL_GEN(m->i915) >= 8) {
>> @@ -1230,7 +1230,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
>>          ee->reset_count = i915_reset_engine_count(&dev_priv->gpu_error,
>>                                                    engine);
>>   
>> -       if (USES_PPGTT(dev_priv)) {
>> +       if (HAS_PPGTT(dev_priv)) {
>>                  int i;
>>   
>>                  ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
>> diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
>> index 295e981e4a39..bd6bd8879cab 100644
>> --- a/drivers/gpu/drm/i915/i915_params.c
>> +++ b/drivers/gpu/drm/i915/i915_params.c
>> @@ -82,10 +82,6 @@ i915_param_named_unsafe(enable_hangcheck, bool, 0644,
>>          "WARNING: Disabling this can cause system wide hangs. "
>>          "(default: true)");
>>   
>> -i915_param_named_unsafe(enable_ppgtt, int, 0400,
>> -       "Override PPGTT usage. "
>> -       "(-1=auto [default], 0=disabled, 1=aliasing, 2=full, 3=full with extended address space)");
>> -
>>   i915_param_named_unsafe(enable_psr, int, 0600,
>>          "Enable PSR "
>>          "(0=disabled, 1=enabled) "
>> diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
>> index 6c4d4a21474b..7e56c516c815 100644
>> --- a/drivers/gpu/drm/i915/i915_params.h
>> +++ b/drivers/gpu/drm/i915/i915_params.h
>> @@ -41,7 +41,6 @@ struct drm_printer;
>>          param(int, vbt_sdvo_panel_type, -1) \
>>          param(int, enable_dc, -1) \
>>          param(int, enable_fbc, -1) \
>> -       param(int, enable_ppgtt, -1) \
>>          param(int, enable_psr, -1) \
>>          param(int, disable_power_well, -1) \
>>          param(int, enable_ips, 1) \
>> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
>> index d6f7b9fe1d26..eeec902896b9 100644
>> --- a/drivers/gpu/drm/i915/i915_pci.c
>> +++ b/drivers/gpu/drm/i915/i915_pci.c
>> @@ -252,7 +252,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
>>          .has_llc = 1, \
>>          .has_rc6 = 1, \
>>          .has_rc6p = 1, \
>> -       .has_aliasing_ppgtt = 1, \
>> +       .ppgtt = INTEL_PPGTT_ALIASING, \
>>          GEN_DEFAULT_PIPEOFFSETS, \
>>          GEN_DEFAULT_PAGE_SIZES, \
>>          CURSOR_OFFSETS
>> @@ -297,8 +297,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
>>          .has_llc = 1, \
>>          .has_rc6 = 1, \
>>          .has_rc6p = 1, \
>> -       .has_aliasing_ppgtt = 1, \
>> -       .has_full_ppgtt = 1, \
>> +       .ppgtt = INTEL_PPGTT_FULL, \
>>          GEN_DEFAULT_PIPEOFFSETS, \
>>          GEN_DEFAULT_PAGE_SIZES, \
>>          IVB_CURSOR_OFFSETS
>> @@ -351,8 +350,7 @@ static const struct intel_device_info intel_valleyview_info = {
>>          .has_rc6 = 1,
>>          .has_gmch_display = 1,
>>          .has_hotplug = 1,
>> -       .has_aliasing_ppgtt = 1,
>> -       .has_full_ppgtt = 1,
>> +       .ppgtt = INTEL_PPGTT_FULL,
>>          .has_snoop = true,
>>          .has_coherent_ggtt = false,
>>          .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
>> @@ -399,7 +397,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
>>          .page_sizes = I915_GTT_PAGE_SIZE_4K | \
>>                        I915_GTT_PAGE_SIZE_2M, \
>>          .has_logical_ring_contexts = 1, \
>> -       .has_full_48bit_ppgtt = 1, \
>> +       .ppgtt = INTEL_PPGTT_FULL_4LVL, \
>>          .has_64bit_reloc = 1, \
>>          .has_reset_engine = 1
>>   
>> @@ -443,8 +441,7 @@ static const struct intel_device_info intel_cherryview_info = {
>>          .has_rc6 = 1,
>>          .has_logical_ring_contexts = 1,
>>          .has_gmch_display = 1,
>> -       .has_aliasing_ppgtt = 1,
>> -       .has_full_ppgtt = 1,
>> +       .ppgtt = INTEL_PPGTT_FULL,
>>          .has_reset_engine = 1,
>>          .has_snoop = true,
>>          .has_coherent_ggtt = false,
>> @@ -518,9 +515,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
>>          .has_logical_ring_contexts = 1, \
>>          .has_logical_ring_preemption = 1, \
>>          .has_guc = 1, \
>> -       .has_aliasing_ppgtt = 1, \
>> -       .has_full_ppgtt = 1, \
>> -       .has_full_48bit_ppgtt = 1, \
>> +       .ppgtt = INTEL_PPGTT_FULL_4LVL, \
>>          .has_reset_engine = 1, \
>>          .has_snoop = true, \
>>          .has_coherent_ggtt = false, \
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>> index 0ef0c6448d53..a841d181efd3 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>> @@ -26,6 +26,7 @@
>>   
>>   #include "intel_device_info.h"
>>   #include "i915_drv.h"
>> +#include "i915_vgpu.h"
>>   
>>   #define PLATFORM_NAME(x) [INTEL_##x] = #x
>>   static const char * const platform_names[] = {
>> @@ -851,6 +852,11 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
>>          else if (INTEL_GEN(dev_priv) >= 11)
>>                  gen11_sseu_info_init(dev_priv);
>>   
>> +       if (IS_GEN6(dev_priv) && intel_vtd_active()) {
>> +               DRM_INFO("Disabling ppGTT for VT-d support\n");
>> +               info->ppgtt = INTEL_PPGTT_NONE;
>> +       }
>> +
>>          /* Initialize command stream timestamp frequency */
>>          info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
>>   }
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
>> index 6eecd64734d5..6bab97687328 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.h
>> +++ b/drivers/gpu/drm/i915/intel_device_info.h
>> @@ -74,21 +74,25 @@ enum intel_platform {
>>          INTEL_MAX_PLATFORMS
>>   };
>>   
>> +enum intel_ppgtt {
>> +       INTEL_PPGTT_NONE = 0,
>> +       INTEL_PPGTT_ALIASING,
>> +       INTEL_PPGTT_FULL,
>> +       INTEL_PPGTT_FULL_4LVL,
>> +};
>> +
>>   #define DEV_INFO_FOR_EACH_FLAG(func) \
>>          func(is_mobile); \
>>          func(is_lp); \
>>          func(is_alpha_support); \
>>          /* Keep has_* in alphabetical order */ \
>>          func(has_64bit_reloc); \
>> -       func(has_aliasing_ppgtt); \
>>          func(has_csr); \
>>          func(has_ddi); \
>>          func(has_dp_mst); \
>>          func(has_reset_engine); \
>>          func(has_fbc); \
>>          func(has_fpga_dbg); \
>> -       func(has_full_ppgtt); \
>> -       func(has_full_48bit_ppgtt); \
>>          func(has_gmch_display); \
>>          func(has_guc); \
>>          func(has_guc_ct); \
>> @@ -154,6 +158,7 @@ struct intel_device_info {
>>          enum intel_platform platform;
>>          u32 platform_mask;
>>   
>> +       enum intel_ppgtt ppgtt;
>>          unsigned int page_sizes; /* page sizes supported by the HW */
>>   
>>          u32 display_mmio_offset;
>> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
>> index 4b28225320ff..3836a8a3761a 100644
>> --- a/drivers/gpu/drm/i915/intel_lrc.c
>> +++ b/drivers/gpu/drm/i915/intel_lrc.c
>> @@ -418,9 +418,8 @@ execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
>>   
>>   static u64 execlists_update_context(struct i915_request *rq)
>>   {
>> +       struct i915_hw_ppgtt *ppgtt = rq->gem_context->ppgtt;
>>          struct intel_context *ce = rq->hw_context;
>> -       struct i915_hw_ppgtt *ppgtt =
>> -               rq->gem_context->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
>>          u32 *reg_state = ce->lrc_reg_state;
>>   
>>          reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail);
>> @@ -1376,7 +1375,7 @@ execlists_context_pin(struct intel_engine_cs *engine,
>>          struct intel_context *ce = to_intel_context(ctx, engine);
>>   
>>          lockdep_assert_held(&ctx->i915->drm.struct_mutex);
>> -       GEM_BUG_ON(!(ctx->ppgtt ?: ctx->i915->mm.aliasing_ppgtt));
>> +       GEM_BUG_ON(!ctx->ppgtt);
>>   
>>          if (likely(ce->pin_count++))
>>                  return ce;
>> @@ -2031,8 +2030,7 @@ static int gen8_emit_bb_start(struct i915_request *rq,
>>           * it is unsafe in case of lite-restore (because the ctx is
>>           * not idle). PML4 is allocated during ppgtt init so this is
>>           * not needed in 48-bit.*/
>> -       if (rq->gem_context->ppgtt &&
>> -           (intel_engine_flag(rq->engine) & rq->gem_context->ppgtt->pd_dirty_rings) &&
>> +       if ((intel_engine_flag(rq->engine) & rq->gem_context->ppgtt->pd_dirty_rings) &&
>>              !i915_vm_is_48bit(&rq->gem_context->ppgtt->vm) &&
>>              !intel_vgpu_active(rq->i915)) {
>>                  ret = intel_logical_ring_emit_pdps(rq);
>> @@ -2634,7 +2632,6 @@ static void execlists_init_reg_state(u32 *regs,
>>                                       struct intel_ring *ring)
>>   {
>>          struct drm_i915_private *dev_priv = engine->i915;
>> -       struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: dev_priv->mm.aliasing_ppgtt;
>>          u32 base = engine->mmio_base;
>>          bool rcs = engine->class == RENDER_CLASS;
>>   
>> @@ -2706,12 +2703,12 @@ static void execlists_init_reg_state(u32 *regs,
>>          CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
>>          CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
>>   
>> -       if (i915_vm_is_48bit(&ppgtt->vm)) {
>> +       if (i915_vm_is_48bit(&ctx->ppgtt->vm)) {
>>                  /* 64b PPGTT (48bit canonical)
>>                   * PDP0_DESCRIPTOR contains the base address to PML4 and
>>                   * other PDP Descriptors are ignored.
>>                   */
>> -               ASSIGN_CTX_PML4(ppgtt, regs);
>> +               ASSIGN_CTX_PML4(ctx->ppgtt, regs);
>>          }
>>   
>>          if (rcs) {
>> diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
>> index 8d03f64eabd7..09ea65a29d98 100644
>> --- a/drivers/gpu/drm/i915/selftests/huge_pages.c
>> +++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
>> @@ -1436,7 +1436,7 @@ static int igt_ppgtt_pin_update(void *arg)
>>           * huge-gtt-pages.
>>           */
>>   
>> -       if (!USES_FULL_48BIT_PPGTT(dev_priv)) {
>> +       if (!HAS_FULL_48BIT_PPGTT(dev_priv)) {
>>                  pr_info("48b PPGTT not supported, skipping\n");
>>                  return 0;
>>          }
>> @@ -1687,10 +1687,9 @@ int i915_gem_huge_page_mock_selftests(void)
>>                  SUBTEST(igt_mock_ppgtt_huge_fill),
>>                  SUBTEST(igt_mock_ppgtt_64K),
>>          };
>> -       int saved_ppgtt = i915_modparams.enable_ppgtt;
>>          struct drm_i915_private *dev_priv;
>> -       struct pci_dev *pdev;
>>          struct i915_hw_ppgtt *ppgtt;
>> +       struct pci_dev *pdev;
>>          int err;
>>   
>>          dev_priv = mock_gem_device();
>> @@ -1698,7 +1697,7 @@ int i915_gem_huge_page_mock_selftests(void)
>>                  return -ENOMEM;
>>   
>>          /* Pretend to be a device which supports the 48b PPGTT */
>> -       i915_modparams.enable_ppgtt = 3;
>> +       mkwrite_device_info(dev_priv)->ppgtt = INTEL_PPGTT_FULL_4LVL;
>>   
>>          pdev = dev_priv->drm.pdev;
>>          dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(39));
>> @@ -1731,9 +1730,6 @@ int i915_gem_huge_page_mock_selftests(void)
>>   
>>   out_unlock:
>>          mutex_unlock(&dev_priv->drm.struct_mutex);
>> -
>> -       i915_modparams.enable_ppgtt = saved_ppgtt;
>> -
>>          drm_dev_put(&dev_priv->drm);
>>   
>>          return err;
>> @@ -1753,7 +1749,7 @@ int i915_gem_huge_page_live_selftests(struct drm_i915_private *dev_priv)
>>          struct i915_gem_context *ctx;
>>          int err;
>>   
>> -       if (!USES_PPGTT(dev_priv)) {
>> +       if (!HAS_PPGTT(dev_priv)) {
>>                  pr_info("PPGTT not supported, skipping live-selftests\n");
>>                  return 0;
>>          }
>> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
>> index 76df25aa90c9..913c0f83f86a 100644
>> --- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
>> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
>> @@ -535,7 +535,6 @@ static int igt_ctx_exec(void *arg)
>>          IGT_TIMEOUT(end_time);
>>          LIST_HEAD(objects);
>>          unsigned long ncontexts, ndwords, dw;
>> -       bool first_shared_gtt = true;
>>          int err = -ENODEV;
>>   
>>          /*
>> @@ -561,12 +560,7 @@ static int igt_ctx_exec(void *arg)
>>                  struct i915_gem_context *ctx;
>>                  unsigned int id;
>>   
>> -               if (first_shared_gtt) {
>> -                       ctx = __create_hw_context(i915, file->driver_priv);
>> -                       first_shared_gtt = false;
>> -               } else {
>> -                       ctx = i915_gem_create_context(i915, file->driver_priv);
>> -               }
>> +               ctx = i915_gem_create_context(i915, file->driver_priv);
>>                  if (IS_ERR(ctx)) {
>>                          err = PTR_ERR(ctx);
>>                          goto out_unlock;
>> @@ -865,33 +859,6 @@ static int igt_switch_to_kernel_context(void *arg)
>>          return err;
>>   }
>>   
>> -static int fake_aliasing_ppgtt_enable(struct drm_i915_private *i915)
>> -{
>> -       struct drm_i915_gem_object *obj;
>> -       int err;
>> -
>> -       err = i915_gem_init_aliasing_ppgtt(i915);
>> -       if (err)
>> -               return err;
>> -
>> -       list_for_each_entry(obj, &i915->mm.bound_list, mm.link) {
>> -               struct i915_vma *vma;
>> -
>> -               vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
>> -               if (IS_ERR(vma))
>> -                       continue;
>> -
>> -               vma->flags &= ~I915_VMA_LOCAL_BIND;
>> -       }
>> -
>> -       return 0;
>> -}
>> -
>> -static void fake_aliasing_ppgtt_disable(struct drm_i915_private *i915)
>> -{
>> -       i915_gem_fini_aliasing_ppgtt(i915);
>> -}
>> -
>>   int i915_gem_context_mock_selftests(void)
>>   {
>>          static const struct i915_subtest tests[] = {
>> @@ -918,31 +885,9 @@ int i915_gem_context_live_selftests(struct drm_i915_private *dev_priv)
>>                  SUBTEST(igt_ctx_exec),
>>                  SUBTEST(igt_ctx_readonly),
>>          };
>> -       bool fake_alias = false;
>> -       int err;
>>   
>>          if (i915_terminally_wedged(&dev_priv->gpu_error))
>>                  return 0;
>>   
>> -       /* Install a fake aliasing gtt for exercise */
>> -       if (USES_PPGTT(dev_priv) && !dev_priv->mm.aliasing_ppgtt) {
>> -               mutex_lock(&dev_priv->drm.struct_mutex);
>> -               err = fake_aliasing_ppgtt_enable(dev_priv);
>> -               mutex_unlock(&dev_priv->drm.struct_mutex);
>> -               if (err)
>> -                       return err;
>> -
>> -               GEM_BUG_ON(!dev_priv->mm.aliasing_ppgtt);
>> -               fake_alias = true;
>> -       }
>> -
>> -       err = i915_subtests(tests, dev_priv);
>> -
>> -       if (fake_alias) {
>> -               mutex_lock(&dev_priv->drm.struct_mutex);
>> -               fake_aliasing_ppgtt_disable(dev_priv);
>> -               mutex_unlock(&dev_priv->drm.struct_mutex);
>> -       }
>> -
>> -       return err;
>> +       return i915_subtests(tests, dev_priv);
>>   }
>> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
>> index 128ad1cf0647..4365979d8222 100644
>> --- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
>> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
>> @@ -351,7 +351,7 @@ static int igt_evict_contexts(void *arg)
>>           * where the GTT space of the request is separate from the GGTT
>>           * allocation required to build the request.
>>           */
>> -       if (!USES_FULL_PPGTT(i915))
>> +       if (!HAS_FULL_PPGTT(i915))
>>                  return 0;
>>   
>>          mutex_lock(&i915->drm.struct_mutex);
>> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
>> index 8e2e269db97e..17b5aaaa7a50 100644
>> --- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
>> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
>> @@ -153,7 +153,7 @@ static int igt_ppgtt_alloc(void *arg)
>>   
>>          /* Allocate a ppggt and try to fill the entire range */
>>   
>> -       if (!USES_PPGTT(dev_priv))
>> +       if (!HAS_PPGTT(dev_priv))
>>                  return 0;
>>   
>>          ppgtt = __hw_ppgtt_create(dev_priv);
>> @@ -1001,7 +1001,7 @@ static int exercise_ppgtt(struct drm_i915_private *dev_priv,
>>          IGT_TIMEOUT(end_time);
>>          int err;
>>   
>> -       if (!USES_FULL_PPGTT(dev_priv))
>> +       if (!HAS_FULL_PPGTT(dev_priv))
>>                  return 0;
>>   
>>          file = mock_file(dev_priv);
>> -- 
>> 2.19.0
>>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v4] drm/i915: Remove i915.enable_ppgtt override
  2018-09-25 18:01   ` Zhi Wang
@ 2018-09-26  1:06     ` He, Min
  2018-09-26  8:02       ` Joonas Lahtinen
  0 siblings, 1 reply; 24+ messages in thread
From: He, Min @ 2018-09-26  1:06 UTC (permalink / raw)
  To: Wang, Zhi A, Joonas Lahtinen, Chris Wilson, intel-gfx, Zhenyu Wang
  Cc: Auld, Matthew

No. We changed to full 48bit ppgtt long time ago. :)

> -----Original Message-----
> From: Wang, Zhi A
> Sent: Wednesday, September 26, 2018 2:01 AM
> To: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>; Chris Wilson
> <chris@chris-wilson.co.uk>; intel-gfx@lists.freedesktop.org; Zhenyu Wang
> <zhenyuw@linux.intel.com>
> Cc: Auld, Matthew <matthew.auld@intel.com>; He, Min <min.he@intel.com>
> Subject: Re: [PATCH v4] drm/i915: Remove i915.enable_ppgtt override
> 
> Hi Min:
> 
> I remembered the IOTG guest kernel is using aliasing-ppgtt in the last
> technical sharing (probably I didn't remember it correctly). Can you
> confirm?
> 
> Also, thanks Joonas for the reminding. :)
> 
> thanks,
> Zhi.
> 
> On 09/25/18 09:22, Joonas Lahtinen wrote:
> > + Zhi and Zhenyu
> >
> > For me the patch looks ok.
> >
> > It refuses to load GVT on systems where 48-bit is not supported, for not
> > worsening the system security when virtualization is enabled (as anybody
> > would probably expect virtualization to improve that). Please see code.
> >
> > Do we have such systems in the wild? Should we instruct the user to
> > updating the hypervisor to specific kernel version when they hit the
> > error?
> >
> > Regards, Joonas
> >
> > Quoting Chris Wilson (2018-09-25 14:48:20)
> >> Now that we are confident in providing full-ppgtt where supported,
> >> remove the ability to override the context isolation.
> >>
> >> v2: Remove faked aliasing-ppgtt for testing as it no longer is accepted.
> >> v3: s/USES/HAS/ to match usage and reject attempts to load the module
> on
> >> old GVT-g setups that do not provide support for full-ppgtt.
> >>
> >> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> >> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> >> Cc: Matthew Auld <matthew.auld@intel.com>
> >> ---
> >>   drivers/gpu/drm/i915/i915_drv.c               | 22 +++--
> >>   drivers/gpu/drm/i915/i915_drv.h               | 14 +--
> >>   drivers/gpu/drm/i915/i915_gem_context.c       |  2 +-
> >>   drivers/gpu/drm/i915/i915_gem_gtt.c           | 88 ++-----------------
> >>   drivers/gpu/drm/i915/i915_gpu_error.c         |  4 +-
> >>   drivers/gpu/drm/i915/i915_params.c            |  4 -
> >>   drivers/gpu/drm/i915/i915_params.h            |  1 -
> >>   drivers/gpu/drm/i915/i915_pci.c               | 17 ++--
> >>   drivers/gpu/drm/i915/intel_device_info.c      |  6 ++
> >>   drivers/gpu/drm/i915/intel_device_info.h      | 11 ++-
> >>   drivers/gpu/drm/i915/intel_lrc.c              | 13 ++-
> >>   drivers/gpu/drm/i915/selftests/huge_pages.c   | 12 +--
> >>   .../gpu/drm/i915/selftests/i915_gem_context.c | 59 +------------
> >>   .../gpu/drm/i915/selftests/i915_gem_evict.c   |  2 +-
> >>   drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |  4 +-
> >>   15 files changed, 62 insertions(+), 197 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_drv.c
> b/drivers/gpu/drm/i915/i915_drv.c
> >> index 44e2c0f5ec50..3efbbc71c3b4 100644
> >> --- a/drivers/gpu/drm/i915/i915_drv.c
> >> +++ b/drivers/gpu/drm/i915/i915_drv.c
> >> @@ -345,7 +345,7 @@ static int i915_getparam_ioctl(struct drm_device
> *dev, void *data,
> >>                  value = HAS_WT(dev_priv);
> >>                  break;
> >>          case I915_PARAM_HAS_ALIASING_PPGTT:
> >> -               value = USES_PPGTT(dev_priv);
> >> +               value = INTEL_PPGTT(dev_priv);
> >>                  break;
> >>          case I915_PARAM_HAS_SEMAPHORES:
> >>                  value = HAS_LEGACY_SEMAPHORES(dev_priv);
> >> @@ -1049,17 +1049,6 @@ static void i915_driver_cleanup_mmio(struct
> drm_i915_private *dev_priv)
> >>
> >>   static void intel_sanitize_options(struct drm_i915_private *dev_priv)
> >>   {
> >> -       /*
> >> -        * i915.enable_ppgtt is read-only, so do an early pass to validate the
> >> -        * user's requested state against the hardware/driver capabilities.
> We
> >> -        * do this now so that we can print out any log messages once rather
> >> -        * than every time we check intel_enable_ppgtt().
> >> -        */
> >> -       i915_modparams.enable_ppgtt =
> >> -               intel_sanitize_enable_ppgtt(dev_priv,
> >> -                                           i915_modparams.enable_ppgtt);
> >> -       DRM_DEBUG_DRIVER("ppgtt mode: %i\n",
> i915_modparams.enable_ppgtt);
> >> -
> >>          intel_gvt_sanitize_options(dev_priv);
> >>   }
> >>
> >> @@ -1374,6 +1363,15 @@ static int i915_driver_init_hw(struct
> drm_i915_private *dev_priv)
> >>
> >>          intel_device_info_runtime_init(mkwrite_device_info(dev_priv));
> >>
> >> +       if (HAS_PPGTT(dev_priv)) {
> >> +               if (intel_vgpu_active(dev_priv) &&
> >> +                   !intel_vgpu_has_full_48bit_ppgtt(dev_priv)) {
> >> +                       i915_report_error(dev_priv,
> >> +                                         "incompatible vGPU found, support for isolated
> ppGTT required\n");
> >> +                       return -ENXIO;
> >> +               }
> >> +       }
> >> +
> >>          intel_sanitize_options(dev_priv);
> >>
> >>          i915_perf_init(dev_priv);
> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> >> index 8624b4bdc242..f28b3c2a3cd2 100644
> >> --- a/drivers/gpu/drm/i915/i915_drv.h
> >> +++ b/drivers/gpu/drm/i915/i915_drv.h
> >> @@ -2593,9 +2593,14 @@ intel_info(const struct drm_i915_private
> *dev_priv)
> >>
> >>   #define HAS_EXECLISTS(dev_priv)
> HAS_LOGICAL_RING_CONTEXTS(dev_priv)
> >>
> >> -#define USES_PPGTT(dev_priv)           (i915_modparams.enable_ppgtt)
> >> -#define USES_FULL_PPGTT(dev_priv)
> (i915_modparams.enable_ppgtt >= 2)
> >> -#define USES_FULL_48BIT_PPGTT(dev_priv)
> (i915_modparams.enable_ppgtt == 3)
> >> +#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt)
> >> +#define HAS_PPGTT(dev_priv) \
> >> +       (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
> >> +#define HAS_FULL_PPGTT(dev_priv) \
> >> +       (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
> >> +#define HAS_FULL_48BIT_PPGTT(dev_priv) \
> >> +       (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL_4LVL)
> >> +
> >>   #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
> >>          GEM_BUG_ON((sizes) == 0); \
> >>          ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
> >> @@ -2743,9 +2748,6 @@ intel_ggtt_update_needs_vtd_wa(struct
> drm_i915_private *dev_priv)
> >>          return IS_BROXTON(dev_priv) && intel_vtd_active();
> >>   }
> >>
> >> -int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
> >> -                               int enable_ppgtt);
> >> -
> >>   /* i915_drv.c */
> >>   void __printf(3, 4)
> >>   __i915_printk(struct drm_i915_private *dev_priv, const char *level,
> >> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
> b/drivers/gpu/drm/i915/i915_gem_context.c
> >> index f772593b99ab..15c92f75b1b8 100644
> >> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> >> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> >> @@ -414,7 +414,7 @@ i915_gem_create_context(struct
> drm_i915_private *dev_priv,
> >>          if (IS_ERR(ctx))
> >>                  return ctx;
> >>
> >> -       if (USES_FULL_PPGTT(dev_priv)) {
> >> +       if (HAS_FULL_PPGTT(dev_priv)) {
> >>                  struct i915_hw_ppgtt *ppgtt;
> >>
> >>                  ppgtt = i915_ppgtt_create(dev_priv, file_priv);
> >> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> >> index f6c7ab413081..c9363504949f 100644
> >> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> >> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> >> @@ -133,55 +133,6 @@ static inline void i915_ggtt_invalidate(struct
> drm_i915_private *i915)
> >>          i915->ggtt.invalidate(i915);
> >>   }
> >>
> >> -int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
> >> -                               int enable_ppgtt)
> >> -{
> >> -       bool has_full_ppgtt;
> >> -       bool has_full_48bit_ppgtt;
> >> -
> >> -       if (!dev_priv->info.has_aliasing_ppgtt)
> >> -               return 0;
> >> -
> >> -       has_full_ppgtt = dev_priv->info.has_full_ppgtt;
> >> -       has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt;
> >> -
> >> -       if (intel_vgpu_active(dev_priv)) {
> >> -               /* GVT-g has no support for 32bit ppgtt */
> >> -               has_full_ppgtt = false;
> >> -               has_full_48bit_ppgtt =
> intel_vgpu_has_full_48bit_ppgtt(dev_priv);
> >> -       }
> >> -
> >> -       /*
> >> -        * We don't allow disabling PPGTT for gen8+ as it's a requirement for
> >> -        * execlists, the sole mechanism available to submit work.
> >> -        */
> >> -       if (enable_ppgtt == 0 && !HAS_EXECLISTS(dev_priv))
> >> -               return 0;
> >> -
> >> -       if (enable_ppgtt == 1)
> >> -               return 1;
> >> -
> >> -       if (enable_ppgtt == 2 && has_full_ppgtt)
> >> -               return 2;
> >> -
> >> -       if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
> >> -               return 3;
> >> -
> >> -       /* Disable ppgtt on SNB if VT-d is on. */
> >> -       if (IS_GEN6(dev_priv) && intel_vtd_active()) {
> >> -               DRM_INFO("Disabling PPGTT because VT-d is on\n");
> >> -               return 0;
> >> -       }
> >> -
> >> -       if (has_full_48bit_ppgtt)
> >> -               return 3;
> >> -
> >> -       if (has_full_ppgtt)
> >> -               return 2;
> >> -
> >> -       return 1;
> >> -}
> >> -
> >>   static int ppgtt_bind_vma(struct i915_vma *vma,
> >>                            enum i915_cache_level cache_level,
> >>                            u32 unused)
> >> @@ -1647,7 +1598,7 @@ static struct i915_hw_ppgtt
> *gen8_ppgtt_create(struct drm_i915_private *i915)
> >>          ppgtt->vm.i915 = i915;
> >>          ppgtt->vm.dma = &i915->drm.pdev->dev;
> >>
> >> -       ppgtt->vm.total = USES_FULL_48BIT_PPGTT(i915) ?
> >> +       ppgtt->vm.total = HAS_FULL_48BIT_PPGTT(i915) ?
> >>                  1ULL << 48 :
> >>                  1ULL << 32;
> >>
> >> @@ -1782,19 +1733,6 @@ static inline void gen6_write_pde(const struct
> gen6_hw_ppgtt *ppgtt,
> >>                    ppgtt->pd_addr + pde);
> >>   }
> >>
> >> -static void gen8_ppgtt_enable(struct drm_i915_private *dev_priv)
> >> -{
> >> -       struct intel_engine_cs *engine;
> >> -       enum intel_engine_id id;
> >> -
> >> -       for_each_engine(engine, dev_priv, id) {
> >> -               u32 four_level = USES_FULL_48BIT_PPGTT(dev_priv) ?
> >> -                                GEN8_GFX_PPGTT_48B : 0;
> >> -               I915_WRITE(RING_MODE_GEN7(engine),
> >> -                          _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
> >> -       }
> >> -}
> >> -
> >>   static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv)
> >>   {
> >>          struct intel_engine_cs *engine;
> >> @@ -1834,7 +1772,8 @@ static void gen6_ppgtt_enable(struct
> drm_i915_private *dev_priv)
> >>          ecochk = I915_READ(GAM_ECOCHK);
> >>          I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
> ECOCHK_PPGTT_CACHE64B);
> >>
> >> -       I915_WRITE(GFX_MODE,
> _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
> >> +       if (HAS_PPGTT(dev_priv)) /* may be disabled for VT-d */
> >> +               I915_WRITE(GFX_MODE,
> _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
> >>   }
> >>
> >>   /* PPGTT support for Sandybdrige/Gen6 and later */
> >> @@ -2237,23 +2176,10 @@ int i915_ppgtt_init_hw(struct
> drm_i915_private *dev_priv)
> >>   {
> >>          gtt_write_workarounds(dev_priv);
> >>
> >> -       /* In the case of execlists, PPGTT is enabled by the context descriptor
> >> -        * and the PDPs are contained within the context itself.  We don't
> >> -        * need to do anything here. */
> >> -       if (HAS_LOGICAL_RING_CONTEXTS(dev_priv))
> >> -               return 0;
> >> -
> >> -       if (!USES_PPGTT(dev_priv))
> >> -               return 0;
> >> -
> >>          if (IS_GEN6(dev_priv))
> >>                  gen6_ppgtt_enable(dev_priv);
> >>          else if (IS_GEN7(dev_priv))
> >>                  gen7_ppgtt_enable(dev_priv);
> >> -       else if (INTEL_GEN(dev_priv) >= 8)
> >> -               gen8_ppgtt_enable(dev_priv);
> >> -       else
> >> -               MISSING_CASE(INTEL_GEN(dev_priv));
> >>
> >>          return 0;
> >>   }
> >> @@ -2952,7 +2878,7 @@ int i915_gem_init_ggtt(struct drm_i915_private
> *dev_priv)
> >>          /* And finally clear the reserved guard page */
> >>          ggtt->vm.clear_range(&ggtt->vm, ggtt->vm.total - PAGE_SIZE,
> PAGE_SIZE);
> >>
> >> -       if (USES_PPGTT(dev_priv) && !USES_FULL_PPGTT(dev_priv)) {
> >> +       if (INTEL_PPGTT(dev_priv) == INTEL_PPGTT_ALIASING) {
> >>                  ret = i915_gem_init_aliasing_ppgtt(dev_priv);
> >>                  if (ret)
> >>                          goto err;
> >> @@ -3275,7 +3201,7 @@ static void bdw_setup_private_ppat(struct
> intel_ppat *ppat)
> >>          ppat->match = bdw_private_pat_match;
> >>          ppat->clear_value = GEN8_PPAT_WB | GEN8_PPAT_LLCELLC |
> GEN8_PPAT_AGE(3);
> >>
> >> -       if (!USES_PPGTT(ppat->i915)) {
> >> +       if (!HAS_PPGTT(ppat->i915)) {
> >>                  /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
> >>                   * so RTL will always use the value corresponding to
> >>                   * pat_sel = 000".
> >> @@ -3402,7 +3328,7 @@ static int gen8_gmch_probe(struct i915_ggtt
> *ggtt)
> >>          ggtt->vm.cleanup = gen6_gmch_remove;
> >>          ggtt->vm.insert_page = gen8_ggtt_insert_page;
> >>          ggtt->vm.clear_range = nop_clear_range;
> >> -       if (!USES_FULL_PPGTT(dev_priv) ||
> intel_scanout_needs_vtd_wa(dev_priv))
> >> +       if (intel_scanout_needs_vtd_wa(dev_priv))
> >>                  ggtt->vm.clear_range = gen8_ggtt_clear_range;
> >>
> >>          ggtt->vm.insert_entries = gen8_ggtt_insert_entries;
> >> @@ -3609,7 +3535,7 @@ int i915_ggtt_init_hw(struct drm_i915_private
> *dev_priv)
> >>          /* Only VLV supports read-only GGTT mappings */
> >>          ggtt->vm.has_read_only = IS_VALLEYVIEW(dev_priv);
> >>
> >> -       if (!HAS_LLC(dev_priv) && !USES_PPGTT(dev_priv))
> >> +       if (!HAS_LLC(dev_priv) && !HAS_PPGTT(dev_priv))
> >>                  ggtt->vm.mm.color_adjust = i915_gtt_color_adjust;
> >>          mutex_unlock(&dev_priv->drm.struct_mutex);
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
> b/drivers/gpu/drm/i915/i915_gpu_error.c
> >> index 2835cacd0d08..3d5554f14dfd 100644
> >> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> >> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> >> @@ -474,7 +474,7 @@ static void error_print_engine(struct
> drm_i915_error_state_buf *m,
> >>                          err_printf(m, "  SYNC_2: 0x%08x\n",
> >>                                     ee->semaphore_mboxes[2]);
> >>          }
> >> -       if (USES_PPGTT(m->i915)) {
> >> +       if (HAS_PPGTT(m->i915)) {
> >>                  err_printf(m, "  GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
> >>
> >>                  if (INTEL_GEN(m->i915) >= 8) {
> >> @@ -1230,7 +1230,7 @@ static void
> error_record_engine_registers(struct i915_gpu_state *error,
> >>          ee->reset_count = i915_reset_engine_count(&dev_priv->gpu_error,
> >>                                                    engine);
> >>
> >> -       if (USES_PPGTT(dev_priv)) {
> >> +       if (HAS_PPGTT(dev_priv)) {
> >>                  int i;
> >>
> >>                  ee->vm_info.gfx_mode =
> I915_READ(RING_MODE_GEN7(engine));
> >> diff --git a/drivers/gpu/drm/i915/i915_params.c
> b/drivers/gpu/drm/i915/i915_params.c
> >> index 295e981e4a39..bd6bd8879cab 100644
> >> --- a/drivers/gpu/drm/i915/i915_params.c
> >> +++ b/drivers/gpu/drm/i915/i915_params.c
> >> @@ -82,10 +82,6 @@ i915_param_named_unsafe(enable_hangcheck,
> bool, 0644,
> >>          "WARNING: Disabling this can cause system wide hangs. "
> >>          "(default: true)");
> >>
> >> -i915_param_named_unsafe(enable_ppgtt, int, 0400,
> >> -       "Override PPGTT usage. "
> >> -       "(-1=auto [default], 0=disabled, 1=aliasing, 2=full, 3=full with
> extended address space)");
> >> -
> >>   i915_param_named_unsafe(enable_psr, int, 0600,
> >>          "Enable PSR "
> >>          "(0=disabled, 1=enabled) "
> >> diff --git a/drivers/gpu/drm/i915/i915_params.h
> b/drivers/gpu/drm/i915/i915_params.h
> >> index 6c4d4a21474b..7e56c516c815 100644
> >> --- a/drivers/gpu/drm/i915/i915_params.h
> >> +++ b/drivers/gpu/drm/i915/i915_params.h
> >> @@ -41,7 +41,6 @@ struct drm_printer;
> >>          param(int, vbt_sdvo_panel_type, -1) \
> >>          param(int, enable_dc, -1) \
> >>          param(int, enable_fbc, -1) \
> >> -       param(int, enable_ppgtt, -1) \
> >>          param(int, enable_psr, -1) \
> >>          param(int, disable_power_well, -1) \
> >>          param(int, enable_ips, 1) \
> >> diff --git a/drivers/gpu/drm/i915/i915_pci.c
> b/drivers/gpu/drm/i915/i915_pci.c
> >> index d6f7b9fe1d26..eeec902896b9 100644
> >> --- a/drivers/gpu/drm/i915/i915_pci.c
> >> +++ b/drivers/gpu/drm/i915/i915_pci.c
> >> @@ -252,7 +252,7 @@ static const struct intel_device_info
> intel_ironlake_m_info = {
> >>          .has_llc = 1, \
> >>          .has_rc6 = 1, \
> >>          .has_rc6p = 1, \
> >> -       .has_aliasing_ppgtt = 1, \
> >> +       .ppgtt = INTEL_PPGTT_ALIASING, \
> >>          GEN_DEFAULT_PIPEOFFSETS, \
> >>          GEN_DEFAULT_PAGE_SIZES, \
> >>          CURSOR_OFFSETS
> >> @@ -297,8 +297,7 @@ static const struct intel_device_info
> intel_sandybridge_m_gt2_info = {
> >>          .has_llc = 1, \
> >>          .has_rc6 = 1, \
> >>          .has_rc6p = 1, \
> >> -       .has_aliasing_ppgtt = 1, \
> >> -       .has_full_ppgtt = 1, \
> >> +       .ppgtt = INTEL_PPGTT_FULL, \
> >>          GEN_DEFAULT_PIPEOFFSETS, \
> >>          GEN_DEFAULT_PAGE_SIZES, \
> >>          IVB_CURSOR_OFFSETS
> >> @@ -351,8 +350,7 @@ static const struct intel_device_info
> intel_valleyview_info = {
> >>          .has_rc6 = 1,
> >>          .has_gmch_display = 1,
> >>          .has_hotplug = 1,
> >> -       .has_aliasing_ppgtt = 1,
> >> -       .has_full_ppgtt = 1,
> >> +       .ppgtt = INTEL_PPGTT_FULL,
> >>          .has_snoop = true,
> >>          .has_coherent_ggtt = false,
> >>          .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
> >> @@ -399,7 +397,7 @@ static const struct intel_device_info
> intel_haswell_gt3_info = {
> >>          .page_sizes = I915_GTT_PAGE_SIZE_4K | \
> >>                        I915_GTT_PAGE_SIZE_2M, \
> >>          .has_logical_ring_contexts = 1, \
> >> -       .has_full_48bit_ppgtt = 1, \
> >> +       .ppgtt = INTEL_PPGTT_FULL_4LVL, \
> >>          .has_64bit_reloc = 1, \
> >>          .has_reset_engine = 1
> >>
> >> @@ -443,8 +441,7 @@ static const struct intel_device_info
> intel_cherryview_info = {
> >>          .has_rc6 = 1,
> >>          .has_logical_ring_contexts = 1,
> >>          .has_gmch_display = 1,
> >> -       .has_aliasing_ppgtt = 1,
> >> -       .has_full_ppgtt = 1,
> >> +       .ppgtt = INTEL_PPGTT_FULL,
> >>          .has_reset_engine = 1,
> >>          .has_snoop = true,
> >>          .has_coherent_ggtt = false,
> >> @@ -518,9 +515,7 @@ static const struct intel_device_info
> intel_skylake_gt4_info = {
> >>          .has_logical_ring_contexts = 1, \
> >>          .has_logical_ring_preemption = 1, \
> >>          .has_guc = 1, \
> >> -       .has_aliasing_ppgtt = 1, \
> >> -       .has_full_ppgtt = 1, \
> >> -       .has_full_48bit_ppgtt = 1, \
> >> +       .ppgtt = INTEL_PPGTT_FULL_4LVL, \
> >>          .has_reset_engine = 1, \
> >>          .has_snoop = true, \
> >>          .has_coherent_ggtt = false, \
> >> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> >> index 0ef0c6448d53..a841d181efd3 100644
> >> --- a/drivers/gpu/drm/i915/intel_device_info.c
> >> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> >> @@ -26,6 +26,7 @@
> >>
> >>   #include "intel_device_info.h"
> >>   #include "i915_drv.h"
> >> +#include "i915_vgpu.h"
> >>
> >>   #define PLATFORM_NAME(x) [INTEL_##x] = #x
> >>   static const char * const platform_names[] = {
> >> @@ -851,6 +852,11 @@ void intel_device_info_runtime_init(struct
> intel_device_info *info)
> >>          else if (INTEL_GEN(dev_priv) >= 11)
> >>                  gen11_sseu_info_init(dev_priv);
> >>
> >> +       if (IS_GEN6(dev_priv) && intel_vtd_active()) {
> >> +               DRM_INFO("Disabling ppGTT for VT-d support\n");
> >> +               info->ppgtt = INTEL_PPGTT_NONE;
> >> +       }
> >> +
> >>          /* Initialize command stream timestamp frequency */
> >>          info->cs_timestamp_frequency_khz =
> read_timestamp_frequency(dev_priv);
> >>   }
> >> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> b/drivers/gpu/drm/i915/intel_device_info.h
> >> index 6eecd64734d5..6bab97687328 100644
> >> --- a/drivers/gpu/drm/i915/intel_device_info.h
> >> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> >> @@ -74,21 +74,25 @@ enum intel_platform {
> >>          INTEL_MAX_PLATFORMS
> >>   };
> >>
> >> +enum intel_ppgtt {
> >> +       INTEL_PPGTT_NONE = 0,
> >> +       INTEL_PPGTT_ALIASING,
> >> +       INTEL_PPGTT_FULL,
> >> +       INTEL_PPGTT_FULL_4LVL,
> >> +};
> >> +
> >>   #define DEV_INFO_FOR_EACH_FLAG(func) \
> >>          func(is_mobile); \
> >>          func(is_lp); \
> >>          func(is_alpha_support); \
> >>          /* Keep has_* in alphabetical order */ \
> >>          func(has_64bit_reloc); \
> >> -       func(has_aliasing_ppgtt); \
> >>          func(has_csr); \
> >>          func(has_ddi); \
> >>          func(has_dp_mst); \
> >>          func(has_reset_engine); \
> >>          func(has_fbc); \
> >>          func(has_fpga_dbg); \
> >> -       func(has_full_ppgtt); \
> >> -       func(has_full_48bit_ppgtt); \
> >>          func(has_gmch_display); \
> >>          func(has_guc); \
> >>          func(has_guc_ct); \
> >> @@ -154,6 +158,7 @@ struct intel_device_info {
> >>          enum intel_platform platform;
> >>          u32 platform_mask;
> >>
> >> +       enum intel_ppgtt ppgtt;
> >>          unsigned int page_sizes; /* page sizes supported by the HW */
> >>
> >>          u32 display_mmio_offset;
> >> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> b/drivers/gpu/drm/i915/intel_lrc.c
> >> index 4b28225320ff..3836a8a3761a 100644
> >> --- a/drivers/gpu/drm/i915/intel_lrc.c
> >> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> >> @@ -418,9 +418,8 @@ execlists_update_context_pdps(struct
> i915_hw_ppgtt *ppgtt, u32 *reg_state)
> >>
> >>   static u64 execlists_update_context(struct i915_request *rq)
> >>   {
> >> +       struct i915_hw_ppgtt *ppgtt = rq->gem_context->ppgtt;
> >>          struct intel_context *ce = rq->hw_context;
> >> -       struct i915_hw_ppgtt *ppgtt =
> >> -               rq->gem_context->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
> >>          u32 *reg_state = ce->lrc_reg_state;
> >>
> >>          reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail);
> >> @@ -1376,7 +1375,7 @@ execlists_context_pin(struct intel_engine_cs
> *engine,
> >>          struct intel_context *ce = to_intel_context(ctx, engine);
> >>
> >>          lockdep_assert_held(&ctx->i915->drm.struct_mutex);
> >> -       GEM_BUG_ON(!(ctx->ppgtt ?: ctx->i915->mm.aliasing_ppgtt));
> >> +       GEM_BUG_ON(!ctx->ppgtt);
> >>
> >>          if (likely(ce->pin_count++))
> >>                  return ce;
> >> @@ -2031,8 +2030,7 @@ static int gen8_emit_bb_start(struct
> i915_request *rq,
> >>           * it is unsafe in case of lite-restore (because the ctx is
> >>           * not idle). PML4 is allocated during ppgtt init so this is
> >>           * not needed in 48-bit.*/
> >> -       if (rq->gem_context->ppgtt &&
> >> -           (intel_engine_flag(rq->engine) & rq->gem_context->ppgtt-
> >pd_dirty_rings) &&
> >> +       if ((intel_engine_flag(rq->engine) & rq->gem_context->ppgtt-
> >pd_dirty_rings) &&
> >>              !i915_vm_is_48bit(&rq->gem_context->ppgtt->vm) &&
> >>              !intel_vgpu_active(rq->i915)) {
> >>                  ret = intel_logical_ring_emit_pdps(rq);
> >> @@ -2634,7 +2632,6 @@ static void execlists_init_reg_state(u32 *regs,
> >>                                       struct intel_ring *ring)
> >>   {
> >>          struct drm_i915_private *dev_priv = engine->i915;
> >> -       struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: dev_priv-
> >mm.aliasing_ppgtt;
> >>          u32 base = engine->mmio_base;
> >>          bool rcs = engine->class == RENDER_CLASS;
> >>
> >> @@ -2706,12 +2703,12 @@ static void execlists_init_reg_state(u32 *regs,
> >>          CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0),
> 0);
> >>          CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0),
> 0);
> >>
> >> -       if (i915_vm_is_48bit(&ppgtt->vm)) {
> >> +       if (i915_vm_is_48bit(&ctx->ppgtt->vm)) {
> >>                  /* 64b PPGTT (48bit canonical)
> >>                   * PDP0_DESCRIPTOR contains the base address to PML4 and
> >>                   * other PDP Descriptors are ignored.
> >>                   */
> >> -               ASSIGN_CTX_PML4(ppgtt, regs);
> >> +               ASSIGN_CTX_PML4(ctx->ppgtt, regs);
> >>          }
> >>
> >>          if (rcs) {
> >> diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c
> b/drivers/gpu/drm/i915/selftests/huge_pages.c
> >> index 8d03f64eabd7..09ea65a29d98 100644
> >> --- a/drivers/gpu/drm/i915/selftests/huge_pages.c
> >> +++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
> >> @@ -1436,7 +1436,7 @@ static int igt_ppgtt_pin_update(void *arg)
> >>           * huge-gtt-pages.
> >>           */
> >>
> >> -       if (!USES_FULL_48BIT_PPGTT(dev_priv)) {
> >> +       if (!HAS_FULL_48BIT_PPGTT(dev_priv)) {
> >>                  pr_info("48b PPGTT not supported, skipping\n");
> >>                  return 0;
> >>          }
> >> @@ -1687,10 +1687,9 @@ int
> i915_gem_huge_page_mock_selftests(void)
> >>                  SUBTEST(igt_mock_ppgtt_huge_fill),
> >>                  SUBTEST(igt_mock_ppgtt_64K),
> >>          };
> >> -       int saved_ppgtt = i915_modparams.enable_ppgtt;
> >>          struct drm_i915_private *dev_priv;
> >> -       struct pci_dev *pdev;
> >>          struct i915_hw_ppgtt *ppgtt;
> >> +       struct pci_dev *pdev;
> >>          int err;
> >>
> >>          dev_priv = mock_gem_device();
> >> @@ -1698,7 +1697,7 @@ int i915_gem_huge_page_mock_selftests(void)
> >>                  return -ENOMEM;
> >>
> >>          /* Pretend to be a device which supports the 48b PPGTT */
> >> -       i915_modparams.enable_ppgtt = 3;
> >> +       mkwrite_device_info(dev_priv)->ppgtt = INTEL_PPGTT_FULL_4LVL;
> >>
> >>          pdev = dev_priv->drm.pdev;
> >>          dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(39));
> >> @@ -1731,9 +1730,6 @@ int i915_gem_huge_page_mock_selftests(void)
> >>
> >>   out_unlock:
> >>          mutex_unlock(&dev_priv->drm.struct_mutex);
> >> -
> >> -       i915_modparams.enable_ppgtt = saved_ppgtt;
> >> -
> >>          drm_dev_put(&dev_priv->drm);
> >>
> >>          return err;
> >> @@ -1753,7 +1749,7 @@ int i915_gem_huge_page_live_selftests(struct
> drm_i915_private *dev_priv)
> >>          struct i915_gem_context *ctx;
> >>          int err;
> >>
> >> -       if (!USES_PPGTT(dev_priv)) {
> >> +       if (!HAS_PPGTT(dev_priv)) {
> >>                  pr_info("PPGTT not supported, skipping live-selftests\n");
> >>                  return 0;
> >>          }
> >> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> >> index 76df25aa90c9..913c0f83f86a 100644
> >> --- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> >> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> >> @@ -535,7 +535,6 @@ static int igt_ctx_exec(void *arg)
> >>          IGT_TIMEOUT(end_time);
> >>          LIST_HEAD(objects);
> >>          unsigned long ncontexts, ndwords, dw;
> >> -       bool first_shared_gtt = true;
> >>          int err = -ENODEV;
> >>
> >>          /*
> >> @@ -561,12 +560,7 @@ static int igt_ctx_exec(void *arg)
> >>                  struct i915_gem_context *ctx;
> >>                  unsigned int id;
> >>
> >> -               if (first_shared_gtt) {
> >> -                       ctx = __create_hw_context(i915, file->driver_priv);
> >> -                       first_shared_gtt = false;
> >> -               } else {
> >> -                       ctx = i915_gem_create_context(i915, file->driver_priv);
> >> -               }
> >> +               ctx = i915_gem_create_context(i915, file->driver_priv);
> >>                  if (IS_ERR(ctx)) {
> >>                          err = PTR_ERR(ctx);
> >>                          goto out_unlock;
> >> @@ -865,33 +859,6 @@ static int igt_switch_to_kernel_context(void
> *arg)
> >>          return err;
> >>   }
> >>
> >> -static int fake_aliasing_ppgtt_enable(struct drm_i915_private *i915)
> >> -{
> >> -       struct drm_i915_gem_object *obj;
> >> -       int err;
> >> -
> >> -       err = i915_gem_init_aliasing_ppgtt(i915);
> >> -       if (err)
> >> -               return err;
> >> -
> >> -       list_for_each_entry(obj, &i915->mm.bound_list, mm.link) {
> >> -               struct i915_vma *vma;
> >> -
> >> -               vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
> >> -               if (IS_ERR(vma))
> >> -                       continue;
> >> -
> >> -               vma->flags &= ~I915_VMA_LOCAL_BIND;
> >> -       }
> >> -
> >> -       return 0;
> >> -}
> >> -
> >> -static void fake_aliasing_ppgtt_disable(struct drm_i915_private *i915)
> >> -{
> >> -       i915_gem_fini_aliasing_ppgtt(i915);
> >> -}
> >> -
> >>   int i915_gem_context_mock_selftests(void)
> >>   {
> >>          static const struct i915_subtest tests[] = {
> >> @@ -918,31 +885,9 @@ int i915_gem_context_live_selftests(struct
> drm_i915_private *dev_priv)
> >>                  SUBTEST(igt_ctx_exec),
> >>                  SUBTEST(igt_ctx_readonly),
> >>          };
> >> -       bool fake_alias = false;
> >> -       int err;
> >>
> >>          if (i915_terminally_wedged(&dev_priv->gpu_error))
> >>                  return 0;
> >>
> >> -       /* Install a fake aliasing gtt for exercise */
> >> -       if (USES_PPGTT(dev_priv) && !dev_priv->mm.aliasing_ppgtt) {
> >> -               mutex_lock(&dev_priv->drm.struct_mutex);
> >> -               err = fake_aliasing_ppgtt_enable(dev_priv);
> >> -               mutex_unlock(&dev_priv->drm.struct_mutex);
> >> -               if (err)
> >> -                       return err;
> >> -
> >> -               GEM_BUG_ON(!dev_priv->mm.aliasing_ppgtt);
> >> -               fake_alias = true;
> >> -       }
> >> -
> >> -       err = i915_subtests(tests, dev_priv);
> >> -
> >> -       if (fake_alias) {
> >> -               mutex_lock(&dev_priv->drm.struct_mutex);
> >> -               fake_aliasing_ppgtt_disable(dev_priv);
> >> -               mutex_unlock(&dev_priv->drm.struct_mutex);
> >> -       }
> >> -
> >> -       return err;
> >> +       return i915_subtests(tests, dev_priv);
> >>   }
> >> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
> b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
> >> index 128ad1cf0647..4365979d8222 100644
> >> --- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
> >> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
> >> @@ -351,7 +351,7 @@ static int igt_evict_contexts(void *arg)
> >>           * where the GTT space of the request is separate from the GGTT
> >>           * allocation required to build the request.
> >>           */
> >> -       if (!USES_FULL_PPGTT(i915))
> >> +       if (!HAS_FULL_PPGTT(i915))
> >>                  return 0;
> >>
> >>          mutex_lock(&i915->drm.struct_mutex);
> >> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> >> index 8e2e269db97e..17b5aaaa7a50 100644
> >> --- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> >> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> >> @@ -153,7 +153,7 @@ static int igt_ppgtt_alloc(void *arg)
> >>
> >>          /* Allocate a ppggt and try to fill the entire range */
> >>
> >> -       if (!USES_PPGTT(dev_priv))
> >> +       if (!HAS_PPGTT(dev_priv))
> >>                  return 0;
> >>
> >>          ppgtt = __hw_ppgtt_create(dev_priv);
> >> @@ -1001,7 +1001,7 @@ static int exercise_ppgtt(struct
> drm_i915_private *dev_priv,
> >>          IGT_TIMEOUT(end_time);
> >>          int err;
> >>
> >> -       if (!USES_FULL_PPGTT(dev_priv))
> >> +       if (!HAS_FULL_PPGTT(dev_priv))
> >>                  return 0;
> >>
> >>          file = mock_file(dev_priv);
> >> --
> >> 2.19.0
> >>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v4] drm/i915: Remove i915.enable_ppgtt override
  2018-09-26  1:06     ` He, Min
@ 2018-09-26  8:02       ` Joonas Lahtinen
  2018-09-26 12:29         ` Zhi Wang
  2018-10-08  9:53         ` Zhenyu Wang
  0 siblings, 2 replies; 24+ messages in thread
From: Joonas Lahtinen @ 2018-09-26  8:02 UTC (permalink / raw)
  To: He, Min, Wang, Zhi A, intel-gfx, Chris Wilson, Zhenyu Wang; +Cc: Auld, Matthew

Quoting He, Min (2018-09-26 04:06:25)
> No. We changed to full 48bit ppgtt long time ago. :)

So would that mean the change is OK to do?

Acked-by from you, Zhi, would be good to have for documentation purposes
in that case :)

Regards, Joonas

> 
> > -----Original Message-----
> > From: Wang, Zhi A
> > Sent: Wednesday, September 26, 2018 2:01 AM
> > To: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>; Chris Wilson
> > <chris@chris-wilson.co.uk>; intel-gfx@lists.freedesktop.org; Zhenyu Wang
> > <zhenyuw@linux.intel.com>
> > Cc: Auld, Matthew <matthew.auld@intel.com>; He, Min <min.he@intel.com>
> > Subject: Re: [PATCH v4] drm/i915: Remove i915.enable_ppgtt override
> > 
> > Hi Min:
> > 
> > I remembered the IOTG guest kernel is using aliasing-ppgtt in the last
> > technical sharing (probably I didn't remember it correctly). Can you
> > confirm?
> > 
> > Also, thanks Joonas for the reminding. :)
> > 
> > thanks,
> > Zhi.
> > 
> > On 09/25/18 09:22, Joonas Lahtinen wrote:
> > > + Zhi and Zhenyu
> > >
> > > For me the patch looks ok.
> > >
> > > It refuses to load GVT on systems where 48-bit is not supported, for not
> > > worsening the system security when virtualization is enabled (as anybody
> > > would probably expect virtualization to improve that). Please see code.
> > >
> > > Do we have such systems in the wild? Should we instruct the user to
> > > updating the hypervisor to specific kernel version when they hit the
> > > error?
> > >
> > > Regards, Joonas
> > >
> > > Quoting Chris Wilson (2018-09-25 14:48:20)
> > >> Now that we are confident in providing full-ppgtt where supported,
> > >> remove the ability to override the context isolation.
> > >>
> > >> v2: Remove faked aliasing-ppgtt for testing as it no longer is accepted.
> > >> v3: s/USES/HAS/ to match usage and reject attempts to load the module
> > on
> > >> old GVT-g setups that do not provide support for full-ppgtt.
> > >>
> > >> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > >> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > >> Cc: Matthew Auld <matthew.auld@intel.com>
> > >> ---
> > >>   drivers/gpu/drm/i915/i915_drv.c               | 22 +++--
> > >>   drivers/gpu/drm/i915/i915_drv.h               | 14 +--
> > >>   drivers/gpu/drm/i915/i915_gem_context.c       |  2 +-
> > >>   drivers/gpu/drm/i915/i915_gem_gtt.c           | 88 ++-----------------
> > >>   drivers/gpu/drm/i915/i915_gpu_error.c         |  4 +-
> > >>   drivers/gpu/drm/i915/i915_params.c            |  4 -
> > >>   drivers/gpu/drm/i915/i915_params.h            |  1 -
> > >>   drivers/gpu/drm/i915/i915_pci.c               | 17 ++--
> > >>   drivers/gpu/drm/i915/intel_device_info.c      |  6 ++
> > >>   drivers/gpu/drm/i915/intel_device_info.h      | 11 ++-
> > >>   drivers/gpu/drm/i915/intel_lrc.c              | 13 ++-
> > >>   drivers/gpu/drm/i915/selftests/huge_pages.c   | 12 +--
> > >>   .../gpu/drm/i915/selftests/i915_gem_context.c | 59 +------------
> > >>   .../gpu/drm/i915/selftests/i915_gem_evict.c   |  2 +-
> > >>   drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |  4 +-
> > >>   15 files changed, 62 insertions(+), 197 deletions(-)
> > >>
> > >> diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > b/drivers/gpu/drm/i915/i915_drv.c
> > >> index 44e2c0f5ec50..3efbbc71c3b4 100644
> > >> --- a/drivers/gpu/drm/i915/i915_drv.c
> > >> +++ b/drivers/gpu/drm/i915/i915_drv.c
> > >> @@ -345,7 +345,7 @@ static int i915_getparam_ioctl(struct drm_device
> > *dev, void *data,
> > >>                  value = HAS_WT(dev_priv);
> > >>                  break;
> > >>          case I915_PARAM_HAS_ALIASING_PPGTT:
> > >> -               value = USES_PPGTT(dev_priv);
> > >> +               value = INTEL_PPGTT(dev_priv);
> > >>                  break;
> > >>          case I915_PARAM_HAS_SEMAPHORES:
> > >>                  value = HAS_LEGACY_SEMAPHORES(dev_priv);
> > >> @@ -1049,17 +1049,6 @@ static void i915_driver_cleanup_mmio(struct
> > drm_i915_private *dev_priv)
> > >>
> > >>   static void intel_sanitize_options(struct drm_i915_private *dev_priv)
> > >>   {
> > >> -       /*
> > >> -        * i915.enable_ppgtt is read-only, so do an early pass to validate the
> > >> -        * user's requested state against the hardware/driver capabilities.
> > We
> > >> -        * do this now so that we can print out any log messages once rather
> > >> -        * than every time we check intel_enable_ppgtt().
> > >> -        */
> > >> -       i915_modparams.enable_ppgtt =
> > >> -               intel_sanitize_enable_ppgtt(dev_priv,
> > >> -                                           i915_modparams.enable_ppgtt);
> > >> -       DRM_DEBUG_DRIVER("ppgtt mode: %i\n",
> > i915_modparams.enable_ppgtt);
> > >> -
> > >>          intel_gvt_sanitize_options(dev_priv);
> > >>   }
> > >>
> > >> @@ -1374,6 +1363,15 @@ static int i915_driver_init_hw(struct
> > drm_i915_private *dev_priv)
> > >>
> > >>          intel_device_info_runtime_init(mkwrite_device_info(dev_priv));
> > >>
> > >> +       if (HAS_PPGTT(dev_priv)) {
> > >> +               if (intel_vgpu_active(dev_priv) &&
> > >> +                   !intel_vgpu_has_full_48bit_ppgtt(dev_priv)) {
> > >> +                       i915_report_error(dev_priv,
> > >> +                                         "incompatible vGPU found, support for isolated
> > ppGTT required\n");
> > >> +                       return -ENXIO;
> > >> +               }
> > >> +       }
> > >> +
> > >>          intel_sanitize_options(dev_priv);
> > >>
> > >>          i915_perf_init(dev_priv);
> > >> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > >> index 8624b4bdc242..f28b3c2a3cd2 100644
> > >> --- a/drivers/gpu/drm/i915/i915_drv.h
> > >> +++ b/drivers/gpu/drm/i915/i915_drv.h
> > >> @@ -2593,9 +2593,14 @@ intel_info(const struct drm_i915_private
> > *dev_priv)
> > >>
> > >>   #define HAS_EXECLISTS(dev_priv)
> > HAS_LOGICAL_RING_CONTEXTS(dev_priv)
> > >>
> > >> -#define USES_PPGTT(dev_priv)           (i915_modparams.enable_ppgtt)
> > >> -#define USES_FULL_PPGTT(dev_priv)
> > (i915_modparams.enable_ppgtt >= 2)
> > >> -#define USES_FULL_48BIT_PPGTT(dev_priv)
> > (i915_modparams.enable_ppgtt == 3)
> > >> +#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt)
> > >> +#define HAS_PPGTT(dev_priv) \
> > >> +       (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
> > >> +#define HAS_FULL_PPGTT(dev_priv) \
> > >> +       (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
> > >> +#define HAS_FULL_48BIT_PPGTT(dev_priv) \
> > >> +       (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL_4LVL)
> > >> +
> > >>   #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
> > >>          GEM_BUG_ON((sizes) == 0); \
> > >>          ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
> > >> @@ -2743,9 +2748,6 @@ intel_ggtt_update_needs_vtd_wa(struct
> > drm_i915_private *dev_priv)
> > >>          return IS_BROXTON(dev_priv) && intel_vtd_active();
> > >>   }
> > >>
> > >> -int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
> > >> -                               int enable_ppgtt);
> > >> -
> > >>   /* i915_drv.c */
> > >>   void __printf(3, 4)
> > >>   __i915_printk(struct drm_i915_private *dev_priv, const char *level,
> > >> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
> > b/drivers/gpu/drm/i915/i915_gem_context.c
> > >> index f772593b99ab..15c92f75b1b8 100644
> > >> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> > >> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> > >> @@ -414,7 +414,7 @@ i915_gem_create_context(struct
> > drm_i915_private *dev_priv,
> > >>          if (IS_ERR(ctx))
> > >>                  return ctx;
> > >>
> > >> -       if (USES_FULL_PPGTT(dev_priv)) {
> > >> +       if (HAS_FULL_PPGTT(dev_priv)) {
> > >>                  struct i915_hw_ppgtt *ppgtt;
> > >>
> > >>                  ppgtt = i915_ppgtt_create(dev_priv, file_priv);
> > >> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > >> index f6c7ab413081..c9363504949f 100644
> > >> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > >> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > >> @@ -133,55 +133,6 @@ static inline void i915_ggtt_invalidate(struct
> > drm_i915_private *i915)
> > >>          i915->ggtt.invalidate(i915);
> > >>   }
> > >>
> > >> -int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
> > >> -                               int enable_ppgtt)
> > >> -{
> > >> -       bool has_full_ppgtt;
> > >> -       bool has_full_48bit_ppgtt;
> > >> -
> > >> -       if (!dev_priv->info.has_aliasing_ppgtt)
> > >> -               return 0;
> > >> -
> > >> -       has_full_ppgtt = dev_priv->info.has_full_ppgtt;
> > >> -       has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt;
> > >> -
> > >> -       if (intel_vgpu_active(dev_priv)) {
> > >> -               /* GVT-g has no support for 32bit ppgtt */
> > >> -               has_full_ppgtt = false;
> > >> -               has_full_48bit_ppgtt =
> > intel_vgpu_has_full_48bit_ppgtt(dev_priv);
> > >> -       }
> > >> -
> > >> -       /*
> > >> -        * We don't allow disabling PPGTT for gen8+ as it's a requirement for
> > >> -        * execlists, the sole mechanism available to submit work.
> > >> -        */
> > >> -       if (enable_ppgtt == 0 && !HAS_EXECLISTS(dev_priv))
> > >> -               return 0;
> > >> -
> > >> -       if (enable_ppgtt == 1)
> > >> -               return 1;
> > >> -
> > >> -       if (enable_ppgtt == 2 && has_full_ppgtt)
> > >> -               return 2;
> > >> -
> > >> -       if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
> > >> -               return 3;
> > >> -
> > >> -       /* Disable ppgtt on SNB if VT-d is on. */
> > >> -       if (IS_GEN6(dev_priv) && intel_vtd_active()) {
> > >> -               DRM_INFO("Disabling PPGTT because VT-d is on\n");
> > >> -               return 0;
> > >> -       }
> > >> -
> > >> -       if (has_full_48bit_ppgtt)
> > >> -               return 3;
> > >> -
> > >> -       if (has_full_ppgtt)
> > >> -               return 2;
> > >> -
> > >> -       return 1;
> > >> -}
> > >> -
> > >>   static int ppgtt_bind_vma(struct i915_vma *vma,
> > >>                            enum i915_cache_level cache_level,
> > >>                            u32 unused)
> > >> @@ -1647,7 +1598,7 @@ static struct i915_hw_ppgtt
> > *gen8_ppgtt_create(struct drm_i915_private *i915)
> > >>          ppgtt->vm.i915 = i915;
> > >>          ppgtt->vm.dma = &i915->drm.pdev->dev;
> > >>
> > >> -       ppgtt->vm.total = USES_FULL_48BIT_PPGTT(i915) ?
> > >> +       ppgtt->vm.total = HAS_FULL_48BIT_PPGTT(i915) ?
> > >>                  1ULL << 48 :
> > >>                  1ULL << 32;
> > >>
> > >> @@ -1782,19 +1733,6 @@ static inline void gen6_write_pde(const struct
> > gen6_hw_ppgtt *ppgtt,
> > >>                    ppgtt->pd_addr + pde);
> > >>   }
> > >>
> > >> -static void gen8_ppgtt_enable(struct drm_i915_private *dev_priv)
> > >> -{
> > >> -       struct intel_engine_cs *engine;
> > >> -       enum intel_engine_id id;
> > >> -
> > >> -       for_each_engine(engine, dev_priv, id) {
> > >> -               u32 four_level = USES_FULL_48BIT_PPGTT(dev_priv) ?
> > >> -                                GEN8_GFX_PPGTT_48B : 0;
> > >> -               I915_WRITE(RING_MODE_GEN7(engine),
> > >> -                          _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
> > >> -       }
> > >> -}
> > >> -
> > >>   static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv)
> > >>   {
> > >>          struct intel_engine_cs *engine;
> > >> @@ -1834,7 +1772,8 @@ static void gen6_ppgtt_enable(struct
> > drm_i915_private *dev_priv)
> > >>          ecochk = I915_READ(GAM_ECOCHK);
> > >>          I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
> > ECOCHK_PPGTT_CACHE64B);
> > >>
> > >> -       I915_WRITE(GFX_MODE,
> > _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
> > >> +       if (HAS_PPGTT(dev_priv)) /* may be disabled for VT-d */
> > >> +               I915_WRITE(GFX_MODE,
> > _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
> > >>   }
> > >>
> > >>   /* PPGTT support for Sandybdrige/Gen6 and later */
> > >> @@ -2237,23 +2176,10 @@ int i915_ppgtt_init_hw(struct
> > drm_i915_private *dev_priv)
> > >>   {
> > >>          gtt_write_workarounds(dev_priv);
> > >>
> > >> -       /* In the case of execlists, PPGTT is enabled by the context descriptor
> > >> -        * and the PDPs are contained within the context itself.  We don't
> > >> -        * need to do anything here. */
> > >> -       if (HAS_LOGICAL_RING_CONTEXTS(dev_priv))
> > >> -               return 0;
> > >> -
> > >> -       if (!USES_PPGTT(dev_priv))
> > >> -               return 0;
> > >> -
> > >>          if (IS_GEN6(dev_priv))
> > >>                  gen6_ppgtt_enable(dev_priv);
> > >>          else if (IS_GEN7(dev_priv))
> > >>                  gen7_ppgtt_enable(dev_priv);
> > >> -       else if (INTEL_GEN(dev_priv) >= 8)
> > >> -               gen8_ppgtt_enable(dev_priv);
> > >> -       else
> > >> -               MISSING_CASE(INTEL_GEN(dev_priv));
> > >>
> > >>          return 0;
> > >>   }
> > >> @@ -2952,7 +2878,7 @@ int i915_gem_init_ggtt(struct drm_i915_private
> > *dev_priv)
> > >>          /* And finally clear the reserved guard page */
> > >>          ggtt->vm.clear_range(&ggtt->vm, ggtt->vm.total - PAGE_SIZE,
> > PAGE_SIZE);
> > >>
> > >> -       if (USES_PPGTT(dev_priv) && !USES_FULL_PPGTT(dev_priv)) {
> > >> +       if (INTEL_PPGTT(dev_priv) == INTEL_PPGTT_ALIASING) {
> > >>                  ret = i915_gem_init_aliasing_ppgtt(dev_priv);
> > >>                  if (ret)
> > >>                          goto err;
> > >> @@ -3275,7 +3201,7 @@ static void bdw_setup_private_ppat(struct
> > intel_ppat *ppat)
> > >>          ppat->match = bdw_private_pat_match;
> > >>          ppat->clear_value = GEN8_PPAT_WB | GEN8_PPAT_LLCELLC |
> > GEN8_PPAT_AGE(3);
> > >>
> > >> -       if (!USES_PPGTT(ppat->i915)) {
> > >> +       if (!HAS_PPGTT(ppat->i915)) {
> > >>                  /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
> > >>                   * so RTL will always use the value corresponding to
> > >>                   * pat_sel = 000".
> > >> @@ -3402,7 +3328,7 @@ static int gen8_gmch_probe(struct i915_ggtt
> > *ggtt)
> > >>          ggtt->vm.cleanup = gen6_gmch_remove;
> > >>          ggtt->vm.insert_page = gen8_ggtt_insert_page;
> > >>          ggtt->vm.clear_range = nop_clear_range;
> > >> -       if (!USES_FULL_PPGTT(dev_priv) ||
> > intel_scanout_needs_vtd_wa(dev_priv))
> > >> +       if (intel_scanout_needs_vtd_wa(dev_priv))
> > >>                  ggtt->vm.clear_range = gen8_ggtt_clear_range;
> > >>
> > >>          ggtt->vm.insert_entries = gen8_ggtt_insert_entries;
> > >> @@ -3609,7 +3535,7 @@ int i915_ggtt_init_hw(struct drm_i915_private
> > *dev_priv)
> > >>          /* Only VLV supports read-only GGTT mappings */
> > >>          ggtt->vm.has_read_only = IS_VALLEYVIEW(dev_priv);
> > >>
> > >> -       if (!HAS_LLC(dev_priv) && !USES_PPGTT(dev_priv))
> > >> +       if (!HAS_LLC(dev_priv) && !HAS_PPGTT(dev_priv))
> > >>                  ggtt->vm.mm.color_adjust = i915_gtt_color_adjust;
> > >>          mutex_unlock(&dev_priv->drm.struct_mutex);
> > >>
> > >> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
> > b/drivers/gpu/drm/i915/i915_gpu_error.c
> > >> index 2835cacd0d08..3d5554f14dfd 100644
> > >> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> > >> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> > >> @@ -474,7 +474,7 @@ static void error_print_engine(struct
> > drm_i915_error_state_buf *m,
> > >>                          err_printf(m, "  SYNC_2: 0x%08x\n",
> > >>                                     ee->semaphore_mboxes[2]);
> > >>          }
> > >> -       if (USES_PPGTT(m->i915)) {
> > >> +       if (HAS_PPGTT(m->i915)) {
> > >>                  err_printf(m, "  GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
> > >>
> > >>                  if (INTEL_GEN(m->i915) >= 8) {
> > >> @@ -1230,7 +1230,7 @@ static void
> > error_record_engine_registers(struct i915_gpu_state *error,
> > >>          ee->reset_count = i915_reset_engine_count(&dev_priv->gpu_error,
> > >>                                                    engine);
> > >>
> > >> -       if (USES_PPGTT(dev_priv)) {
> > >> +       if (HAS_PPGTT(dev_priv)) {
> > >>                  int i;
> > >>
> > >>                  ee->vm_info.gfx_mode =
> > I915_READ(RING_MODE_GEN7(engine));
> > >> diff --git a/drivers/gpu/drm/i915/i915_params.c
> > b/drivers/gpu/drm/i915/i915_params.c
> > >> index 295e981e4a39..bd6bd8879cab 100644
> > >> --- a/drivers/gpu/drm/i915/i915_params.c
> > >> +++ b/drivers/gpu/drm/i915/i915_params.c
> > >> @@ -82,10 +82,6 @@ i915_param_named_unsafe(enable_hangcheck,
> > bool, 0644,
> > >>          "WARNING: Disabling this can cause system wide hangs. "
> > >>          "(default: true)");
> > >>
> > >> -i915_param_named_unsafe(enable_ppgtt, int, 0400,
> > >> -       "Override PPGTT usage. "
> > >> -       "(-1=auto [default], 0=disabled, 1=aliasing, 2=full, 3=full with
> > extended address space)");
> > >> -
> > >>   i915_param_named_unsafe(enable_psr, int, 0600,
> > >>          "Enable PSR "
> > >>          "(0=disabled, 1=enabled) "
> > >> diff --git a/drivers/gpu/drm/i915/i915_params.h
> > b/drivers/gpu/drm/i915/i915_params.h
> > >> index 6c4d4a21474b..7e56c516c815 100644
> > >> --- a/drivers/gpu/drm/i915/i915_params.h
> > >> +++ b/drivers/gpu/drm/i915/i915_params.h
> > >> @@ -41,7 +41,6 @@ struct drm_printer;
> > >>          param(int, vbt_sdvo_panel_type, -1) \
> > >>          param(int, enable_dc, -1) \
> > >>          param(int, enable_fbc, -1) \
> > >> -       param(int, enable_ppgtt, -1) \
> > >>          param(int, enable_psr, -1) \
> > >>          param(int, disable_power_well, -1) \
> > >>          param(int, enable_ips, 1) \
> > >> diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > b/drivers/gpu/drm/i915/i915_pci.c
> > >> index d6f7b9fe1d26..eeec902896b9 100644
> > >> --- a/drivers/gpu/drm/i915/i915_pci.c
> > >> +++ b/drivers/gpu/drm/i915/i915_pci.c
> > >> @@ -252,7 +252,7 @@ static const struct intel_device_info
> > intel_ironlake_m_info = {
> > >>          .has_llc = 1, \
> > >>          .has_rc6 = 1, \
> > >>          .has_rc6p = 1, \
> > >> -       .has_aliasing_ppgtt = 1, \
> > >> +       .ppgtt = INTEL_PPGTT_ALIASING, \
> > >>          GEN_DEFAULT_PIPEOFFSETS, \
> > >>          GEN_DEFAULT_PAGE_SIZES, \
> > >>          CURSOR_OFFSETS
> > >> @@ -297,8 +297,7 @@ static const struct intel_device_info
> > intel_sandybridge_m_gt2_info = {
> > >>          .has_llc = 1, \
> > >>          .has_rc6 = 1, \
> > >>          .has_rc6p = 1, \
> > >> -       .has_aliasing_ppgtt = 1, \
> > >> -       .has_full_ppgtt = 1, \
> > >> +       .ppgtt = INTEL_PPGTT_FULL, \
> > >>          GEN_DEFAULT_PIPEOFFSETS, \
> > >>          GEN_DEFAULT_PAGE_SIZES, \
> > >>          IVB_CURSOR_OFFSETS
> > >> @@ -351,8 +350,7 @@ static const struct intel_device_info
> > intel_valleyview_info = {
> > >>          .has_rc6 = 1,
> > >>          .has_gmch_display = 1,
> > >>          .has_hotplug = 1,
> > >> -       .has_aliasing_ppgtt = 1,
> > >> -       .has_full_ppgtt = 1,
> > >> +       .ppgtt = INTEL_PPGTT_FULL,
> > >>          .has_snoop = true,
> > >>          .has_coherent_ggtt = false,
> > >>          .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
> > >> @@ -399,7 +397,7 @@ static const struct intel_device_info
> > intel_haswell_gt3_info = {
> > >>          .page_sizes = I915_GTT_PAGE_SIZE_4K | \
> > >>                        I915_GTT_PAGE_SIZE_2M, \
> > >>          .has_logical_ring_contexts = 1, \
> > >> -       .has_full_48bit_ppgtt = 1, \
> > >> +       .ppgtt = INTEL_PPGTT_FULL_4LVL, \
> > >>          .has_64bit_reloc = 1, \
> > >>          .has_reset_engine = 1
> > >>
> > >> @@ -443,8 +441,7 @@ static const struct intel_device_info
> > intel_cherryview_info = {
> > >>          .has_rc6 = 1,
> > >>          .has_logical_ring_contexts = 1,
> > >>          .has_gmch_display = 1,
> > >> -       .has_aliasing_ppgtt = 1,
> > >> -       .has_full_ppgtt = 1,
> > >> +       .ppgtt = INTEL_PPGTT_FULL,
> > >>          .has_reset_engine = 1,
> > >>          .has_snoop = true,
> > >>          .has_coherent_ggtt = false,
> > >> @@ -518,9 +515,7 @@ static const struct intel_device_info
> > intel_skylake_gt4_info = {
> > >>          .has_logical_ring_contexts = 1, \
> > >>          .has_logical_ring_preemption = 1, \
> > >>          .has_guc = 1, \
> > >> -       .has_aliasing_ppgtt = 1, \
> > >> -       .has_full_ppgtt = 1, \
> > >> -       .has_full_48bit_ppgtt = 1, \
> > >> +       .ppgtt = INTEL_PPGTT_FULL_4LVL, \
> > >>          .has_reset_engine = 1, \
> > >>          .has_snoop = true, \
> > >>          .has_coherent_ggtt = false, \
> > >> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> > b/drivers/gpu/drm/i915/intel_device_info.c
> > >> index 0ef0c6448d53..a841d181efd3 100644
> > >> --- a/drivers/gpu/drm/i915/intel_device_info.c
> > >> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > >> @@ -26,6 +26,7 @@
> > >>
> > >>   #include "intel_device_info.h"
> > >>   #include "i915_drv.h"
> > >> +#include "i915_vgpu.h"
> > >>
> > >>   #define PLATFORM_NAME(x) [INTEL_##x] = #x
> > >>   static const char * const platform_names[] = {
> > >> @@ -851,6 +852,11 @@ void intel_device_info_runtime_init(struct
> > intel_device_info *info)
> > >>          else if (INTEL_GEN(dev_priv) >= 11)
> > >>                  gen11_sseu_info_init(dev_priv);
> > >>
> > >> +       if (IS_GEN6(dev_priv) && intel_vtd_active()) {
> > >> +               DRM_INFO("Disabling ppGTT for VT-d support\n");
> > >> +               info->ppgtt = INTEL_PPGTT_NONE;
> > >> +       }
> > >> +
> > >>          /* Initialize command stream timestamp frequency */
> > >>          info->cs_timestamp_frequency_khz =
> > read_timestamp_frequency(dev_priv);
> > >>   }
> > >> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> > b/drivers/gpu/drm/i915/intel_device_info.h
> > >> index 6eecd64734d5..6bab97687328 100644
> > >> --- a/drivers/gpu/drm/i915/intel_device_info.h
> > >> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > >> @@ -74,21 +74,25 @@ enum intel_platform {
> > >>          INTEL_MAX_PLATFORMS
> > >>   };
> > >>
> > >> +enum intel_ppgtt {
> > >> +       INTEL_PPGTT_NONE = 0,
> > >> +       INTEL_PPGTT_ALIASING,
> > >> +       INTEL_PPGTT_FULL,
> > >> +       INTEL_PPGTT_FULL_4LVL,
> > >> +};
> > >> +
> > >>   #define DEV_INFO_FOR_EACH_FLAG(func) \
> > >>          func(is_mobile); \
> > >>          func(is_lp); \
> > >>          func(is_alpha_support); \
> > >>          /* Keep has_* in alphabetical order */ \
> > >>          func(has_64bit_reloc); \
> > >> -       func(has_aliasing_ppgtt); \
> > >>          func(has_csr); \
> > >>          func(has_ddi); \
> > >>          func(has_dp_mst); \
> > >>          func(has_reset_engine); \
> > >>          func(has_fbc); \
> > >>          func(has_fpga_dbg); \
> > >> -       func(has_full_ppgtt); \
> > >> -       func(has_full_48bit_ppgtt); \
> > >>          func(has_gmch_display); \
> > >>          func(has_guc); \
> > >>          func(has_guc_ct); \
> > >> @@ -154,6 +158,7 @@ struct intel_device_info {
> > >>          enum intel_platform platform;
> > >>          u32 platform_mask;
> > >>
> > >> +       enum intel_ppgtt ppgtt;
> > >>          unsigned int page_sizes; /* page sizes supported by the HW */
> > >>
> > >>          u32 display_mmio_offset;
> > >> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> > b/drivers/gpu/drm/i915/intel_lrc.c
> > >> index 4b28225320ff..3836a8a3761a 100644
> > >> --- a/drivers/gpu/drm/i915/intel_lrc.c
> > >> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> > >> @@ -418,9 +418,8 @@ execlists_update_context_pdps(struct
> > i915_hw_ppgtt *ppgtt, u32 *reg_state)
> > >>
> > >>   static u64 execlists_update_context(struct i915_request *rq)
> > >>   {
> > >> +       struct i915_hw_ppgtt *ppgtt = rq->gem_context->ppgtt;
> > >>          struct intel_context *ce = rq->hw_context;
> > >> -       struct i915_hw_ppgtt *ppgtt =
> > >> -               rq->gem_context->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
> > >>          u32 *reg_state = ce->lrc_reg_state;
> > >>
> > >>          reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail);
> > >> @@ -1376,7 +1375,7 @@ execlists_context_pin(struct intel_engine_cs
> > *engine,
> > >>          struct intel_context *ce = to_intel_context(ctx, engine);
> > >>
> > >>          lockdep_assert_held(&ctx->i915->drm.struct_mutex);
> > >> -       GEM_BUG_ON(!(ctx->ppgtt ?: ctx->i915->mm.aliasing_ppgtt));
> > >> +       GEM_BUG_ON(!ctx->ppgtt);
> > >>
> > >>          if (likely(ce->pin_count++))
> > >>                  return ce;
> > >> @@ -2031,8 +2030,7 @@ static int gen8_emit_bb_start(struct
> > i915_request *rq,
> > >>           * it is unsafe in case of lite-restore (because the ctx is
> > >>           * not idle). PML4 is allocated during ppgtt init so this is
> > >>           * not needed in 48-bit.*/
> > >> -       if (rq->gem_context->ppgtt &&
> > >> -           (intel_engine_flag(rq->engine) & rq->gem_context->ppgtt-
> > >pd_dirty_rings) &&
> > >> +       if ((intel_engine_flag(rq->engine) & rq->gem_context->ppgtt-
> > >pd_dirty_rings) &&
> > >>              !i915_vm_is_48bit(&rq->gem_context->ppgtt->vm) &&
> > >>              !intel_vgpu_active(rq->i915)) {
> > >>                  ret = intel_logical_ring_emit_pdps(rq);
> > >> @@ -2634,7 +2632,6 @@ static void execlists_init_reg_state(u32 *regs,
> > >>                                       struct intel_ring *ring)
> > >>   {
> > >>          struct drm_i915_private *dev_priv = engine->i915;
> > >> -       struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: dev_priv-
> > >mm.aliasing_ppgtt;
> > >>          u32 base = engine->mmio_base;
> > >>          bool rcs = engine->class == RENDER_CLASS;
> > >>
> > >> @@ -2706,12 +2703,12 @@ static void execlists_init_reg_state(u32 *regs,
> > >>          CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0),
> > 0);
> > >>          CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0),
> > 0);
> > >>
> > >> -       if (i915_vm_is_48bit(&ppgtt->vm)) {
> > >> +       if (i915_vm_is_48bit(&ctx->ppgtt->vm)) {
> > >>                  /* 64b PPGTT (48bit canonical)
> > >>                   * PDP0_DESCRIPTOR contains the base address to PML4 and
> > >>                   * other PDP Descriptors are ignored.
> > >>                   */
> > >> -               ASSIGN_CTX_PML4(ppgtt, regs);
> > >> +               ASSIGN_CTX_PML4(ctx->ppgtt, regs);
> > >>          }
> > >>
> > >>          if (rcs) {
> > >> diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c
> > b/drivers/gpu/drm/i915/selftests/huge_pages.c
> > >> index 8d03f64eabd7..09ea65a29d98 100644
> > >> --- a/drivers/gpu/drm/i915/selftests/huge_pages.c
> > >> +++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
> > >> @@ -1436,7 +1436,7 @@ static int igt_ppgtt_pin_update(void *arg)
> > >>           * huge-gtt-pages.
> > >>           */
> > >>
> > >> -       if (!USES_FULL_48BIT_PPGTT(dev_priv)) {
> > >> +       if (!HAS_FULL_48BIT_PPGTT(dev_priv)) {
> > >>                  pr_info("48b PPGTT not supported, skipping\n");
> > >>                  return 0;
> > >>          }
> > >> @@ -1687,10 +1687,9 @@ int
> > i915_gem_huge_page_mock_selftests(void)
> > >>                  SUBTEST(igt_mock_ppgtt_huge_fill),
> > >>                  SUBTEST(igt_mock_ppgtt_64K),
> > >>          };
> > >> -       int saved_ppgtt = i915_modparams.enable_ppgtt;
> > >>          struct drm_i915_private *dev_priv;
> > >> -       struct pci_dev *pdev;
> > >>          struct i915_hw_ppgtt *ppgtt;
> > >> +       struct pci_dev *pdev;
> > >>          int err;
> > >>
> > >>          dev_priv = mock_gem_device();
> > >> @@ -1698,7 +1697,7 @@ int i915_gem_huge_page_mock_selftests(void)
> > >>                  return -ENOMEM;
> > >>
> > >>          /* Pretend to be a device which supports the 48b PPGTT */
> > >> -       i915_modparams.enable_ppgtt = 3;
> > >> +       mkwrite_device_info(dev_priv)->ppgtt = INTEL_PPGTT_FULL_4LVL;
> > >>
> > >>          pdev = dev_priv->drm.pdev;
> > >>          dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(39));
> > >> @@ -1731,9 +1730,6 @@ int i915_gem_huge_page_mock_selftests(void)
> > >>
> > >>   out_unlock:
> > >>          mutex_unlock(&dev_priv->drm.struct_mutex);
> > >> -
> > >> -       i915_modparams.enable_ppgtt = saved_ppgtt;
> > >> -
> > >>          drm_dev_put(&dev_priv->drm);
> > >>
> > >>          return err;
> > >> @@ -1753,7 +1749,7 @@ int i915_gem_huge_page_live_selftests(struct
> > drm_i915_private *dev_priv)
> > >>          struct i915_gem_context *ctx;
> > >>          int err;
> > >>
> > >> -       if (!USES_PPGTT(dev_priv)) {
> > >> +       if (!HAS_PPGTT(dev_priv)) {
> > >>                  pr_info("PPGTT not supported, skipping live-selftests\n");
> > >>                  return 0;
> > >>          }
> > >> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> > b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> > >> index 76df25aa90c9..913c0f83f86a 100644
> > >> --- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> > >> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> > >> @@ -535,7 +535,6 @@ static int igt_ctx_exec(void *arg)
> > >>          IGT_TIMEOUT(end_time);
> > >>          LIST_HEAD(objects);
> > >>          unsigned long ncontexts, ndwords, dw;
> > >> -       bool first_shared_gtt = true;
> > >>          int err = -ENODEV;
> > >>
> > >>          /*
> > >> @@ -561,12 +560,7 @@ static int igt_ctx_exec(void *arg)
> > >>                  struct i915_gem_context *ctx;
> > >>                  unsigned int id;
> > >>
> > >> -               if (first_shared_gtt) {
> > >> -                       ctx = __create_hw_context(i915, file->driver_priv);
> > >> -                       first_shared_gtt = false;
> > >> -               } else {
> > >> -                       ctx = i915_gem_create_context(i915, file->driver_priv);
> > >> -               }
> > >> +               ctx = i915_gem_create_context(i915, file->driver_priv);
> > >>                  if (IS_ERR(ctx)) {
> > >>                          err = PTR_ERR(ctx);
> > >>                          goto out_unlock;
> > >> @@ -865,33 +859,6 @@ static int igt_switch_to_kernel_context(void
> > *arg)
> > >>          return err;
> > >>   }
> > >>
> > >> -static int fake_aliasing_ppgtt_enable(struct drm_i915_private *i915)
> > >> -{
> > >> -       struct drm_i915_gem_object *obj;
> > >> -       int err;
> > >> -
> > >> -       err = i915_gem_init_aliasing_ppgtt(i915);
> > >> -       if (err)
> > >> -               return err;
> > >> -
> > >> -       list_for_each_entry(obj, &i915->mm.bound_list, mm.link) {
> > >> -               struct i915_vma *vma;
> > >> -
> > >> -               vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
> > >> -               if (IS_ERR(vma))
> > >> -                       continue;
> > >> -
> > >> -               vma->flags &= ~I915_VMA_LOCAL_BIND;
> > >> -       }
> > >> -
> > >> -       return 0;
> > >> -}
> > >> -
> > >> -static void fake_aliasing_ppgtt_disable(struct drm_i915_private *i915)
> > >> -{
> > >> -       i915_gem_fini_aliasing_ppgtt(i915);
> > >> -}
> > >> -
> > >>   int i915_gem_context_mock_selftests(void)
> > >>   {
> > >>          static const struct i915_subtest tests[] = {
> > >> @@ -918,31 +885,9 @@ int i915_gem_context_live_selftests(struct
> > drm_i915_private *dev_priv)
> > >>                  SUBTEST(igt_ctx_exec),
> > >>                  SUBTEST(igt_ctx_readonly),
> > >>          };
> > >> -       bool fake_alias = false;
> > >> -       int err;
> > >>
> > >>          if (i915_terminally_wedged(&dev_priv->gpu_error))
> > >>                  return 0;
> > >>
> > >> -       /* Install a fake aliasing gtt for exercise */
> > >> -       if (USES_PPGTT(dev_priv) && !dev_priv->mm.aliasing_ppgtt) {
> > >> -               mutex_lock(&dev_priv->drm.struct_mutex);
> > >> -               err = fake_aliasing_ppgtt_enable(dev_priv);
> > >> -               mutex_unlock(&dev_priv->drm.struct_mutex);
> > >> -               if (err)
> > >> -                       return err;
> > >> -
> > >> -               GEM_BUG_ON(!dev_priv->mm.aliasing_ppgtt);
> > >> -               fake_alias = true;
> > >> -       }
> > >> -
> > >> -       err = i915_subtests(tests, dev_priv);
> > >> -
> > >> -       if (fake_alias) {
> > >> -               mutex_lock(&dev_priv->drm.struct_mutex);
> > >> -               fake_aliasing_ppgtt_disable(dev_priv);
> > >> -               mutex_unlock(&dev_priv->drm.struct_mutex);
> > >> -       }
> > >> -
> > >> -       return err;
> > >> +       return i915_subtests(tests, dev_priv);
> > >>   }
> > >> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
> > b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
> > >> index 128ad1cf0647..4365979d8222 100644
> > >> --- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
> > >> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
> > >> @@ -351,7 +351,7 @@ static int igt_evict_contexts(void *arg)
> > >>           * where the GTT space of the request is separate from the GGTT
> > >>           * allocation required to build the request.
> > >>           */
> > >> -       if (!USES_FULL_PPGTT(i915))
> > >> +       if (!HAS_FULL_PPGTT(i915))
> > >>                  return 0;
> > >>
> > >>          mutex_lock(&i915->drm.struct_mutex);
> > >> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> > b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> > >> index 8e2e269db97e..17b5aaaa7a50 100644
> > >> --- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> > >> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> > >> @@ -153,7 +153,7 @@ static int igt_ppgtt_alloc(void *arg)
> > >>
> > >>          /* Allocate a ppggt and try to fill the entire range */
> > >>
> > >> -       if (!USES_PPGTT(dev_priv))
> > >> +       if (!HAS_PPGTT(dev_priv))
> > >>                  return 0;
> > >>
> > >>          ppgtt = __hw_ppgtt_create(dev_priv);
> > >> @@ -1001,7 +1001,7 @@ static int exercise_ppgtt(struct
> > drm_i915_private *dev_priv,
> > >>          IGT_TIMEOUT(end_time);
> > >>          int err;
> > >>
> > >> -       if (!USES_FULL_PPGTT(dev_priv))
> > >> +       if (!HAS_FULL_PPGTT(dev_priv))
> > >>                  return 0;
> > >>
> > >>          file = mock_file(dev_priv);
> > >> --
> > >> 2.19.0
> > >>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v4] drm/i915: Remove i915.enable_ppgtt override
  2018-09-26  8:02       ` Joonas Lahtinen
@ 2018-09-26 12:29         ` Zhi Wang
  2018-10-08  9:53         ` Zhenyu Wang
  1 sibling, 0 replies; 24+ messages in thread
From: Zhi Wang @ 2018-09-26 12:29 UTC (permalink / raw)
  To: Joonas Lahtinen, He, Min, intel-gfx, Chris Wilson, Zhenyu Wang
  Cc: Auld, Matthew

Sure. Acked-by: Zhi Wang <zhi.a.wang@intel.com>

Meanwhile, I could send a patch to remove 
gen8_preallocate_top_level_pdp() in i915_gem_gtt.c, which is only used 
by vGPU with 32bit PPGTT (no one is going to use them after this patch 
is landed)

Thanks,
Zhi.

On 09/26/18 04:02, Joonas Lahtinen wrote:
> Quoting He, Min (2018-09-26 04:06:25)
>> No. We changed to full 48bit ppgtt long time ago. :)
> 
> So would that mean the change is OK to do?
> 
> Acked-by from you, Zhi, would be good to have for documentation purposes
> in that case :)
> 
> Regards, Joonas
> 
>>
>>> -----Original Message-----
>>> From: Wang, Zhi A
>>> Sent: Wednesday, September 26, 2018 2:01 AM
>>> To: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>; Chris Wilson
>>> <chris@chris-wilson.co.uk>; intel-gfx@lists.freedesktop.org; Zhenyu Wang
>>> <zhenyuw@linux.intel.com>
>>> Cc: Auld, Matthew <matthew.auld@intel.com>; He, Min <min.he@intel.com>
>>> Subject: Re: [PATCH v4] drm/i915: Remove i915.enable_ppgtt override
>>>
>>> Hi Min:
>>>
>>> I remembered the IOTG guest kernel is using aliasing-ppgtt in the last
>>> technical sharing (probably I didn't remember it correctly). Can you
>>> confirm?
>>>
>>> Also, thanks Joonas for the reminding. :)
>>>
>>> thanks,
>>> Zhi.
>>>
>>> On 09/25/18 09:22, Joonas Lahtinen wrote:
>>>> + Zhi and Zhenyu
>>>>
>>>> For me the patch looks ok.
>>>>
>>>> It refuses to load GVT on systems where 48-bit is not supported, for not
>>>> worsening the system security when virtualization is enabled (as anybody
>>>> would probably expect virtualization to improve that). Please see code.
>>>>
>>>> Do we have such systems in the wild? Should we instruct the user to
>>>> updating the hypervisor to specific kernel version when they hit the
>>>> error?
>>>>
>>>> Regards, Joonas
>>>>
>>>> Quoting Chris Wilson (2018-09-25 14:48:20)
>>>>> Now that we are confident in providing full-ppgtt where supported,
>>>>> remove the ability to override the context isolation.
>>>>>
>>>>> v2: Remove faked aliasing-ppgtt for testing as it no longer is accepted.
>>>>> v3: s/USES/HAS/ to match usage and reject attempts to load the module
>>> on
>>>>> old GVT-g setups that do not provide support for full-ppgtt.
>>>>>
>>>>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>>>>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>>>>> Cc: Matthew Auld <matthew.auld@intel.com>
>>>>> ---
>>>>>    drivers/gpu/drm/i915/i915_drv.c               | 22 +++--
>>>>>    drivers/gpu/drm/i915/i915_drv.h               | 14 +--
>>>>>    drivers/gpu/drm/i915/i915_gem_context.c       |  2 +-
>>>>>    drivers/gpu/drm/i915/i915_gem_gtt.c           | 88 ++-----------------
>>>>>    drivers/gpu/drm/i915/i915_gpu_error.c         |  4 +-
>>>>>    drivers/gpu/drm/i915/i915_params.c            |  4 -
>>>>>    drivers/gpu/drm/i915/i915_params.h            |  1 -
>>>>>    drivers/gpu/drm/i915/i915_pci.c               | 17 ++--
>>>>>    drivers/gpu/drm/i915/intel_device_info.c      |  6 ++
>>>>>    drivers/gpu/drm/i915/intel_device_info.h      | 11 ++-
>>>>>    drivers/gpu/drm/i915/intel_lrc.c              | 13 ++-
>>>>>    drivers/gpu/drm/i915/selftests/huge_pages.c   | 12 +--
>>>>>    .../gpu/drm/i915/selftests/i915_gem_context.c | 59 +------------
>>>>>    .../gpu/drm/i915/selftests/i915_gem_evict.c   |  2 +-
>>>>>    drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |  4 +-
>>>>>    15 files changed, 62 insertions(+), 197 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/i915_drv.c
>>> b/drivers/gpu/drm/i915/i915_drv.c
>>>>> index 44e2c0f5ec50..3efbbc71c3b4 100644
>>>>> --- a/drivers/gpu/drm/i915/i915_drv.c
>>>>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>>>>> @@ -345,7 +345,7 @@ static int i915_getparam_ioctl(struct drm_device
>>> *dev, void *data,
>>>>>                   value = HAS_WT(dev_priv);
>>>>>                   break;
>>>>>           case I915_PARAM_HAS_ALIASING_PPGTT:
>>>>> -               value = USES_PPGTT(dev_priv);
>>>>> +               value = INTEL_PPGTT(dev_priv);
>>>>>                   break;
>>>>>           case I915_PARAM_HAS_SEMAPHORES:
>>>>>                   value = HAS_LEGACY_SEMAPHORES(dev_priv);
>>>>> @@ -1049,17 +1049,6 @@ static void i915_driver_cleanup_mmio(struct
>>> drm_i915_private *dev_priv)
>>>>>
>>>>>    static void intel_sanitize_options(struct drm_i915_private *dev_priv)
>>>>>    {
>>>>> -       /*
>>>>> -        * i915.enable_ppgtt is read-only, so do an early pass to validate the
>>>>> -        * user's requested state against the hardware/driver capabilities.
>>> We
>>>>> -        * do this now so that we can print out any log messages once rather
>>>>> -        * than every time we check intel_enable_ppgtt().
>>>>> -        */
>>>>> -       i915_modparams.enable_ppgtt =
>>>>> -               intel_sanitize_enable_ppgtt(dev_priv,
>>>>> -                                           i915_modparams.enable_ppgtt);
>>>>> -       DRM_DEBUG_DRIVER("ppgtt mode: %i\n",
>>> i915_modparams.enable_ppgtt);
>>>>> -
>>>>>           intel_gvt_sanitize_options(dev_priv);
>>>>>    }
>>>>>
>>>>> @@ -1374,6 +1363,15 @@ static int i915_driver_init_hw(struct
>>> drm_i915_private *dev_priv)
>>>>>
>>>>>           intel_device_info_runtime_init(mkwrite_device_info(dev_priv));
>>>>>
>>>>> +       if (HAS_PPGTT(dev_priv)) {
>>>>> +               if (intel_vgpu_active(dev_priv) &&
>>>>> +                   !intel_vgpu_has_full_48bit_ppgtt(dev_priv)) {
>>>>> +                       i915_report_error(dev_priv,
>>>>> +                                         "incompatible vGPU found, support for isolated
>>> ppGTT required\n");
>>>>> +                       return -ENXIO;
>>>>> +               }
>>>>> +       }
>>>>> +
>>>>>           intel_sanitize_options(dev_priv);
>>>>>
>>>>>           i915_perf_init(dev_priv);
>>>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>>> b/drivers/gpu/drm/i915/i915_drv.h
>>>>> index 8624b4bdc242..f28b3c2a3cd2 100644
>>>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>>>> @@ -2593,9 +2593,14 @@ intel_info(const struct drm_i915_private
>>> *dev_priv)
>>>>>
>>>>>    #define HAS_EXECLISTS(dev_priv)
>>> HAS_LOGICAL_RING_CONTEXTS(dev_priv)
>>>>>
>>>>> -#define USES_PPGTT(dev_priv)           (i915_modparams.enable_ppgtt)
>>>>> -#define USES_FULL_PPGTT(dev_priv)
>>> (i915_modparams.enable_ppgtt >= 2)
>>>>> -#define USES_FULL_48BIT_PPGTT(dev_priv)
>>> (i915_modparams.enable_ppgtt == 3)
>>>>> +#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt)
>>>>> +#define HAS_PPGTT(dev_priv) \
>>>>> +       (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
>>>>> +#define HAS_FULL_PPGTT(dev_priv) \
>>>>> +       (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
>>>>> +#define HAS_FULL_48BIT_PPGTT(dev_priv) \
>>>>> +       (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL_4LVL)
>>>>> +
>>>>>    #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
>>>>>           GEM_BUG_ON((sizes) == 0); \
>>>>>           ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
>>>>> @@ -2743,9 +2748,6 @@ intel_ggtt_update_needs_vtd_wa(struct
>>> drm_i915_private *dev_priv)
>>>>>           return IS_BROXTON(dev_priv) && intel_vtd_active();
>>>>>    }
>>>>>
>>>>> -int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
>>>>> -                               int enable_ppgtt);
>>>>> -
>>>>>    /* i915_drv.c */
>>>>>    void __printf(3, 4)
>>>>>    __i915_printk(struct drm_i915_private *dev_priv, const char *level,
>>>>> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
>>> b/drivers/gpu/drm/i915/i915_gem_context.c
>>>>> index f772593b99ab..15c92f75b1b8 100644
>>>>> --- a/drivers/gpu/drm/i915/i915_gem_context.c
>>>>> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
>>>>> @@ -414,7 +414,7 @@ i915_gem_create_context(struct
>>> drm_i915_private *dev_priv,
>>>>>           if (IS_ERR(ctx))
>>>>>                   return ctx;
>>>>>
>>>>> -       if (USES_FULL_PPGTT(dev_priv)) {
>>>>> +       if (HAS_FULL_PPGTT(dev_priv)) {
>>>>>                   struct i915_hw_ppgtt *ppgtt;
>>>>>
>>>>>                   ppgtt = i915_ppgtt_create(dev_priv, file_priv);
>>>>> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
>>> b/drivers/gpu/drm/i915/i915_gem_gtt.c
>>>>> index f6c7ab413081..c9363504949f 100644
>>>>> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
>>>>> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
>>>>> @@ -133,55 +133,6 @@ static inline void i915_ggtt_invalidate(struct
>>> drm_i915_private *i915)
>>>>>           i915->ggtt.invalidate(i915);
>>>>>    }
>>>>>
>>>>> -int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
>>>>> -                               int enable_ppgtt)
>>>>> -{
>>>>> -       bool has_full_ppgtt;
>>>>> -       bool has_full_48bit_ppgtt;
>>>>> -
>>>>> -       if (!dev_priv->info.has_aliasing_ppgtt)
>>>>> -               return 0;
>>>>> -
>>>>> -       has_full_ppgtt = dev_priv->info.has_full_ppgtt;
>>>>> -       has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt;
>>>>> -
>>>>> -       if (intel_vgpu_active(dev_priv)) {
>>>>> -               /* GVT-g has no support for 32bit ppgtt */
>>>>> -               has_full_ppgtt = false;
>>>>> -               has_full_48bit_ppgtt =
>>> intel_vgpu_has_full_48bit_ppgtt(dev_priv);
>>>>> -       }
>>>>> -
>>>>> -       /*
>>>>> -        * We don't allow disabling PPGTT for gen8+ as it's a requirement for
>>>>> -        * execlists, the sole mechanism available to submit work.
>>>>> -        */
>>>>> -       if (enable_ppgtt == 0 && !HAS_EXECLISTS(dev_priv))
>>>>> -               return 0;
>>>>> -
>>>>> -       if (enable_ppgtt == 1)
>>>>> -               return 1;
>>>>> -
>>>>> -       if (enable_ppgtt == 2 && has_full_ppgtt)
>>>>> -               return 2;
>>>>> -
>>>>> -       if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
>>>>> -               return 3;
>>>>> -
>>>>> -       /* Disable ppgtt on SNB if VT-d is on. */
>>>>> -       if (IS_GEN6(dev_priv) && intel_vtd_active()) {
>>>>> -               DRM_INFO("Disabling PPGTT because VT-d is on\n");
>>>>> -               return 0;
>>>>> -       }
>>>>> -
>>>>> -       if (has_full_48bit_ppgtt)
>>>>> -               return 3;
>>>>> -
>>>>> -       if (has_full_ppgtt)
>>>>> -               return 2;
>>>>> -
>>>>> -       return 1;
>>>>> -}
>>>>> -
>>>>>    static int ppgtt_bind_vma(struct i915_vma *vma,
>>>>>                             enum i915_cache_level cache_level,
>>>>>                             u32 unused)
>>>>> @@ -1647,7 +1598,7 @@ static struct i915_hw_ppgtt
>>> *gen8_ppgtt_create(struct drm_i915_private *i915)
>>>>>           ppgtt->vm.i915 = i915;
>>>>>           ppgtt->vm.dma = &i915->drm.pdev->dev;
>>>>>
>>>>> -       ppgtt->vm.total = USES_FULL_48BIT_PPGTT(i915) ?
>>>>> +       ppgtt->vm.total = HAS_FULL_48BIT_PPGTT(i915) ?
>>>>>                   1ULL << 48 :
>>>>>                   1ULL << 32;
>>>>>
>>>>> @@ -1782,19 +1733,6 @@ static inline void gen6_write_pde(const struct
>>> gen6_hw_ppgtt *ppgtt,
>>>>>                     ppgtt->pd_addr + pde);
>>>>>    }
>>>>>
>>>>> -static void gen8_ppgtt_enable(struct drm_i915_private *dev_priv)
>>>>> -{
>>>>> -       struct intel_engine_cs *engine;
>>>>> -       enum intel_engine_id id;
>>>>> -
>>>>> -       for_each_engine(engine, dev_priv, id) {
>>>>> -               u32 four_level = USES_FULL_48BIT_PPGTT(dev_priv) ?
>>>>> -                                GEN8_GFX_PPGTT_48B : 0;
>>>>> -               I915_WRITE(RING_MODE_GEN7(engine),
>>>>> -                          _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
>>>>> -       }
>>>>> -}
>>>>> -
>>>>>    static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv)
>>>>>    {
>>>>>           struct intel_engine_cs *engine;
>>>>> @@ -1834,7 +1772,8 @@ static void gen6_ppgtt_enable(struct
>>> drm_i915_private *dev_priv)
>>>>>           ecochk = I915_READ(GAM_ECOCHK);
>>>>>           I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
>>> ECOCHK_PPGTT_CACHE64B);
>>>>>
>>>>> -       I915_WRITE(GFX_MODE,
>>> _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
>>>>> +       if (HAS_PPGTT(dev_priv)) /* may be disabled for VT-d */
>>>>> +               I915_WRITE(GFX_MODE,
>>> _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
>>>>>    }
>>>>>
>>>>>    /* PPGTT support for Sandybdrige/Gen6 and later */
>>>>> @@ -2237,23 +2176,10 @@ int i915_ppgtt_init_hw(struct
>>> drm_i915_private *dev_priv)
>>>>>    {
>>>>>           gtt_write_workarounds(dev_priv);
>>>>>
>>>>> -       /* In the case of execlists, PPGTT is enabled by the context descriptor
>>>>> -        * and the PDPs are contained within the context itself.  We don't
>>>>> -        * need to do anything here. */
>>>>> -       if (HAS_LOGICAL_RING_CONTEXTS(dev_priv))
>>>>> -               return 0;
>>>>> -
>>>>> -       if (!USES_PPGTT(dev_priv))
>>>>> -               return 0;
>>>>> -
>>>>>           if (IS_GEN6(dev_priv))
>>>>>                   gen6_ppgtt_enable(dev_priv);
>>>>>           else if (IS_GEN7(dev_priv))
>>>>>                   gen7_ppgtt_enable(dev_priv);
>>>>> -       else if (INTEL_GEN(dev_priv) >= 8)
>>>>> -               gen8_ppgtt_enable(dev_priv);
>>>>> -       else
>>>>> -               MISSING_CASE(INTEL_GEN(dev_priv));
>>>>>
>>>>>           return 0;
>>>>>    }
>>>>> @@ -2952,7 +2878,7 @@ int i915_gem_init_ggtt(struct drm_i915_private
>>> *dev_priv)
>>>>>           /* And finally clear the reserved guard page */
>>>>>           ggtt->vm.clear_range(&ggtt->vm, ggtt->vm.total - PAGE_SIZE,
>>> PAGE_SIZE);
>>>>>
>>>>> -       if (USES_PPGTT(dev_priv) && !USES_FULL_PPGTT(dev_priv)) {
>>>>> +       if (INTEL_PPGTT(dev_priv) == INTEL_PPGTT_ALIASING) {
>>>>>                   ret = i915_gem_init_aliasing_ppgtt(dev_priv);
>>>>>                   if (ret)
>>>>>                           goto err;
>>>>> @@ -3275,7 +3201,7 @@ static void bdw_setup_private_ppat(struct
>>> intel_ppat *ppat)
>>>>>           ppat->match = bdw_private_pat_match;
>>>>>           ppat->clear_value = GEN8_PPAT_WB | GEN8_PPAT_LLCELLC |
>>> GEN8_PPAT_AGE(3);
>>>>>
>>>>> -       if (!USES_PPGTT(ppat->i915)) {
>>>>> +       if (!HAS_PPGTT(ppat->i915)) {
>>>>>                   /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
>>>>>                    * so RTL will always use the value corresponding to
>>>>>                    * pat_sel = 000".
>>>>> @@ -3402,7 +3328,7 @@ static int gen8_gmch_probe(struct i915_ggtt
>>> *ggtt)
>>>>>           ggtt->vm.cleanup = gen6_gmch_remove;
>>>>>           ggtt->vm.insert_page = gen8_ggtt_insert_page;
>>>>>           ggtt->vm.clear_range = nop_clear_range;
>>>>> -       if (!USES_FULL_PPGTT(dev_priv) ||
>>> intel_scanout_needs_vtd_wa(dev_priv))
>>>>> +       if (intel_scanout_needs_vtd_wa(dev_priv))
>>>>>                   ggtt->vm.clear_range = gen8_ggtt_clear_range;
>>>>>
>>>>>           ggtt->vm.insert_entries = gen8_ggtt_insert_entries;
>>>>> @@ -3609,7 +3535,7 @@ int i915_ggtt_init_hw(struct drm_i915_private
>>> *dev_priv)
>>>>>           /* Only VLV supports read-only GGTT mappings */
>>>>>           ggtt->vm.has_read_only = IS_VALLEYVIEW(dev_priv);
>>>>>
>>>>> -       if (!HAS_LLC(dev_priv) && !USES_PPGTT(dev_priv))
>>>>> +       if (!HAS_LLC(dev_priv) && !HAS_PPGTT(dev_priv))
>>>>>                   ggtt->vm.mm.color_adjust = i915_gtt_color_adjust;
>>>>>           mutex_unlock(&dev_priv->drm.struct_mutex);
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
>>> b/drivers/gpu/drm/i915/i915_gpu_error.c
>>>>> index 2835cacd0d08..3d5554f14dfd 100644
>>>>> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
>>>>> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
>>>>> @@ -474,7 +474,7 @@ static void error_print_engine(struct
>>> drm_i915_error_state_buf *m,
>>>>>                           err_printf(m, "  SYNC_2: 0x%08x\n",
>>>>>                                      ee->semaphore_mboxes[2]);
>>>>>           }
>>>>> -       if (USES_PPGTT(m->i915)) {
>>>>> +       if (HAS_PPGTT(m->i915)) {
>>>>>                   err_printf(m, "  GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
>>>>>
>>>>>                   if (INTEL_GEN(m->i915) >= 8) {
>>>>> @@ -1230,7 +1230,7 @@ static void
>>> error_record_engine_registers(struct i915_gpu_state *error,
>>>>>           ee->reset_count = i915_reset_engine_count(&dev_priv->gpu_error,
>>>>>                                                     engine);
>>>>>
>>>>> -       if (USES_PPGTT(dev_priv)) {
>>>>> +       if (HAS_PPGTT(dev_priv)) {
>>>>>                   int i;
>>>>>
>>>>>                   ee->vm_info.gfx_mode =
>>> I915_READ(RING_MODE_GEN7(engine));
>>>>> diff --git a/drivers/gpu/drm/i915/i915_params.c
>>> b/drivers/gpu/drm/i915/i915_params.c
>>>>> index 295e981e4a39..bd6bd8879cab 100644
>>>>> --- a/drivers/gpu/drm/i915/i915_params.c
>>>>> +++ b/drivers/gpu/drm/i915/i915_params.c
>>>>> @@ -82,10 +82,6 @@ i915_param_named_unsafe(enable_hangcheck,
>>> bool, 0644,
>>>>>           "WARNING: Disabling this can cause system wide hangs. "
>>>>>           "(default: true)");
>>>>>
>>>>> -i915_param_named_unsafe(enable_ppgtt, int, 0400,
>>>>> -       "Override PPGTT usage. "
>>>>> -       "(-1=auto [default], 0=disabled, 1=aliasing, 2=full, 3=full with
>>> extended address space)");
>>>>> -
>>>>>    i915_param_named_unsafe(enable_psr, int, 0600,
>>>>>           "Enable PSR "
>>>>>           "(0=disabled, 1=enabled) "
>>>>> diff --git a/drivers/gpu/drm/i915/i915_params.h
>>> b/drivers/gpu/drm/i915/i915_params.h
>>>>> index 6c4d4a21474b..7e56c516c815 100644
>>>>> --- a/drivers/gpu/drm/i915/i915_params.h
>>>>> +++ b/drivers/gpu/drm/i915/i915_params.h
>>>>> @@ -41,7 +41,6 @@ struct drm_printer;
>>>>>           param(int, vbt_sdvo_panel_type, -1) \
>>>>>           param(int, enable_dc, -1) \
>>>>>           param(int, enable_fbc, -1) \
>>>>> -       param(int, enable_ppgtt, -1) \
>>>>>           param(int, enable_psr, -1) \
>>>>>           param(int, disable_power_well, -1) \
>>>>>           param(int, enable_ips, 1) \
>>>>> diff --git a/drivers/gpu/drm/i915/i915_pci.c
>>> b/drivers/gpu/drm/i915/i915_pci.c
>>>>> index d6f7b9fe1d26..eeec902896b9 100644
>>>>> --- a/drivers/gpu/drm/i915/i915_pci.c
>>>>> +++ b/drivers/gpu/drm/i915/i915_pci.c
>>>>> @@ -252,7 +252,7 @@ static const struct intel_device_info
>>> intel_ironlake_m_info = {
>>>>>           .has_llc = 1, \
>>>>>           .has_rc6 = 1, \
>>>>>           .has_rc6p = 1, \
>>>>> -       .has_aliasing_ppgtt = 1, \
>>>>> +       .ppgtt = INTEL_PPGTT_ALIASING, \
>>>>>           GEN_DEFAULT_PIPEOFFSETS, \
>>>>>           GEN_DEFAULT_PAGE_SIZES, \
>>>>>           CURSOR_OFFSETS
>>>>> @@ -297,8 +297,7 @@ static const struct intel_device_info
>>> intel_sandybridge_m_gt2_info = {
>>>>>           .has_llc = 1, \
>>>>>           .has_rc6 = 1, \
>>>>>           .has_rc6p = 1, \
>>>>> -       .has_aliasing_ppgtt = 1, \
>>>>> -       .has_full_ppgtt = 1, \
>>>>> +       .ppgtt = INTEL_PPGTT_FULL, \
>>>>>           GEN_DEFAULT_PIPEOFFSETS, \
>>>>>           GEN_DEFAULT_PAGE_SIZES, \
>>>>>           IVB_CURSOR_OFFSETS
>>>>> @@ -351,8 +350,7 @@ static const struct intel_device_info
>>> intel_valleyview_info = {
>>>>>           .has_rc6 = 1,
>>>>>           .has_gmch_display = 1,
>>>>>           .has_hotplug = 1,
>>>>> -       .has_aliasing_ppgtt = 1,
>>>>> -       .has_full_ppgtt = 1,
>>>>> +       .ppgtt = INTEL_PPGTT_FULL,
>>>>>           .has_snoop = true,
>>>>>           .has_coherent_ggtt = false,
>>>>>           .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
>>>>> @@ -399,7 +397,7 @@ static const struct intel_device_info
>>> intel_haswell_gt3_info = {
>>>>>           .page_sizes = I915_GTT_PAGE_SIZE_4K | \
>>>>>                         I915_GTT_PAGE_SIZE_2M, \
>>>>>           .has_logical_ring_contexts = 1, \
>>>>> -       .has_full_48bit_ppgtt = 1, \
>>>>> +       .ppgtt = INTEL_PPGTT_FULL_4LVL, \
>>>>>           .has_64bit_reloc = 1, \
>>>>>           .has_reset_engine = 1
>>>>>
>>>>> @@ -443,8 +441,7 @@ static const struct intel_device_info
>>> intel_cherryview_info = {
>>>>>           .has_rc6 = 1,
>>>>>           .has_logical_ring_contexts = 1,
>>>>>           .has_gmch_display = 1,
>>>>> -       .has_aliasing_ppgtt = 1,
>>>>> -       .has_full_ppgtt = 1,
>>>>> +       .ppgtt = INTEL_PPGTT_FULL,
>>>>>           .has_reset_engine = 1,
>>>>>           .has_snoop = true,
>>>>>           .has_coherent_ggtt = false,
>>>>> @@ -518,9 +515,7 @@ static const struct intel_device_info
>>> intel_skylake_gt4_info = {
>>>>>           .has_logical_ring_contexts = 1, \
>>>>>           .has_logical_ring_preemption = 1, \
>>>>>           .has_guc = 1, \
>>>>> -       .has_aliasing_ppgtt = 1, \
>>>>> -       .has_full_ppgtt = 1, \
>>>>> -       .has_full_48bit_ppgtt = 1, \
>>>>> +       .ppgtt = INTEL_PPGTT_FULL_4LVL, \
>>>>>           .has_reset_engine = 1, \
>>>>>           .has_snoop = true, \
>>>>>           .has_coherent_ggtt = false, \
>>>>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
>>> b/drivers/gpu/drm/i915/intel_device_info.c
>>>>> index 0ef0c6448d53..a841d181efd3 100644
>>>>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>>>>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>>>>> @@ -26,6 +26,7 @@
>>>>>
>>>>>    #include "intel_device_info.h"
>>>>>    #include "i915_drv.h"
>>>>> +#include "i915_vgpu.h"
>>>>>
>>>>>    #define PLATFORM_NAME(x) [INTEL_##x] = #x
>>>>>    static const char * const platform_names[] = {
>>>>> @@ -851,6 +852,11 @@ void intel_device_info_runtime_init(struct
>>> intel_device_info *info)
>>>>>           else if (INTEL_GEN(dev_priv) >= 11)
>>>>>                   gen11_sseu_info_init(dev_priv);
>>>>>
>>>>> +       if (IS_GEN6(dev_priv) && intel_vtd_active()) {
>>>>> +               DRM_INFO("Disabling ppGTT for VT-d support\n");
>>>>> +               info->ppgtt = INTEL_PPGTT_NONE;
>>>>> +       }
>>>>> +
>>>>>           /* Initialize command stream timestamp frequency */
>>>>>           info->cs_timestamp_frequency_khz =
>>> read_timestamp_frequency(dev_priv);
>>>>>    }
>>>>> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
>>> b/drivers/gpu/drm/i915/intel_device_info.h
>>>>> index 6eecd64734d5..6bab97687328 100644
>>>>> --- a/drivers/gpu/drm/i915/intel_device_info.h
>>>>> +++ b/drivers/gpu/drm/i915/intel_device_info.h
>>>>> @@ -74,21 +74,25 @@ enum intel_platform {
>>>>>           INTEL_MAX_PLATFORMS
>>>>>    };
>>>>>
>>>>> +enum intel_ppgtt {
>>>>> +       INTEL_PPGTT_NONE = 0,
>>>>> +       INTEL_PPGTT_ALIASING,
>>>>> +       INTEL_PPGTT_FULL,
>>>>> +       INTEL_PPGTT_FULL_4LVL,
>>>>> +};
>>>>> +
>>>>>    #define DEV_INFO_FOR_EACH_FLAG(func) \
>>>>>           func(is_mobile); \
>>>>>           func(is_lp); \
>>>>>           func(is_alpha_support); \
>>>>>           /* Keep has_* in alphabetical order */ \
>>>>>           func(has_64bit_reloc); \
>>>>> -       func(has_aliasing_ppgtt); \
>>>>>           func(has_csr); \
>>>>>           func(has_ddi); \
>>>>>           func(has_dp_mst); \
>>>>>           func(has_reset_engine); \
>>>>>           func(has_fbc); \
>>>>>           func(has_fpga_dbg); \
>>>>> -       func(has_full_ppgtt); \
>>>>> -       func(has_full_48bit_ppgtt); \
>>>>>           func(has_gmch_display); \
>>>>>           func(has_guc); \
>>>>>           func(has_guc_ct); \
>>>>> @@ -154,6 +158,7 @@ struct intel_device_info {
>>>>>           enum intel_platform platform;
>>>>>           u32 platform_mask;
>>>>>
>>>>> +       enum intel_ppgtt ppgtt;
>>>>>           unsigned int page_sizes; /* page sizes supported by the HW */
>>>>>
>>>>>           u32 display_mmio_offset;
>>>>> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
>>> b/drivers/gpu/drm/i915/intel_lrc.c
>>>>> index 4b28225320ff..3836a8a3761a 100644
>>>>> --- a/drivers/gpu/drm/i915/intel_lrc.c
>>>>> +++ b/drivers/gpu/drm/i915/intel_lrc.c
>>>>> @@ -418,9 +418,8 @@ execlists_update_context_pdps(struct
>>> i915_hw_ppgtt *ppgtt, u32 *reg_state)
>>>>>
>>>>>    static u64 execlists_update_context(struct i915_request *rq)
>>>>>    {
>>>>> +       struct i915_hw_ppgtt *ppgtt = rq->gem_context->ppgtt;
>>>>>           struct intel_context *ce = rq->hw_context;
>>>>> -       struct i915_hw_ppgtt *ppgtt =
>>>>> -               rq->gem_context->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
>>>>>           u32 *reg_state = ce->lrc_reg_state;
>>>>>
>>>>>           reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail);
>>>>> @@ -1376,7 +1375,7 @@ execlists_context_pin(struct intel_engine_cs
>>> *engine,
>>>>>           struct intel_context *ce = to_intel_context(ctx, engine);
>>>>>
>>>>>           lockdep_assert_held(&ctx->i915->drm.struct_mutex);
>>>>> -       GEM_BUG_ON(!(ctx->ppgtt ?: ctx->i915->mm.aliasing_ppgtt));
>>>>> +       GEM_BUG_ON(!ctx->ppgtt);
>>>>>
>>>>>           if (likely(ce->pin_count++))
>>>>>                   return ce;
>>>>> @@ -2031,8 +2030,7 @@ static int gen8_emit_bb_start(struct
>>> i915_request *rq,
>>>>>            * it is unsafe in case of lite-restore (because the ctx is
>>>>>            * not idle). PML4 is allocated during ppgtt init so this is
>>>>>            * not needed in 48-bit.*/
>>>>> -       if (rq->gem_context->ppgtt &&
>>>>> -           (intel_engine_flag(rq->engine) & rq->gem_context->ppgtt-
>>>> pd_dirty_rings) &&
>>>>> +       if ((intel_engine_flag(rq->engine) & rq->gem_context->ppgtt-
>>>> pd_dirty_rings) &&
>>>>>               !i915_vm_is_48bit(&rq->gem_context->ppgtt->vm) &&
>>>>>               !intel_vgpu_active(rq->i915)) {
>>>>>                   ret = intel_logical_ring_emit_pdps(rq);
>>>>> @@ -2634,7 +2632,6 @@ static void execlists_init_reg_state(u32 *regs,
>>>>>                                        struct intel_ring *ring)
>>>>>    {
>>>>>           struct drm_i915_private *dev_priv = engine->i915;
>>>>> -       struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: dev_priv-
>>>> mm.aliasing_ppgtt;
>>>>>           u32 base = engine->mmio_base;
>>>>>           bool rcs = engine->class == RENDER_CLASS;
>>>>>
>>>>> @@ -2706,12 +2703,12 @@ static void execlists_init_reg_state(u32 *regs,
>>>>>           CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0),
>>> 0);
>>>>>           CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0),
>>> 0);
>>>>>
>>>>> -       if (i915_vm_is_48bit(&ppgtt->vm)) {
>>>>> +       if (i915_vm_is_48bit(&ctx->ppgtt->vm)) {
>>>>>                   /* 64b PPGTT (48bit canonical)
>>>>>                    * PDP0_DESCRIPTOR contains the base address to PML4 and
>>>>>                    * other PDP Descriptors are ignored.
>>>>>                    */
>>>>> -               ASSIGN_CTX_PML4(ppgtt, regs);
>>>>> +               ASSIGN_CTX_PML4(ctx->ppgtt, regs);
>>>>>           }
>>>>>
>>>>>           if (rcs) {
>>>>> diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c
>>> b/drivers/gpu/drm/i915/selftests/huge_pages.c
>>>>> index 8d03f64eabd7..09ea65a29d98 100644
>>>>> --- a/drivers/gpu/drm/i915/selftests/huge_pages.c
>>>>> +++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
>>>>> @@ -1436,7 +1436,7 @@ static int igt_ppgtt_pin_update(void *arg)
>>>>>            * huge-gtt-pages.
>>>>>            */
>>>>>
>>>>> -       if (!USES_FULL_48BIT_PPGTT(dev_priv)) {
>>>>> +       if (!HAS_FULL_48BIT_PPGTT(dev_priv)) {
>>>>>                   pr_info("48b PPGTT not supported, skipping\n");
>>>>>                   return 0;
>>>>>           }
>>>>> @@ -1687,10 +1687,9 @@ int
>>> i915_gem_huge_page_mock_selftests(void)
>>>>>                   SUBTEST(igt_mock_ppgtt_huge_fill),
>>>>>                   SUBTEST(igt_mock_ppgtt_64K),
>>>>>           };
>>>>> -       int saved_ppgtt = i915_modparams.enable_ppgtt;
>>>>>           struct drm_i915_private *dev_priv;
>>>>> -       struct pci_dev *pdev;
>>>>>           struct i915_hw_ppgtt *ppgtt;
>>>>> +       struct pci_dev *pdev;
>>>>>           int err;
>>>>>
>>>>>           dev_priv = mock_gem_device();
>>>>> @@ -1698,7 +1697,7 @@ int i915_gem_huge_page_mock_selftests(void)
>>>>>                   return -ENOMEM;
>>>>>
>>>>>           /* Pretend to be a device which supports the 48b PPGTT */
>>>>> -       i915_modparams.enable_ppgtt = 3;
>>>>> +       mkwrite_device_info(dev_priv)->ppgtt = INTEL_PPGTT_FULL_4LVL;
>>>>>
>>>>>           pdev = dev_priv->drm.pdev;
>>>>>           dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(39));
>>>>> @@ -1731,9 +1730,6 @@ int i915_gem_huge_page_mock_selftests(void)
>>>>>
>>>>>    out_unlock:
>>>>>           mutex_unlock(&dev_priv->drm.struct_mutex);
>>>>> -
>>>>> -       i915_modparams.enable_ppgtt = saved_ppgtt;
>>>>> -
>>>>>           drm_dev_put(&dev_priv->drm);
>>>>>
>>>>>           return err;
>>>>> @@ -1753,7 +1749,7 @@ int i915_gem_huge_page_live_selftests(struct
>>> drm_i915_private *dev_priv)
>>>>>           struct i915_gem_context *ctx;
>>>>>           int err;
>>>>>
>>>>> -       if (!USES_PPGTT(dev_priv)) {
>>>>> +       if (!HAS_PPGTT(dev_priv)) {
>>>>>                   pr_info("PPGTT not supported, skipping live-selftests\n");
>>>>>                   return 0;
>>>>>           }
>>>>> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
>>> b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
>>>>> index 76df25aa90c9..913c0f83f86a 100644
>>>>> --- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
>>>>> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
>>>>> @@ -535,7 +535,6 @@ static int igt_ctx_exec(void *arg)
>>>>>           IGT_TIMEOUT(end_time);
>>>>>           LIST_HEAD(objects);
>>>>>           unsigned long ncontexts, ndwords, dw;
>>>>> -       bool first_shared_gtt = true;
>>>>>           int err = -ENODEV;
>>>>>
>>>>>           /*
>>>>> @@ -561,12 +560,7 @@ static int igt_ctx_exec(void *arg)
>>>>>                   struct i915_gem_context *ctx;
>>>>>                   unsigned int id;
>>>>>
>>>>> -               if (first_shared_gtt) {
>>>>> -                       ctx = __create_hw_context(i915, file->driver_priv);
>>>>> -                       first_shared_gtt = false;
>>>>> -               } else {
>>>>> -                       ctx = i915_gem_create_context(i915, file->driver_priv);
>>>>> -               }
>>>>> +               ctx = i915_gem_create_context(i915, file->driver_priv);
>>>>>                   if (IS_ERR(ctx)) {
>>>>>                           err = PTR_ERR(ctx);
>>>>>                           goto out_unlock;
>>>>> @@ -865,33 +859,6 @@ static int igt_switch_to_kernel_context(void
>>> *arg)
>>>>>           return err;
>>>>>    }
>>>>>
>>>>> -static int fake_aliasing_ppgtt_enable(struct drm_i915_private *i915)
>>>>> -{
>>>>> -       struct drm_i915_gem_object *obj;
>>>>> -       int err;
>>>>> -
>>>>> -       err = i915_gem_init_aliasing_ppgtt(i915);
>>>>> -       if (err)
>>>>> -               return err;
>>>>> -
>>>>> -       list_for_each_entry(obj, &i915->mm.bound_list, mm.link) {
>>>>> -               struct i915_vma *vma;
>>>>> -
>>>>> -               vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
>>>>> -               if (IS_ERR(vma))
>>>>> -                       continue;
>>>>> -
>>>>> -               vma->flags &= ~I915_VMA_LOCAL_BIND;
>>>>> -       }
>>>>> -
>>>>> -       return 0;
>>>>> -}
>>>>> -
>>>>> -static void fake_aliasing_ppgtt_disable(struct drm_i915_private *i915)
>>>>> -{
>>>>> -       i915_gem_fini_aliasing_ppgtt(i915);
>>>>> -}
>>>>> -
>>>>>    int i915_gem_context_mock_selftests(void)
>>>>>    {
>>>>>           static const struct i915_subtest tests[] = {
>>>>> @@ -918,31 +885,9 @@ int i915_gem_context_live_selftests(struct
>>> drm_i915_private *dev_priv)
>>>>>                   SUBTEST(igt_ctx_exec),
>>>>>                   SUBTEST(igt_ctx_readonly),
>>>>>           };
>>>>> -       bool fake_alias = false;
>>>>> -       int err;
>>>>>
>>>>>           if (i915_terminally_wedged(&dev_priv->gpu_error))
>>>>>                   return 0;
>>>>>
>>>>> -       /* Install a fake aliasing gtt for exercise */
>>>>> -       if (USES_PPGTT(dev_priv) && !dev_priv->mm.aliasing_ppgtt) {
>>>>> -               mutex_lock(&dev_priv->drm.struct_mutex);
>>>>> -               err = fake_aliasing_ppgtt_enable(dev_priv);
>>>>> -               mutex_unlock(&dev_priv->drm.struct_mutex);
>>>>> -               if (err)
>>>>> -                       return err;
>>>>> -
>>>>> -               GEM_BUG_ON(!dev_priv->mm.aliasing_ppgtt);
>>>>> -               fake_alias = true;
>>>>> -       }
>>>>> -
>>>>> -       err = i915_subtests(tests, dev_priv);
>>>>> -
>>>>> -       if (fake_alias) {
>>>>> -               mutex_lock(&dev_priv->drm.struct_mutex);
>>>>> -               fake_aliasing_ppgtt_disable(dev_priv);
>>>>> -               mutex_unlock(&dev_priv->drm.struct_mutex);
>>>>> -       }
>>>>> -
>>>>> -       return err;
>>>>> +       return i915_subtests(tests, dev_priv);
>>>>>    }
>>>>> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
>>> b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
>>>>> index 128ad1cf0647..4365979d8222 100644
>>>>> --- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
>>>>> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
>>>>> @@ -351,7 +351,7 @@ static int igt_evict_contexts(void *arg)
>>>>>            * where the GTT space of the request is separate from the GGTT
>>>>>            * allocation required to build the request.
>>>>>            */
>>>>> -       if (!USES_FULL_PPGTT(i915))
>>>>> +       if (!HAS_FULL_PPGTT(i915))
>>>>>                   return 0;
>>>>>
>>>>>           mutex_lock(&i915->drm.struct_mutex);
>>>>> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
>>> b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
>>>>> index 8e2e269db97e..17b5aaaa7a50 100644
>>>>> --- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
>>>>> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
>>>>> @@ -153,7 +153,7 @@ static int igt_ppgtt_alloc(void *arg)
>>>>>
>>>>>           /* Allocate a ppggt and try to fill the entire range */
>>>>>
>>>>> -       if (!USES_PPGTT(dev_priv))
>>>>> +       if (!HAS_PPGTT(dev_priv))
>>>>>                   return 0;
>>>>>
>>>>>           ppgtt = __hw_ppgtt_create(dev_priv);
>>>>> @@ -1001,7 +1001,7 @@ static int exercise_ppgtt(struct
>>> drm_i915_private *dev_priv,
>>>>>           IGT_TIMEOUT(end_time);
>>>>>           int err;
>>>>>
>>>>> -       if (!USES_FULL_PPGTT(dev_priv))
>>>>> +       if (!HAS_FULL_PPGTT(dev_priv))
>>>>>                   return 0;
>>>>>
>>>>>           file = mock_file(dev_priv);
>>>>> --
>>>>> 2.19.0
>>>>>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v4] drm/i915: Remove i915.enable_ppgtt override
  2018-09-25 13:27 ` Joonas Lahtinen
@ 2018-09-26 13:16   ` Joonas Lahtinen
  0 siblings, 0 replies; 24+ messages in thread
From: Joonas Lahtinen @ 2018-09-26 13:16 UTC (permalink / raw)
  To: Chris Wilson, intel-gfx; +Cc: Matthew Auld

Quoting Joonas Lahtinen (2018-09-25 16:27:47)
> Quoting Chris Wilson (2018-09-25 14:48:20)
> > Now that we are confident in providing full-ppgtt where supported,
> > remove the ability to override the context isolation.
> > 
> > v2: Remove faked aliasing-ppgtt for testing as it no longer is accepted.
> > v3: s/USES/HAS/ to match usage and reject attempts to load the module on
> > old GVT-g setups that do not provide support for full-ppgtt.
> > 
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > Cc: Matthew Auld <matthew.auld@intel.com>
> 
> <SNIP>
> 
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -345,7 +345,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
> >                 value = HAS_WT(dev_priv);
> >                 break;
> >         case I915_PARAM_HAS_ALIASING_PPGTT:
> > -               value = USES_PPGTT(dev_priv);
> > +               value = INTEL_PPGTT(dev_priv);
> >                 break;
> 
> Luckily nobody has decided to renumber the modparam values for the sake
> of our uAPI :P

With the uAPI header addition + translation (just highlight in the commit
message that we're just spelling out an existing uAPI), this is;

Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

Regards, Joonas

> 
> Maybe best to have the values in uapi header and then add a translation
> here to avoid such a problem in the future. I'd prefer to limit to just
> relying the information of 0 (none), 1 (aliasing) or 2 (full) unless
> somebody has slipped in code to userspace that relies on detecting the
> 48-bits from here instead the right place...
> 
> Regards, Joonas
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread
* [PATCH v5] drm/i915: Remove i915.enable_ppgtt override
  2018-09-25 11:48 [PATCH v4] drm/i915: Remove i915.enable_ppgtt override Chris Wilson
                   ` (4 preceding siblings ...)
  2018-09-25 13:27 ` Joonas Lahtinen
@ 2018-09-26 20:12 ` Chris Wilson
  2018-09-27  8:20   ` Joonas Lahtinen
  2018-09-26 21:34 ` ✗ Fi.CI.SPARSE: warning for drm/i915: Remove i915.enable_ppgtt override (rev2) Patchwork
                   ` (2 subsequent siblings)
  8 siblings, 1 reply; 24+ messages in thread
From: Chris Wilson @ 2018-09-26 20:12 UTC (permalink / raw)
  To: intel-gfx; +Cc: Matthew Auld

Now that we are confident in providing full-ppgtt where supported,
remove the ability to override the context isolation.

v2: Remove faked aliasing-ppgtt for testing as it no longer is accepted.
v3: s/USES/HAS/ to match usage and reject attempts to load the module on
old GVT-g setups that do not provide support for full-ppgtt.
v4: Insulate ABI ppGTT values from our internal enum (later plans
involve moving ppGTT depth out of the enum, thus potentially breaking
ABI unless we document the current values).

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> #v3
Acked-by: Zhi Wang <zhi.a.wang@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c               | 22 +++--
 drivers/gpu/drm/i915/i915_drv.h               | 14 +--
 drivers/gpu/drm/i915/i915_gem_context.c       |  2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c           | 88 ++-----------------
 drivers/gpu/drm/i915/i915_gpu_error.c         |  4 +-
 drivers/gpu/drm/i915/i915_params.c            |  4 -
 drivers/gpu/drm/i915/i915_params.h            |  1 -
 drivers/gpu/drm/i915/i915_pci.c               | 17 ++--
 drivers/gpu/drm/i915/intel_device_info.c      |  6 ++
 drivers/gpu/drm/i915/intel_device_info.h      | 13 ++-
 drivers/gpu/drm/i915/intel_lrc.c              | 13 ++-
 drivers/gpu/drm/i915/selftests/huge_pages.c   | 12 +--
 .../gpu/drm/i915/selftests/i915_gem_context.c | 59 +------------
 .../gpu/drm/i915/selftests/i915_gem_evict.c   |  2 +-
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |  4 +-
 include/uapi/drm/i915_drm.h                   |  8 ++
 16 files changed, 72 insertions(+), 197 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index ade9bca250fa..1b028f429e92 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -345,7 +345,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
 		value = HAS_WT(dev_priv);
 		break;
 	case I915_PARAM_HAS_ALIASING_PPGTT:
-		value = USES_PPGTT(dev_priv);
+		value = min_t(int, INTEL_PPGTT(dev_priv), I915_GEM_PPGTT_FULL);
 		break;
 	case I915_PARAM_HAS_SEMAPHORES:
 		value = HAS_LEGACY_SEMAPHORES(dev_priv);
@@ -1049,17 +1049,6 @@ static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
 
 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 {
-	/*
-	 * i915.enable_ppgtt is read-only, so do an early pass to validate the
-	 * user's requested state against the hardware/driver capabilities.  We
-	 * do this now so that we can print out any log messages once rather
-	 * than every time we check intel_enable_ppgtt().
-	 */
-	i915_modparams.enable_ppgtt =
-		intel_sanitize_enable_ppgtt(dev_priv,
-					    i915_modparams.enable_ppgtt);
-	DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
-
 	intel_gvt_sanitize_options(dev_priv);
 }
 
@@ -1374,6 +1363,15 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
 
 	intel_device_info_runtime_init(mkwrite_device_info(dev_priv));
 
+	if (HAS_PPGTT(dev_priv)) {
+		if (intel_vgpu_active(dev_priv) &&
+		    !intel_vgpu_has_full_48bit_ppgtt(dev_priv)) {
+			i915_report_error(dev_priv,
+					  "incompatible vGPU found, support for isolated ppGTT required\n");
+			return -ENXIO;
+		}
+	}
+
 	intel_sanitize_options(dev_priv);
 
 	i915_perf_init(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8624b4bdc242..f28b3c2a3cd2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2593,9 +2593,14 @@ intel_info(const struct drm_i915_private *dev_priv)
 
 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
 
-#define USES_PPGTT(dev_priv)		(i915_modparams.enable_ppgtt)
-#define USES_FULL_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt >= 2)
-#define USES_FULL_48BIT_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt == 3)
+#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt)
+#define HAS_PPGTT(dev_priv) \
+	(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
+#define HAS_FULL_PPGTT(dev_priv) \
+	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
+#define HAS_FULL_48BIT_PPGTT(dev_priv)	\
+	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL_4LVL)
+
 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
 	GEM_BUG_ON((sizes) == 0); \
 	((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
@@ -2743,9 +2748,6 @@ intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
 	return IS_BROXTON(dev_priv) && intel_vtd_active();
 }
 
-int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
-				int enable_ppgtt);
-
 /* i915_drv.c */
 void __printf(3, 4)
 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index f772593b99ab..15c92f75b1b8 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -414,7 +414,7 @@ i915_gem_create_context(struct drm_i915_private *dev_priv,
 	if (IS_ERR(ctx))
 		return ctx;
 
-	if (USES_FULL_PPGTT(dev_priv)) {
+	if (HAS_FULL_PPGTT(dev_priv)) {
 		struct i915_hw_ppgtt *ppgtt;
 
 		ppgtt = i915_ppgtt_create(dev_priv, file_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index f6c7ab413081..c9363504949f 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -133,55 +133,6 @@ static inline void i915_ggtt_invalidate(struct drm_i915_private *i915)
 	i915->ggtt.invalidate(i915);
 }
 
-int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
-			       	int enable_ppgtt)
-{
-	bool has_full_ppgtt;
-	bool has_full_48bit_ppgtt;
-
-	if (!dev_priv->info.has_aliasing_ppgtt)
-		return 0;
-
-	has_full_ppgtt = dev_priv->info.has_full_ppgtt;
-	has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt;
-
-	if (intel_vgpu_active(dev_priv)) {
-		/* GVT-g has no support for 32bit ppgtt */
-		has_full_ppgtt = false;
-		has_full_48bit_ppgtt = intel_vgpu_has_full_48bit_ppgtt(dev_priv);
-	}
-
-	/*
-	 * We don't allow disabling PPGTT for gen8+ as it's a requirement for
-	 * execlists, the sole mechanism available to submit work.
-	 */
-	if (enable_ppgtt == 0 && !HAS_EXECLISTS(dev_priv))
-		return 0;
-
-	if (enable_ppgtt == 1)
-		return 1;
-
-	if (enable_ppgtt == 2 && has_full_ppgtt)
-		return 2;
-
-	if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
-		return 3;
-
-	/* Disable ppgtt on SNB if VT-d is on. */
-	if (IS_GEN6(dev_priv) && intel_vtd_active()) {
-		DRM_INFO("Disabling PPGTT because VT-d is on\n");
-		return 0;
-	}
-
-	if (has_full_48bit_ppgtt)
-		return 3;
-
-	if (has_full_ppgtt)
-		return 2;
-
-	return 1;
-}
-
 static int ppgtt_bind_vma(struct i915_vma *vma,
 			  enum i915_cache_level cache_level,
 			  u32 unused)
@@ -1647,7 +1598,7 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
 	ppgtt->vm.i915 = i915;
 	ppgtt->vm.dma = &i915->drm.pdev->dev;
 
-	ppgtt->vm.total = USES_FULL_48BIT_PPGTT(i915) ?
+	ppgtt->vm.total = HAS_FULL_48BIT_PPGTT(i915) ?
 		1ULL << 48 :
 		1ULL << 32;
 
@@ -1782,19 +1733,6 @@ static inline void gen6_write_pde(const struct gen6_hw_ppgtt *ppgtt,
 		  ppgtt->pd_addr + pde);
 }
 
-static void gen8_ppgtt_enable(struct drm_i915_private *dev_priv)
-{
-	struct intel_engine_cs *engine;
-	enum intel_engine_id id;
-
-	for_each_engine(engine, dev_priv, id) {
-		u32 four_level = USES_FULL_48BIT_PPGTT(dev_priv) ?
-				 GEN8_GFX_PPGTT_48B : 0;
-		I915_WRITE(RING_MODE_GEN7(engine),
-			   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
-	}
-}
-
 static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv)
 {
 	struct intel_engine_cs *engine;
@@ -1834,7 +1772,8 @@ static void gen6_ppgtt_enable(struct drm_i915_private *dev_priv)
 	ecochk = I915_READ(GAM_ECOCHK);
 	I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
 
-	I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
+	if (HAS_PPGTT(dev_priv)) /* may be disabled for VT-d */
+		I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 }
 
 /* PPGTT support for Sandybdrige/Gen6 and later */
@@ -2237,23 +2176,10 @@ int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv)
 {
 	gtt_write_workarounds(dev_priv);
 
-	/* In the case of execlists, PPGTT is enabled by the context descriptor
-	 * and the PDPs are contained within the context itself.  We don't
-	 * need to do anything here. */
-	if (HAS_LOGICAL_RING_CONTEXTS(dev_priv))
-		return 0;
-
-	if (!USES_PPGTT(dev_priv))
-		return 0;
-
 	if (IS_GEN6(dev_priv))
 		gen6_ppgtt_enable(dev_priv);
 	else if (IS_GEN7(dev_priv))
 		gen7_ppgtt_enable(dev_priv);
-	else if (INTEL_GEN(dev_priv) >= 8)
-		gen8_ppgtt_enable(dev_priv);
-	else
-		MISSING_CASE(INTEL_GEN(dev_priv));
 
 	return 0;
 }
@@ -2952,7 +2878,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
 	/* And finally clear the reserved guard page */
 	ggtt->vm.clear_range(&ggtt->vm, ggtt->vm.total - PAGE_SIZE, PAGE_SIZE);
 
-	if (USES_PPGTT(dev_priv) && !USES_FULL_PPGTT(dev_priv)) {
+	if (INTEL_PPGTT(dev_priv) == INTEL_PPGTT_ALIASING) {
 		ret = i915_gem_init_aliasing_ppgtt(dev_priv);
 		if (ret)
 			goto err;
@@ -3275,7 +3201,7 @@ static void bdw_setup_private_ppat(struct intel_ppat *ppat)
 	ppat->match = bdw_private_pat_match;
 	ppat->clear_value = GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3);
 
-	if (!USES_PPGTT(ppat->i915)) {
+	if (!HAS_PPGTT(ppat->i915)) {
 		/* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
 		 * so RTL will always use the value corresponding to
 		 * pat_sel = 000".
@@ -3402,7 +3328,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
 	ggtt->vm.cleanup = gen6_gmch_remove;
 	ggtt->vm.insert_page = gen8_ggtt_insert_page;
 	ggtt->vm.clear_range = nop_clear_range;
-	if (!USES_FULL_PPGTT(dev_priv) || intel_scanout_needs_vtd_wa(dev_priv))
+	if (intel_scanout_needs_vtd_wa(dev_priv))
 		ggtt->vm.clear_range = gen8_ggtt_clear_range;
 
 	ggtt->vm.insert_entries = gen8_ggtt_insert_entries;
@@ -3609,7 +3535,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
 	/* Only VLV supports read-only GGTT mappings */
 	ggtt->vm.has_read_only = IS_VALLEYVIEW(dev_priv);
 
-	if (!HAS_LLC(dev_priv) && !USES_PPGTT(dev_priv))
+	if (!HAS_LLC(dev_priv) && !HAS_PPGTT(dev_priv))
 		ggtt->vm.mm.color_adjust = i915_gtt_color_adjust;
 	mutex_unlock(&dev_priv->drm.struct_mutex);
 
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 2835cacd0d08..3d5554f14dfd 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -474,7 +474,7 @@ static void error_print_engine(struct drm_i915_error_state_buf *m,
 			err_printf(m, "  SYNC_2: 0x%08x\n",
 				   ee->semaphore_mboxes[2]);
 	}
-	if (USES_PPGTT(m->i915)) {
+	if (HAS_PPGTT(m->i915)) {
 		err_printf(m, "  GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
 
 		if (INTEL_GEN(m->i915) >= 8) {
@@ -1230,7 +1230,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
 	ee->reset_count = i915_reset_engine_count(&dev_priv->gpu_error,
 						  engine);
 
-	if (USES_PPGTT(dev_priv)) {
+	if (HAS_PPGTT(dev_priv)) {
 		int i;
 
 		ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 295e981e4a39..bd6bd8879cab 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -82,10 +82,6 @@ i915_param_named_unsafe(enable_hangcheck, bool, 0644,
 	"WARNING: Disabling this can cause system wide hangs. "
 	"(default: true)");
 
-i915_param_named_unsafe(enable_ppgtt, int, 0400,
-	"Override PPGTT usage. "
-	"(-1=auto [default], 0=disabled, 1=aliasing, 2=full, 3=full with extended address space)");
-
 i915_param_named_unsafe(enable_psr, int, 0600,
 	"Enable PSR "
 	"(0=disabled, 1=enabled) "
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 6c4d4a21474b..7e56c516c815 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -41,7 +41,6 @@ struct drm_printer;
 	param(int, vbt_sdvo_panel_type, -1) \
 	param(int, enable_dc, -1) \
 	param(int, enable_fbc, -1) \
-	param(int, enable_ppgtt, -1) \
 	param(int, enable_psr, -1) \
 	param(int, disable_power_well, -1) \
 	param(int, enable_ips, 1) \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d6f7b9fe1d26..eeec902896b9 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -252,7 +252,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
 	.has_llc = 1, \
 	.has_rc6 = 1, \
 	.has_rc6p = 1, \
-	.has_aliasing_ppgtt = 1, \
+	.ppgtt = INTEL_PPGTT_ALIASING, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
 	CURSOR_OFFSETS
@@ -297,8 +297,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
 	.has_llc = 1, \
 	.has_rc6 = 1, \
 	.has_rc6p = 1, \
-	.has_aliasing_ppgtt = 1, \
-	.has_full_ppgtt = 1, \
+	.ppgtt = INTEL_PPGTT_FULL, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
 	IVB_CURSOR_OFFSETS
@@ -351,8 +350,7 @@ static const struct intel_device_info intel_valleyview_info = {
 	.has_rc6 = 1,
 	.has_gmch_display = 1,
 	.has_hotplug = 1,
-	.has_aliasing_ppgtt = 1,
-	.has_full_ppgtt = 1,
+	.ppgtt = INTEL_PPGTT_FULL,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
@@ -399,7 +397,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
 	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
 		      I915_GTT_PAGE_SIZE_2M, \
 	.has_logical_ring_contexts = 1, \
-	.has_full_48bit_ppgtt = 1, \
+	.ppgtt = INTEL_PPGTT_FULL_4LVL, \
 	.has_64bit_reloc = 1, \
 	.has_reset_engine = 1
 
@@ -443,8 +441,7 @@ static const struct intel_device_info intel_cherryview_info = {
 	.has_rc6 = 1,
 	.has_logical_ring_contexts = 1,
 	.has_gmch_display = 1,
-	.has_aliasing_ppgtt = 1,
-	.has_full_ppgtt = 1,
+	.ppgtt = INTEL_PPGTT_FULL,
 	.has_reset_engine = 1,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
@@ -518,9 +515,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
 	.has_logical_ring_contexts = 1, \
 	.has_logical_ring_preemption = 1, \
 	.has_guc = 1, \
-	.has_aliasing_ppgtt = 1, \
-	.has_full_ppgtt = 1, \
-	.has_full_48bit_ppgtt = 1, \
+	.ppgtt = INTEL_PPGTT_FULL_4LVL, \
 	.has_reset_engine = 1, \
 	.has_snoop = true, \
 	.has_coherent_ggtt = false, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 31f6be774833..268c8f286cc0 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -26,6 +26,7 @@
 
 #include "intel_device_info.h"
 #include "i915_drv.h"
+#include "i915_vgpu.h"
 
 #define PLATFORM_NAME(x) [INTEL_##x] = #x
 static const char * const platform_names[] = {
@@ -850,6 +851,11 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
 	else if (INTEL_GEN(dev_priv) >= 11)
 		gen11_sseu_info_init(dev_priv);
 
+	if (IS_GEN6(dev_priv) && intel_vtd_active()) {
+		DRM_INFO("Disabling ppGTT for VT-d support\n");
+		info->ppgtt = INTEL_PPGTT_NONE;
+	}
+
 	/* Initialize command stream timestamp frequency */
 	info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
 }
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 6eecd64734d5..af7002640cdf 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -25,6 +25,8 @@
 #ifndef _INTEL_DEVICE_INFO_H_
 #define _INTEL_DEVICE_INFO_H_
 
+#include <uapi/drm/i915_drm.h>
+
 #include "intel_display.h"
 
 struct drm_printer;
@@ -74,21 +76,25 @@ enum intel_platform {
 	INTEL_MAX_PLATFORMS
 };
 
+enum intel_ppgtt {
+	INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
+	INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
+	INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
+	INTEL_PPGTT_FULL_4LVL,
+};
+
 #define DEV_INFO_FOR_EACH_FLAG(func) \
 	func(is_mobile); \
 	func(is_lp); \
 	func(is_alpha_support); \
 	/* Keep has_* in alphabetical order */ \
 	func(has_64bit_reloc); \
-	func(has_aliasing_ppgtt); \
 	func(has_csr); \
 	func(has_ddi); \
 	func(has_dp_mst); \
 	func(has_reset_engine); \
 	func(has_fbc); \
 	func(has_fpga_dbg); \
-	func(has_full_ppgtt); \
-	func(has_full_48bit_ppgtt); \
 	func(has_gmch_display); \
 	func(has_guc); \
 	func(has_guc_ct); \
@@ -154,6 +160,7 @@ struct intel_device_info {
 	enum intel_platform platform;
 	u32 platform_mask;
 
+	enum intel_ppgtt ppgtt;
 	unsigned int page_sizes; /* page sizes supported by the HW */
 
 	u32 display_mmio_offset;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 4b28225320ff..3836a8a3761a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -418,9 +418,8 @@ execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
 
 static u64 execlists_update_context(struct i915_request *rq)
 {
+	struct i915_hw_ppgtt *ppgtt = rq->gem_context->ppgtt;
 	struct intel_context *ce = rq->hw_context;
-	struct i915_hw_ppgtt *ppgtt =
-		rq->gem_context->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
 	u32 *reg_state = ce->lrc_reg_state;
 
 	reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail);
@@ -1376,7 +1375,7 @@ execlists_context_pin(struct intel_engine_cs *engine,
 	struct intel_context *ce = to_intel_context(ctx, engine);
 
 	lockdep_assert_held(&ctx->i915->drm.struct_mutex);
-	GEM_BUG_ON(!(ctx->ppgtt ?: ctx->i915->mm.aliasing_ppgtt));
+	GEM_BUG_ON(!ctx->ppgtt);
 
 	if (likely(ce->pin_count++))
 		return ce;
@@ -2031,8 +2030,7 @@ static int gen8_emit_bb_start(struct i915_request *rq,
 	 * it is unsafe in case of lite-restore (because the ctx is
 	 * not idle). PML4 is allocated during ppgtt init so this is
 	 * not needed in 48-bit.*/
-	if (rq->gem_context->ppgtt &&
-	    (intel_engine_flag(rq->engine) & rq->gem_context->ppgtt->pd_dirty_rings) &&
+	if ((intel_engine_flag(rq->engine) & rq->gem_context->ppgtt->pd_dirty_rings) &&
 	    !i915_vm_is_48bit(&rq->gem_context->ppgtt->vm) &&
 	    !intel_vgpu_active(rq->i915)) {
 		ret = intel_logical_ring_emit_pdps(rq);
@@ -2634,7 +2632,6 @@ static void execlists_init_reg_state(u32 *regs,
 				     struct intel_ring *ring)
 {
 	struct drm_i915_private *dev_priv = engine->i915;
-	struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: dev_priv->mm.aliasing_ppgtt;
 	u32 base = engine->mmio_base;
 	bool rcs = engine->class == RENDER_CLASS;
 
@@ -2706,12 +2703,12 @@ static void execlists_init_reg_state(u32 *regs,
 	CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
 	CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
 
-	if (i915_vm_is_48bit(&ppgtt->vm)) {
+	if (i915_vm_is_48bit(&ctx->ppgtt->vm)) {
 		/* 64b PPGTT (48bit canonical)
 		 * PDP0_DESCRIPTOR contains the base address to PML4 and
 		 * other PDP Descriptors are ignored.
 		 */
-		ASSIGN_CTX_PML4(ppgtt, regs);
+		ASSIGN_CTX_PML4(ctx->ppgtt, regs);
 	}
 
 	if (rcs) {
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 8d03f64eabd7..09ea65a29d98 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1436,7 +1436,7 @@ static int igt_ppgtt_pin_update(void *arg)
 	 * huge-gtt-pages.
 	 */
 
-	if (!USES_FULL_48BIT_PPGTT(dev_priv)) {
+	if (!HAS_FULL_48BIT_PPGTT(dev_priv)) {
 		pr_info("48b PPGTT not supported, skipping\n");
 		return 0;
 	}
@@ -1687,10 +1687,9 @@ int i915_gem_huge_page_mock_selftests(void)
 		SUBTEST(igt_mock_ppgtt_huge_fill),
 		SUBTEST(igt_mock_ppgtt_64K),
 	};
-	int saved_ppgtt = i915_modparams.enable_ppgtt;
 	struct drm_i915_private *dev_priv;
-	struct pci_dev *pdev;
 	struct i915_hw_ppgtt *ppgtt;
+	struct pci_dev *pdev;
 	int err;
 
 	dev_priv = mock_gem_device();
@@ -1698,7 +1697,7 @@ int i915_gem_huge_page_mock_selftests(void)
 		return -ENOMEM;
 
 	/* Pretend to be a device which supports the 48b PPGTT */
-	i915_modparams.enable_ppgtt = 3;
+	mkwrite_device_info(dev_priv)->ppgtt = INTEL_PPGTT_FULL_4LVL;
 
 	pdev = dev_priv->drm.pdev;
 	dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(39));
@@ -1731,9 +1730,6 @@ int i915_gem_huge_page_mock_selftests(void)
 
 out_unlock:
 	mutex_unlock(&dev_priv->drm.struct_mutex);
-
-	i915_modparams.enable_ppgtt = saved_ppgtt;
-
 	drm_dev_put(&dev_priv->drm);
 
 	return err;
@@ -1753,7 +1749,7 @@ int i915_gem_huge_page_live_selftests(struct drm_i915_private *dev_priv)
 	struct i915_gem_context *ctx;
 	int err;
 
-	if (!USES_PPGTT(dev_priv)) {
+	if (!HAS_PPGTT(dev_priv)) {
 		pr_info("PPGTT not supported, skipping live-selftests\n");
 		return 0;
 	}
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
index 76df25aa90c9..913c0f83f86a 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
@@ -535,7 +535,6 @@ static int igt_ctx_exec(void *arg)
 	IGT_TIMEOUT(end_time);
 	LIST_HEAD(objects);
 	unsigned long ncontexts, ndwords, dw;
-	bool first_shared_gtt = true;
 	int err = -ENODEV;
 
 	/*
@@ -561,12 +560,7 @@ static int igt_ctx_exec(void *arg)
 		struct i915_gem_context *ctx;
 		unsigned int id;
 
-		if (first_shared_gtt) {
-			ctx = __create_hw_context(i915, file->driver_priv);
-			first_shared_gtt = false;
-		} else {
-			ctx = i915_gem_create_context(i915, file->driver_priv);
-		}
+		ctx = i915_gem_create_context(i915, file->driver_priv);
 		if (IS_ERR(ctx)) {
 			err = PTR_ERR(ctx);
 			goto out_unlock;
@@ -865,33 +859,6 @@ static int igt_switch_to_kernel_context(void *arg)
 	return err;
 }
 
-static int fake_aliasing_ppgtt_enable(struct drm_i915_private *i915)
-{
-	struct drm_i915_gem_object *obj;
-	int err;
-
-	err = i915_gem_init_aliasing_ppgtt(i915);
-	if (err)
-		return err;
-
-	list_for_each_entry(obj, &i915->mm.bound_list, mm.link) {
-		struct i915_vma *vma;
-
-		vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
-		if (IS_ERR(vma))
-			continue;
-
-		vma->flags &= ~I915_VMA_LOCAL_BIND;
-	}
-
-	return 0;
-}
-
-static void fake_aliasing_ppgtt_disable(struct drm_i915_private *i915)
-{
-	i915_gem_fini_aliasing_ppgtt(i915);
-}
-
 int i915_gem_context_mock_selftests(void)
 {
 	static const struct i915_subtest tests[] = {
@@ -918,31 +885,9 @@ int i915_gem_context_live_selftests(struct drm_i915_private *dev_priv)
 		SUBTEST(igt_ctx_exec),
 		SUBTEST(igt_ctx_readonly),
 	};
-	bool fake_alias = false;
-	int err;
 
 	if (i915_terminally_wedged(&dev_priv->gpu_error))
 		return 0;
 
-	/* Install a fake aliasing gtt for exercise */
-	if (USES_PPGTT(dev_priv) && !dev_priv->mm.aliasing_ppgtt) {
-		mutex_lock(&dev_priv->drm.struct_mutex);
-		err = fake_aliasing_ppgtt_enable(dev_priv);
-		mutex_unlock(&dev_priv->drm.struct_mutex);
-		if (err)
-			return err;
-
-		GEM_BUG_ON(!dev_priv->mm.aliasing_ppgtt);
-		fake_alias = true;
-	}
-
-	err = i915_subtests(tests, dev_priv);
-
-	if (fake_alias) {
-		mutex_lock(&dev_priv->drm.struct_mutex);
-		fake_aliasing_ppgtt_disable(dev_priv);
-		mutex_unlock(&dev_priv->drm.struct_mutex);
-	}
-
-	return err;
+	return i915_subtests(tests, dev_priv);
 }
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
index 128ad1cf0647..4365979d8222 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
@@ -351,7 +351,7 @@ static int igt_evict_contexts(void *arg)
 	 * where the GTT space of the request is separate from the GGTT
 	 * allocation required to build the request.
 	 */
-	if (!USES_FULL_PPGTT(i915))
+	if (!HAS_FULL_PPGTT(i915))
 		return 0;
 
 	mutex_lock(&i915->drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 8e2e269db97e..17b5aaaa7a50 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -153,7 +153,7 @@ static int igt_ppgtt_alloc(void *arg)
 
 	/* Allocate a ppggt and try to fill the entire range */
 
-	if (!USES_PPGTT(dev_priv))
+	if (!HAS_PPGTT(dev_priv))
 		return 0;
 
 	ppgtt = __hw_ppgtt_create(dev_priv);
@@ -1001,7 +1001,7 @@ static int exercise_ppgtt(struct drm_i915_private *dev_priv,
 	IGT_TIMEOUT(end_time);
 	int err;
 
-	if (!USES_FULL_PPGTT(dev_priv))
+	if (!HAS_FULL_PPGTT(dev_priv))
 		return 0;
 
 	file = mock_file(dev_priv);
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index a4446f452040..298b2e197744 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -412,6 +412,14 @@ typedef struct drm_i915_irq_wait {
 	int irq_seq;
 } drm_i915_irq_wait_t;
 
+/*
+ * Different modes of per-process Graphics Translation Table,
+ * see I915_PARAM_HAS_ALIASING_PPGTT
+ */
+#define I915_GEM_PPGTT_NONE	0
+#define I915_GEM_PPGTT_ALIASING	1
+#define I915_GEM_PPGTT_FULL	2
+
 /* Ioctl to query kernel params:
  */
 #define I915_PARAM_IRQ_ACTIVE            1
-- 
2.19.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 24+ messages in thread
* ✗ Fi.CI.SPARSE: warning for drm/i915: Remove i915.enable_ppgtt override (rev2)
  2018-09-25 11:48 [PATCH v4] drm/i915: Remove i915.enable_ppgtt override Chris Wilson
                   ` (5 preceding siblings ...)
  2018-09-26 20:12 ` [PATCH v5] " Chris Wilson
@ 2018-09-26 21:34 ` Patchwork
  2018-09-26 21:55 ` ✓ Fi.CI.BAT: success " Patchwork
  2018-09-27  3:00 ` ✓ Fi.CI.IGT: " Patchwork
  8 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2018-09-26 21:34 UTC (permalink / raw)
  To: Chris Wilson; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Remove i915.enable_ppgtt override (rev2)
URL   : https://patchwork.freedesktop.org/series/50143/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915: Remove i915.enable_ppgtt override
+drivers/gpu/drm/i915/i915_drv.c:348:25: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_gem_gtt.c:348:14: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_gem_gtt.c:348:14: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/i915_gem_gtt.c:348:14: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/i915_gem_gtt.c:348:14: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3718:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3720:16: warning: expression using sizeof(void)

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Remove i915.enable_ppgtt override (rev2)
  2018-09-25 11:48 [PATCH v4] drm/i915: Remove i915.enable_ppgtt override Chris Wilson
                   ` (6 preceding siblings ...)
  2018-09-26 21:34 ` ✗ Fi.CI.SPARSE: warning for drm/i915: Remove i915.enable_ppgtt override (rev2) Patchwork
@ 2018-09-26 21:55 ` Patchwork
  2018-09-27  3:00 ` ✓ Fi.CI.IGT: " Patchwork
  8 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2018-09-26 21:55 UTC (permalink / raw)
  To: Chris Wilson; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Remove i915.enable_ppgtt override (rev2)
URL   : https://patchwork.freedesktop.org/series/50143/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4885 -> Patchwork_10288 =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_10288 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10288, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/50143/revisions/2/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10288:

  === IGT changes ===

    ==== Warnings ====

    igt@pm_rpm@module-reload:
      fi-hsw-4770r:       SKIP -> PASS

    
== Known issues ==

  Here are the changes found in Patchwork_10288 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@debugfs_test@read_all_entries:
      fi-icl-u:           PASS -> DMESG-WARN (fdo#108070, fdo#107724)

    igt@drv_hangman@error-state-basic:
      fi-icl-u:           PASS -> DMESG-WARN (fdo#107724)

    igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
      fi-byt-clapper:     PASS -> FAIL (fdo#103191, fdo#107362)

    igt@kms_psr@primary_page_flip:
      fi-kbl-7560u:       PASS -> FAIL (fdo#107336)

    igt@pm_rpm@basic-pci-d3-state:
      fi-glk-j4005:       PASS -> DMESG-WARN (fdo#106097)

    
    ==== Possible fixes ====

    igt@drv_module_reload@basic-reload:
      fi-glk-j4005:       DMESG-WARN (fdo#106725, fdo#106248) -> PASS

    igt@drv_module_reload@basic-reload-inject:
      fi-hsw-4770r:       DMESG-WARN (fdo#107924, fdo#107425) -> PASS

    igt@kms_flip@basic-flip-vs-wf_vblank:
      fi-glk-j4005:       FAIL (fdo#100368) -> PASS

    igt@kms_psr@primary_page_flip:
      fi-whl-u:           FAIL (fdo#107336) -> PASS

    
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097
  fdo#106248 https://bugs.freedesktop.org/show_bug.cgi?id=106248
  fdo#106725 https://bugs.freedesktop.org/show_bug.cgi?id=106725
  fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107425 https://bugs.freedesktop.org/show_bug.cgi?id=107425
  fdo#107724 https://bugs.freedesktop.org/show_bug.cgi?id=107724
  fdo#107924 https://bugs.freedesktop.org/show_bug.cgi?id=107924
  fdo#108070 https://bugs.freedesktop.org/show_bug.cgi?id=108070


== Participating hosts (46 -> 40) ==

  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-u2 fi-skl-6700hq 


== Build changes ==

    * Linux: CI_DRM_4885 -> Patchwork_10288

  CI_DRM_4885: c4571c393173c2eafd308bcad5f22b2e6a99b5ad @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4651: 63baa2f9e9483e01b378b943fac5b99976c5e485 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10288: 88527510b5bfaaeab5950394310ed448600eb3c4 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

88527510b5bf drm/i915: Remove i915.enable_ppgtt override

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10288/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915: Remove i915.enable_ppgtt override (rev2)
  2018-09-25 11:48 [PATCH v4] drm/i915: Remove i915.enable_ppgtt override Chris Wilson
                   ` (7 preceding siblings ...)
  2018-09-26 21:55 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-09-27  3:00 ` Patchwork
  8 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2018-09-27  3:00 UTC (permalink / raw)
  To: Chris Wilson; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Remove i915.enable_ppgtt override (rev2)
URL   : https://patchwork.freedesktop.org/series/50143/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4885_full -> Patchwork_10288_full =

== Summary - SUCCESS ==

  No regressions found.

  

== Known issues ==

  Here are the changes found in Patchwork_10288_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_exec_params@sol-reset-invalid:
      shard-snb:          SKIP -> INCOMPLETE (fdo#105411)

    igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy:
      shard-hsw:          PASS -> FAIL (fdo#105767)

    igt@kms_fbcon_fbt@fbc-suspend:
      shard-apl:          PASS -> INCOMPLETE (fdo#103927)

    igt@kms_flip@flip-vs-expired-vblank-interruptible:
      shard-glk:          PASS -> FAIL (fdo#102887, fdo#105363)

    
    ==== Possible fixes ====

    igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
      shard-kbl:          DMESG-WARN (fdo#107956) -> PASS

    igt@kms_setmode@basic:
      shard-kbl:          FAIL (fdo#99912) -> PASS

    
    ==== Warnings ====

    igt@gem_workarounds@suspend-resume-fd:
      shard-apl:          FAIL (fdo#103375) -> INCOMPLETE (fdo#103927)

    
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
  fdo#105767 https://bugs.freedesktop.org/show_bug.cgi?id=105767
  fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (6 -> 5) ==

  Missing    (1): shard-skl 


== Build changes ==

    * Linux: CI_DRM_4885 -> Patchwork_10288

  CI_DRM_4885: c4571c393173c2eafd308bcad5f22b2e6a99b5ad @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4651: 63baa2f9e9483e01b378b943fac5b99976c5e485 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10288: 88527510b5bfaaeab5950394310ed448600eb3c4 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10288/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v5] drm/i915: Remove i915.enable_ppgtt override
  2018-09-26 20:12 ` [PATCH v5] " Chris Wilson
@ 2018-09-27  8:20   ` Joonas Lahtinen
  2018-09-27  8:55     ` Chris Wilson
  0 siblings, 1 reply; 24+ messages in thread
From: Joonas Lahtinen @ 2018-09-27  8:20 UTC (permalink / raw)
  To: Chris Wilson, intel-gfx, Jani Nikula; +Cc: Matthew Auld

Quoting Chris Wilson (2018-09-26 23:12:22)
> Now that we are confident in providing full-ppgtt where supported,
> remove the ability to override the context isolation.
> 
> v2: Remove faked aliasing-ppgtt for testing as it no longer is accepted.
> v3: s/USES/HAS/ to match usage and reject attempts to load the module on
> old GVT-g setups that do not provide support for full-ppgtt.
> v4: Insulate ABI ppGTT values from our internal enum (later plans
> involve moving ppGTT depth out of the enum, thus potentially breaking
> ABI unless we document the current values).
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> #v3

+ Jani for awareness when handling dinq, this solidifies existing uAPI
And drops the reporting of 48-bit ppGTT through this getparam as we
already have context specific I915_CONTEXT_PARAM_GTT_SIZE for that and
no known abusers for the unintended reporting outside 0,1,2 set.

Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

Regards, Joonas

> Acked-by: Zhi Wang <zhi.a.wang@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.c               | 22 +++--
>  drivers/gpu/drm/i915/i915_drv.h               | 14 +--
>  drivers/gpu/drm/i915/i915_gem_context.c       |  2 +-
>  drivers/gpu/drm/i915/i915_gem_gtt.c           | 88 ++-----------------
>  drivers/gpu/drm/i915/i915_gpu_error.c         |  4 +-
>  drivers/gpu/drm/i915/i915_params.c            |  4 -
>  drivers/gpu/drm/i915/i915_params.h            |  1 -
>  drivers/gpu/drm/i915/i915_pci.c               | 17 ++--
>  drivers/gpu/drm/i915/intel_device_info.c      |  6 ++
>  drivers/gpu/drm/i915/intel_device_info.h      | 13 ++-
>  drivers/gpu/drm/i915/intel_lrc.c              | 13 ++-
>  drivers/gpu/drm/i915/selftests/huge_pages.c   | 12 +--
>  .../gpu/drm/i915/selftests/i915_gem_context.c | 59 +------------
>  .../gpu/drm/i915/selftests/i915_gem_evict.c   |  2 +-
>  drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |  4 +-
>  include/uapi/drm/i915_drm.h                   |  8 ++
>  16 files changed, 72 insertions(+), 197 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index ade9bca250fa..1b028f429e92 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -345,7 +345,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
>                 value = HAS_WT(dev_priv);
>                 break;
>         case I915_PARAM_HAS_ALIASING_PPGTT:
> -               value = USES_PPGTT(dev_priv);
> +               value = min_t(int, INTEL_PPGTT(dev_priv), I915_GEM_PPGTT_FULL);
>                 break;
>         case I915_PARAM_HAS_SEMAPHORES:
>                 value = HAS_LEGACY_SEMAPHORES(dev_priv);
> @@ -1049,17 +1049,6 @@ static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
>  
>  static void intel_sanitize_options(struct drm_i915_private *dev_priv)
>  {
> -       /*
> -        * i915.enable_ppgtt is read-only, so do an early pass to validate the
> -        * user's requested state against the hardware/driver capabilities.  We
> -        * do this now so that we can print out any log messages once rather
> -        * than every time we check intel_enable_ppgtt().
> -        */
> -       i915_modparams.enable_ppgtt =
> -               intel_sanitize_enable_ppgtt(dev_priv,
> -                                           i915_modparams.enable_ppgtt);
> -       DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
> -
>         intel_gvt_sanitize_options(dev_priv);
>  }
>  
> @@ -1374,6 +1363,15 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
>  
>         intel_device_info_runtime_init(mkwrite_device_info(dev_priv));
>  
> +       if (HAS_PPGTT(dev_priv)) {
> +               if (intel_vgpu_active(dev_priv) &&
> +                   !intel_vgpu_has_full_48bit_ppgtt(dev_priv)) {
> +                       i915_report_error(dev_priv,
> +                                         "incompatible vGPU found, support for isolated ppGTT required\n");
> +                       return -ENXIO;
> +               }
> +       }
> +
>         intel_sanitize_options(dev_priv);
>  
>         i915_perf_init(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8624b4bdc242..f28b3c2a3cd2 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2593,9 +2593,14 @@ intel_info(const struct drm_i915_private *dev_priv)
>  
>  #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
>  
> -#define USES_PPGTT(dev_priv)           (i915_modparams.enable_ppgtt)
> -#define USES_FULL_PPGTT(dev_priv)      (i915_modparams.enable_ppgtt >= 2)
> -#define USES_FULL_48BIT_PPGTT(dev_priv)        (i915_modparams.enable_ppgtt == 3)
> +#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt)
> +#define HAS_PPGTT(dev_priv) \
> +       (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
> +#define HAS_FULL_PPGTT(dev_priv) \
> +       (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
> +#define HAS_FULL_48BIT_PPGTT(dev_priv) \
> +       (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL_4LVL)
> +
>  #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
>         GEM_BUG_ON((sizes) == 0); \
>         ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
> @@ -2743,9 +2748,6 @@ intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
>         return IS_BROXTON(dev_priv) && intel_vtd_active();
>  }
>  
> -int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
> -                               int enable_ppgtt);
> -
>  /* i915_drv.c */
>  void __printf(3, 4)
>  __i915_printk(struct drm_i915_private *dev_priv, const char *level,
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index f772593b99ab..15c92f75b1b8 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -414,7 +414,7 @@ i915_gem_create_context(struct drm_i915_private *dev_priv,
>         if (IS_ERR(ctx))
>                 return ctx;
>  
> -       if (USES_FULL_PPGTT(dev_priv)) {
> +       if (HAS_FULL_PPGTT(dev_priv)) {
>                 struct i915_hw_ppgtt *ppgtt;
>  
>                 ppgtt = i915_ppgtt_create(dev_priv, file_priv);
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index f6c7ab413081..c9363504949f 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -133,55 +133,6 @@ static inline void i915_ggtt_invalidate(struct drm_i915_private *i915)
>         i915->ggtt.invalidate(i915);
>  }
>  
> -int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
> -                               int enable_ppgtt)
> -{
> -       bool has_full_ppgtt;
> -       bool has_full_48bit_ppgtt;
> -
> -       if (!dev_priv->info.has_aliasing_ppgtt)
> -               return 0;
> -
> -       has_full_ppgtt = dev_priv->info.has_full_ppgtt;
> -       has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt;
> -
> -       if (intel_vgpu_active(dev_priv)) {
> -               /* GVT-g has no support for 32bit ppgtt */
> -               has_full_ppgtt = false;
> -               has_full_48bit_ppgtt = intel_vgpu_has_full_48bit_ppgtt(dev_priv);
> -       }
> -
> -       /*
> -        * We don't allow disabling PPGTT for gen8+ as it's a requirement for
> -        * execlists, the sole mechanism available to submit work.
> -        */
> -       if (enable_ppgtt == 0 && !HAS_EXECLISTS(dev_priv))
> -               return 0;
> -
> -       if (enable_ppgtt == 1)
> -               return 1;
> -
> -       if (enable_ppgtt == 2 && has_full_ppgtt)
> -               return 2;
> -
> -       if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
> -               return 3;
> -
> -       /* Disable ppgtt on SNB if VT-d is on. */
> -       if (IS_GEN6(dev_priv) && intel_vtd_active()) {
> -               DRM_INFO("Disabling PPGTT because VT-d is on\n");
> -               return 0;
> -       }
> -
> -       if (has_full_48bit_ppgtt)
> -               return 3;
> -
> -       if (has_full_ppgtt)
> -               return 2;
> -
> -       return 1;
> -}
> -
>  static int ppgtt_bind_vma(struct i915_vma *vma,
>                           enum i915_cache_level cache_level,
>                           u32 unused)
> @@ -1647,7 +1598,7 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
>         ppgtt->vm.i915 = i915;
>         ppgtt->vm.dma = &i915->drm.pdev->dev;
>  
> -       ppgtt->vm.total = USES_FULL_48BIT_PPGTT(i915) ?
> +       ppgtt->vm.total = HAS_FULL_48BIT_PPGTT(i915) ?
>                 1ULL << 48 :
>                 1ULL << 32;
>  
> @@ -1782,19 +1733,6 @@ static inline void gen6_write_pde(const struct gen6_hw_ppgtt *ppgtt,
>                   ppgtt->pd_addr + pde);
>  }
>  
> -static void gen8_ppgtt_enable(struct drm_i915_private *dev_priv)
> -{
> -       struct intel_engine_cs *engine;
> -       enum intel_engine_id id;
> -
> -       for_each_engine(engine, dev_priv, id) {
> -               u32 four_level = USES_FULL_48BIT_PPGTT(dev_priv) ?
> -                                GEN8_GFX_PPGTT_48B : 0;
> -               I915_WRITE(RING_MODE_GEN7(engine),
> -                          _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
> -       }
> -}
> -
>  static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv)
>  {
>         struct intel_engine_cs *engine;
> @@ -1834,7 +1772,8 @@ static void gen6_ppgtt_enable(struct drm_i915_private *dev_priv)
>         ecochk = I915_READ(GAM_ECOCHK);
>         I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
>  
> -       I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
> +       if (HAS_PPGTT(dev_priv)) /* may be disabled for VT-d */
> +               I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
>  }
>  
>  /* PPGTT support for Sandybdrige/Gen6 and later */
> @@ -2237,23 +2176,10 @@ int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv)
>  {
>         gtt_write_workarounds(dev_priv);
>  
> -       /* In the case of execlists, PPGTT is enabled by the context descriptor
> -        * and the PDPs are contained within the context itself.  We don't
> -        * need to do anything here. */
> -       if (HAS_LOGICAL_RING_CONTEXTS(dev_priv))
> -               return 0;
> -
> -       if (!USES_PPGTT(dev_priv))
> -               return 0;
> -
>         if (IS_GEN6(dev_priv))
>                 gen6_ppgtt_enable(dev_priv);
>         else if (IS_GEN7(dev_priv))
>                 gen7_ppgtt_enable(dev_priv);
> -       else if (INTEL_GEN(dev_priv) >= 8)
> -               gen8_ppgtt_enable(dev_priv);
> -       else
> -               MISSING_CASE(INTEL_GEN(dev_priv));
>  
>         return 0;
>  }
> @@ -2952,7 +2878,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
>         /* And finally clear the reserved guard page */
>         ggtt->vm.clear_range(&ggtt->vm, ggtt->vm.total - PAGE_SIZE, PAGE_SIZE);
>  
> -       if (USES_PPGTT(dev_priv) && !USES_FULL_PPGTT(dev_priv)) {
> +       if (INTEL_PPGTT(dev_priv) == INTEL_PPGTT_ALIASING) {
>                 ret = i915_gem_init_aliasing_ppgtt(dev_priv);
>                 if (ret)
>                         goto err;
> @@ -3275,7 +3201,7 @@ static void bdw_setup_private_ppat(struct intel_ppat *ppat)
>         ppat->match = bdw_private_pat_match;
>         ppat->clear_value = GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3);
>  
> -       if (!USES_PPGTT(ppat->i915)) {
> +       if (!HAS_PPGTT(ppat->i915)) {
>                 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
>                  * so RTL will always use the value corresponding to
>                  * pat_sel = 000".
> @@ -3402,7 +3328,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
>         ggtt->vm.cleanup = gen6_gmch_remove;
>         ggtt->vm.insert_page = gen8_ggtt_insert_page;
>         ggtt->vm.clear_range = nop_clear_range;
> -       if (!USES_FULL_PPGTT(dev_priv) || intel_scanout_needs_vtd_wa(dev_priv))
> +       if (intel_scanout_needs_vtd_wa(dev_priv))
>                 ggtt->vm.clear_range = gen8_ggtt_clear_range;
>  
>         ggtt->vm.insert_entries = gen8_ggtt_insert_entries;
> @@ -3609,7 +3535,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
>         /* Only VLV supports read-only GGTT mappings */
>         ggtt->vm.has_read_only = IS_VALLEYVIEW(dev_priv);
>  
> -       if (!HAS_LLC(dev_priv) && !USES_PPGTT(dev_priv))
> +       if (!HAS_LLC(dev_priv) && !HAS_PPGTT(dev_priv))
>                 ggtt->vm.mm.color_adjust = i915_gtt_color_adjust;
>         mutex_unlock(&dev_priv->drm.struct_mutex);
>  
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 2835cacd0d08..3d5554f14dfd 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -474,7 +474,7 @@ static void error_print_engine(struct drm_i915_error_state_buf *m,
>                         err_printf(m, "  SYNC_2: 0x%08x\n",
>                                    ee->semaphore_mboxes[2]);
>         }
> -       if (USES_PPGTT(m->i915)) {
> +       if (HAS_PPGTT(m->i915)) {
>                 err_printf(m, "  GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
>  
>                 if (INTEL_GEN(m->i915) >= 8) {
> @@ -1230,7 +1230,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
>         ee->reset_count = i915_reset_engine_count(&dev_priv->gpu_error,
>                                                   engine);
>  
> -       if (USES_PPGTT(dev_priv)) {
> +       if (HAS_PPGTT(dev_priv)) {
>                 int i;
>  
>                 ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
> diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
> index 295e981e4a39..bd6bd8879cab 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -82,10 +82,6 @@ i915_param_named_unsafe(enable_hangcheck, bool, 0644,
>         "WARNING: Disabling this can cause system wide hangs. "
>         "(default: true)");
>  
> -i915_param_named_unsafe(enable_ppgtt, int, 0400,
> -       "Override PPGTT usage. "
> -       "(-1=auto [default], 0=disabled, 1=aliasing, 2=full, 3=full with extended address space)");
> -
>  i915_param_named_unsafe(enable_psr, int, 0600,
>         "Enable PSR "
>         "(0=disabled, 1=enabled) "
> diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
> index 6c4d4a21474b..7e56c516c815 100644
> --- a/drivers/gpu/drm/i915/i915_params.h
> +++ b/drivers/gpu/drm/i915/i915_params.h
> @@ -41,7 +41,6 @@ struct drm_printer;
>         param(int, vbt_sdvo_panel_type, -1) \
>         param(int, enable_dc, -1) \
>         param(int, enable_fbc, -1) \
> -       param(int, enable_ppgtt, -1) \
>         param(int, enable_psr, -1) \
>         param(int, disable_power_well, -1) \
>         param(int, enable_ips, 1) \
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index d6f7b9fe1d26..eeec902896b9 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -252,7 +252,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
>         .has_llc = 1, \
>         .has_rc6 = 1, \
>         .has_rc6p = 1, \
> -       .has_aliasing_ppgtt = 1, \
> +       .ppgtt = INTEL_PPGTT_ALIASING, \
>         GEN_DEFAULT_PIPEOFFSETS, \
>         GEN_DEFAULT_PAGE_SIZES, \
>         CURSOR_OFFSETS
> @@ -297,8 +297,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
>         .has_llc = 1, \
>         .has_rc6 = 1, \
>         .has_rc6p = 1, \
> -       .has_aliasing_ppgtt = 1, \
> -       .has_full_ppgtt = 1, \
> +       .ppgtt = INTEL_PPGTT_FULL, \
>         GEN_DEFAULT_PIPEOFFSETS, \
>         GEN_DEFAULT_PAGE_SIZES, \
>         IVB_CURSOR_OFFSETS
> @@ -351,8 +350,7 @@ static const struct intel_device_info intel_valleyview_info = {
>         .has_rc6 = 1,
>         .has_gmch_display = 1,
>         .has_hotplug = 1,
> -       .has_aliasing_ppgtt = 1,
> -       .has_full_ppgtt = 1,
> +       .ppgtt = INTEL_PPGTT_FULL,
>         .has_snoop = true,
>         .has_coherent_ggtt = false,
>         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
> @@ -399,7 +397,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
>         .page_sizes = I915_GTT_PAGE_SIZE_4K | \
>                       I915_GTT_PAGE_SIZE_2M, \
>         .has_logical_ring_contexts = 1, \
> -       .has_full_48bit_ppgtt = 1, \
> +       .ppgtt = INTEL_PPGTT_FULL_4LVL, \
>         .has_64bit_reloc = 1, \
>         .has_reset_engine = 1
>  
> @@ -443,8 +441,7 @@ static const struct intel_device_info intel_cherryview_info = {
>         .has_rc6 = 1,
>         .has_logical_ring_contexts = 1,
>         .has_gmch_display = 1,
> -       .has_aliasing_ppgtt = 1,
> -       .has_full_ppgtt = 1,
> +       .ppgtt = INTEL_PPGTT_FULL,
>         .has_reset_engine = 1,
>         .has_snoop = true,
>         .has_coherent_ggtt = false,
> @@ -518,9 +515,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
>         .has_logical_ring_contexts = 1, \
>         .has_logical_ring_preemption = 1, \
>         .has_guc = 1, \
> -       .has_aliasing_ppgtt = 1, \
> -       .has_full_ppgtt = 1, \
> -       .has_full_48bit_ppgtt = 1, \
> +       .ppgtt = INTEL_PPGTT_FULL_4LVL, \
>         .has_reset_engine = 1, \
>         .has_snoop = true, \
>         .has_coherent_ggtt = false, \
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 31f6be774833..268c8f286cc0 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -26,6 +26,7 @@
>  
>  #include "intel_device_info.h"
>  #include "i915_drv.h"
> +#include "i915_vgpu.h"
>  
>  #define PLATFORM_NAME(x) [INTEL_##x] = #x
>  static const char * const platform_names[] = {
> @@ -850,6 +851,11 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
>         else if (INTEL_GEN(dev_priv) >= 11)
>                 gen11_sseu_info_init(dev_priv);
>  
> +       if (IS_GEN6(dev_priv) && intel_vtd_active()) {
> +               DRM_INFO("Disabling ppGTT for VT-d support\n");
> +               info->ppgtt = INTEL_PPGTT_NONE;
> +       }
> +
>         /* Initialize command stream timestamp frequency */
>         info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
>  }
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 6eecd64734d5..af7002640cdf 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -25,6 +25,8 @@
>  #ifndef _INTEL_DEVICE_INFO_H_
>  #define _INTEL_DEVICE_INFO_H_
>  
> +#include <uapi/drm/i915_drm.h>
> +
>  #include "intel_display.h"
>  
>  struct drm_printer;
> @@ -74,21 +76,25 @@ enum intel_platform {
>         INTEL_MAX_PLATFORMS
>  };
>  
> +enum intel_ppgtt {
> +       INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
> +       INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
> +       INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
> +       INTEL_PPGTT_FULL_4LVL,
> +};
> +
>  #define DEV_INFO_FOR_EACH_FLAG(func) \
>         func(is_mobile); \
>         func(is_lp); \
>         func(is_alpha_support); \
>         /* Keep has_* in alphabetical order */ \
>         func(has_64bit_reloc); \
> -       func(has_aliasing_ppgtt); \
>         func(has_csr); \
>         func(has_ddi); \
>         func(has_dp_mst); \
>         func(has_reset_engine); \
>         func(has_fbc); \
>         func(has_fpga_dbg); \
> -       func(has_full_ppgtt); \
> -       func(has_full_48bit_ppgtt); \
>         func(has_gmch_display); \
>         func(has_guc); \
>         func(has_guc_ct); \
> @@ -154,6 +160,7 @@ struct intel_device_info {
>         enum intel_platform platform;
>         u32 platform_mask;
>  
> +       enum intel_ppgtt ppgtt;
>         unsigned int page_sizes; /* page sizes supported by the HW */
>  
>         u32 display_mmio_offset;
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 4b28225320ff..3836a8a3761a 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -418,9 +418,8 @@ execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
>  
>  static u64 execlists_update_context(struct i915_request *rq)
>  {
> +       struct i915_hw_ppgtt *ppgtt = rq->gem_context->ppgtt;
>         struct intel_context *ce = rq->hw_context;
> -       struct i915_hw_ppgtt *ppgtt =
> -               rq->gem_context->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
>         u32 *reg_state = ce->lrc_reg_state;
>  
>         reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail);
> @@ -1376,7 +1375,7 @@ execlists_context_pin(struct intel_engine_cs *engine,
>         struct intel_context *ce = to_intel_context(ctx, engine);
>  
>         lockdep_assert_held(&ctx->i915->drm.struct_mutex);
> -       GEM_BUG_ON(!(ctx->ppgtt ?: ctx->i915->mm.aliasing_ppgtt));
> +       GEM_BUG_ON(!ctx->ppgtt);
>  
>         if (likely(ce->pin_count++))
>                 return ce;
> @@ -2031,8 +2030,7 @@ static int gen8_emit_bb_start(struct i915_request *rq,
>          * it is unsafe in case of lite-restore (because the ctx is
>          * not idle). PML4 is allocated during ppgtt init so this is
>          * not needed in 48-bit.*/
> -       if (rq->gem_context->ppgtt &&
> -           (intel_engine_flag(rq->engine) & rq->gem_context->ppgtt->pd_dirty_rings) &&
> +       if ((intel_engine_flag(rq->engine) & rq->gem_context->ppgtt->pd_dirty_rings) &&
>             !i915_vm_is_48bit(&rq->gem_context->ppgtt->vm) &&
>             !intel_vgpu_active(rq->i915)) {
>                 ret = intel_logical_ring_emit_pdps(rq);
> @@ -2634,7 +2632,6 @@ static void execlists_init_reg_state(u32 *regs,
>                                      struct intel_ring *ring)
>  {
>         struct drm_i915_private *dev_priv = engine->i915;
> -       struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: dev_priv->mm.aliasing_ppgtt;
>         u32 base = engine->mmio_base;
>         bool rcs = engine->class == RENDER_CLASS;
>  
> @@ -2706,12 +2703,12 @@ static void execlists_init_reg_state(u32 *regs,
>         CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
>         CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
>  
> -       if (i915_vm_is_48bit(&ppgtt->vm)) {
> +       if (i915_vm_is_48bit(&ctx->ppgtt->vm)) {
>                 /* 64b PPGTT (48bit canonical)
>                  * PDP0_DESCRIPTOR contains the base address to PML4 and
>                  * other PDP Descriptors are ignored.
>                  */
> -               ASSIGN_CTX_PML4(ppgtt, regs);
> +               ASSIGN_CTX_PML4(ctx->ppgtt, regs);
>         }
>  
>         if (rcs) {
> diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
> index 8d03f64eabd7..09ea65a29d98 100644
> --- a/drivers/gpu/drm/i915/selftests/huge_pages.c
> +++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
> @@ -1436,7 +1436,7 @@ static int igt_ppgtt_pin_update(void *arg)
>          * huge-gtt-pages.
>          */
>  
> -       if (!USES_FULL_48BIT_PPGTT(dev_priv)) {
> +       if (!HAS_FULL_48BIT_PPGTT(dev_priv)) {
>                 pr_info("48b PPGTT not supported, skipping\n");
>                 return 0;
>         }
> @@ -1687,10 +1687,9 @@ int i915_gem_huge_page_mock_selftests(void)
>                 SUBTEST(igt_mock_ppgtt_huge_fill),
>                 SUBTEST(igt_mock_ppgtt_64K),
>         };
> -       int saved_ppgtt = i915_modparams.enable_ppgtt;
>         struct drm_i915_private *dev_priv;
> -       struct pci_dev *pdev;
>         struct i915_hw_ppgtt *ppgtt;
> +       struct pci_dev *pdev;
>         int err;
>  
>         dev_priv = mock_gem_device();
> @@ -1698,7 +1697,7 @@ int i915_gem_huge_page_mock_selftests(void)
>                 return -ENOMEM;
>  
>         /* Pretend to be a device which supports the 48b PPGTT */
> -       i915_modparams.enable_ppgtt = 3;
> +       mkwrite_device_info(dev_priv)->ppgtt = INTEL_PPGTT_FULL_4LVL;
>  
>         pdev = dev_priv->drm.pdev;
>         dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(39));
> @@ -1731,9 +1730,6 @@ int i915_gem_huge_page_mock_selftests(void)
>  
>  out_unlock:
>         mutex_unlock(&dev_priv->drm.struct_mutex);
> -
> -       i915_modparams.enable_ppgtt = saved_ppgtt;
> -
>         drm_dev_put(&dev_priv->drm);
>  
>         return err;
> @@ -1753,7 +1749,7 @@ int i915_gem_huge_page_live_selftests(struct drm_i915_private *dev_priv)
>         struct i915_gem_context *ctx;
>         int err;
>  
> -       if (!USES_PPGTT(dev_priv)) {
> +       if (!HAS_PPGTT(dev_priv)) {
>                 pr_info("PPGTT not supported, skipping live-selftests\n");
>                 return 0;
>         }
> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> index 76df25aa90c9..913c0f83f86a 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> @@ -535,7 +535,6 @@ static int igt_ctx_exec(void *arg)
>         IGT_TIMEOUT(end_time);
>         LIST_HEAD(objects);
>         unsigned long ncontexts, ndwords, dw;
> -       bool first_shared_gtt = true;
>         int err = -ENODEV;
>  
>         /*
> @@ -561,12 +560,7 @@ static int igt_ctx_exec(void *arg)
>                 struct i915_gem_context *ctx;
>                 unsigned int id;
>  
> -               if (first_shared_gtt) {
> -                       ctx = __create_hw_context(i915, file->driver_priv);
> -                       first_shared_gtt = false;
> -               } else {
> -                       ctx = i915_gem_create_context(i915, file->driver_priv);
> -               }
> +               ctx = i915_gem_create_context(i915, file->driver_priv);
>                 if (IS_ERR(ctx)) {
>                         err = PTR_ERR(ctx);
>                         goto out_unlock;
> @@ -865,33 +859,6 @@ static int igt_switch_to_kernel_context(void *arg)
>         return err;
>  }
>  
> -static int fake_aliasing_ppgtt_enable(struct drm_i915_private *i915)
> -{
> -       struct drm_i915_gem_object *obj;
> -       int err;
> -
> -       err = i915_gem_init_aliasing_ppgtt(i915);
> -       if (err)
> -               return err;
> -
> -       list_for_each_entry(obj, &i915->mm.bound_list, mm.link) {
> -               struct i915_vma *vma;
> -
> -               vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
> -               if (IS_ERR(vma))
> -                       continue;
> -
> -               vma->flags &= ~I915_VMA_LOCAL_BIND;
> -       }
> -
> -       return 0;
> -}
> -
> -static void fake_aliasing_ppgtt_disable(struct drm_i915_private *i915)
> -{
> -       i915_gem_fini_aliasing_ppgtt(i915);
> -}
> -
>  int i915_gem_context_mock_selftests(void)
>  {
>         static const struct i915_subtest tests[] = {
> @@ -918,31 +885,9 @@ int i915_gem_context_live_selftests(struct drm_i915_private *dev_priv)
>                 SUBTEST(igt_ctx_exec),
>                 SUBTEST(igt_ctx_readonly),
>         };
> -       bool fake_alias = false;
> -       int err;
>  
>         if (i915_terminally_wedged(&dev_priv->gpu_error))
>                 return 0;
>  
> -       /* Install a fake aliasing gtt for exercise */
> -       if (USES_PPGTT(dev_priv) && !dev_priv->mm.aliasing_ppgtt) {
> -               mutex_lock(&dev_priv->drm.struct_mutex);
> -               err = fake_aliasing_ppgtt_enable(dev_priv);
> -               mutex_unlock(&dev_priv->drm.struct_mutex);
> -               if (err)
> -                       return err;
> -
> -               GEM_BUG_ON(!dev_priv->mm.aliasing_ppgtt);
> -               fake_alias = true;
> -       }
> -
> -       err = i915_subtests(tests, dev_priv);
> -
> -       if (fake_alias) {
> -               mutex_lock(&dev_priv->drm.struct_mutex);
> -               fake_aliasing_ppgtt_disable(dev_priv);
> -               mutex_unlock(&dev_priv->drm.struct_mutex);
> -       }
> -
> -       return err;
> +       return i915_subtests(tests, dev_priv);
>  }
> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
> index 128ad1cf0647..4365979d8222 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
> @@ -351,7 +351,7 @@ static int igt_evict_contexts(void *arg)
>          * where the GTT space of the request is separate from the GGTT
>          * allocation required to build the request.
>          */
> -       if (!USES_FULL_PPGTT(i915))
> +       if (!HAS_FULL_PPGTT(i915))
>                 return 0;
>  
>         mutex_lock(&i915->drm.struct_mutex);
> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> index 8e2e269db97e..17b5aaaa7a50 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> @@ -153,7 +153,7 @@ static int igt_ppgtt_alloc(void *arg)
>  
>         /* Allocate a ppggt and try to fill the entire range */
>  
> -       if (!USES_PPGTT(dev_priv))
> +       if (!HAS_PPGTT(dev_priv))
>                 return 0;
>  
>         ppgtt = __hw_ppgtt_create(dev_priv);
> @@ -1001,7 +1001,7 @@ static int exercise_ppgtt(struct drm_i915_private *dev_priv,
>         IGT_TIMEOUT(end_time);
>         int err;
>  
> -       if (!USES_FULL_PPGTT(dev_priv))
> +       if (!HAS_FULL_PPGTT(dev_priv))
>                 return 0;
>  
>         file = mock_file(dev_priv);
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index a4446f452040..298b2e197744 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -412,6 +412,14 @@ typedef struct drm_i915_irq_wait {
>         int irq_seq;
>  } drm_i915_irq_wait_t;
>  
> +/*
> + * Different modes of per-process Graphics Translation Table,
> + * see I915_PARAM_HAS_ALIASING_PPGTT
> + */
> +#define I915_GEM_PPGTT_NONE    0
> +#define I915_GEM_PPGTT_ALIASING        1
> +#define I915_GEM_PPGTT_FULL    2
> +
>  /* Ioctl to query kernel params:
>   */
>  #define I915_PARAM_IRQ_ACTIVE            1
> -- 
> 2.19.0
> 
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v5] drm/i915: Remove i915.enable_ppgtt override
  2018-09-27  8:20   ` Joonas Lahtinen
@ 2018-09-27  8:55     ` Chris Wilson
  2018-09-27 10:57       ` Joonas Lahtinen
  0 siblings, 1 reply; 24+ messages in thread
From: Chris Wilson @ 2018-09-27  8:55 UTC (permalink / raw)
  To: Jani Nikula, Joonas Lahtinen, intel-gfx; +Cc: Matthew Auld

Quoting Joonas Lahtinen (2018-09-27 09:20:06)
> Quoting Chris Wilson (2018-09-26 23:12:22)
> > Now that we are confident in providing full-ppgtt where supported,
> > remove the ability to override the context isolation.
> > 
> > v2: Remove faked aliasing-ppgtt for testing as it no longer is accepted.
> > v3: s/USES/HAS/ to match usage and reject attempts to load the module on
> > old GVT-g setups that do not provide support for full-ppgtt.
> > v4: Insulate ABI ppGTT values from our internal enum (later plans
> > involve moving ppGTT depth out of the enum, thus potentially breaking
> > ABI unless we document the current values).
> > 
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > Cc: Matthew Auld <matthew.auld@intel.com>
> > Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> #v3
> 
> + Jani for awareness when handling dinq, this solidifies existing uAPI
> And drops the reporting of 48-bit ppGTT through this getparam as we
> already have context specific I915_CONTEXT_PARAM_GTT_SIZE for that and
> no known abusers for the unintended reporting outside 0,1,2 set.

Are we past the 4.20 cutoff? I'd rather have this in 4.21 so that we
have a cycle in front of users before sealing the transition.
-Chris
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v5] drm/i915: Remove i915.enable_ppgtt override
  2018-09-27  8:55     ` Chris Wilson
@ 2018-09-27 10:57       ` Joonas Lahtinen
  2018-09-27 11:07         ` Chris Wilson
  0 siblings, 1 reply; 24+ messages in thread
From: Joonas Lahtinen @ 2018-09-27 10:57 UTC (permalink / raw)
  To: Chris Wilson, Jani Nikula, intel-gfx; +Cc: Matthew Auld

Quoting Chris Wilson (2018-09-27 11:55:03)
> Quoting Joonas Lahtinen (2018-09-27 09:20:06)
> > Quoting Chris Wilson (2018-09-26 23:12:22)
> > > Now that we are confident in providing full-ppgtt where supported,
> > > remove the ability to override the context isolation.
> > > 
> > > v2: Remove faked aliasing-ppgtt for testing as it no longer is accepted.
> > > v3: s/USES/HAS/ to match usage and reject attempts to load the module on
> > > old GVT-g setups that do not provide support for full-ppgtt.
> > > v4: Insulate ABI ppGTT values from our internal enum (later plans
> > > involve moving ppGTT depth out of the enum, thus potentially breaking
> > > ABI unless we document the current values).
> > > 
> > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > > Cc: Matthew Auld <matthew.auld@intel.com>
> > > Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> #v3
> > 
> > + Jani for awareness when handling dinq, this solidifies existing uAPI
> > And drops the reporting of 48-bit ppGTT through this getparam as we
> > already have context specific I915_CONTEXT_PARAM_GTT_SIZE for that and
> > no known abusers for the unintended reporting outside 0,1,2 set.
> 
> Are we past the 4.20 cutoff? I'd rather have this in 4.21 so that we
> have a cycle in front of users before sealing the transition.

Yes we are. Just go ahead with the merge.

Regards, Joonas
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^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v5] drm/i915: Remove i915.enable_ppgtt override
  2018-09-27 10:57       ` Joonas Lahtinen
@ 2018-09-27 11:07         ` Chris Wilson
  0 siblings, 0 replies; 24+ messages in thread
From: Chris Wilson @ 2018-09-27 11:07 UTC (permalink / raw)
  To: Jani Nikula, Joonas Lahtinen, intel-gfx; +Cc: Matthew Auld

Quoting Joonas Lahtinen (2018-09-27 11:57:53)
> Quoting Chris Wilson (2018-09-27 11:55:03)
> > Quoting Joonas Lahtinen (2018-09-27 09:20:06)
> > > Quoting Chris Wilson (2018-09-26 23:12:22)
> > > > Now that we are confident in providing full-ppgtt where supported,
> > > > remove the ability to override the context isolation.
> > > > 
> > > > v2: Remove faked aliasing-ppgtt for testing as it no longer is accepted.
> > > > v3: s/USES/HAS/ to match usage and reject attempts to load the module on
> > > > old GVT-g setups that do not provide support for full-ppgtt.
> > > > v4: Insulate ABI ppGTT values from our internal enum (later plans
> > > > involve moving ppGTT depth out of the enum, thus potentially breaking
> > > > ABI unless we document the current values).
> > > > 
> > > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > > > Cc: Matthew Auld <matthew.auld@intel.com>
> > > > Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> #v3
> > > 
> > > + Jani for awareness when handling dinq, this solidifies existing uAPI
> > > And drops the reporting of 48-bit ppGTT through this getparam as we
> > > already have context specific I915_CONTEXT_PARAM_GTT_SIZE for that and
> > > no known abusers for the unintended reporting outside 0,1,2 set.
> > 
> > Are we past the 4.20 cutoff? I'd rather have this in 4.21 so that we
> > have a cycle in front of users before sealing the transition.
> 
> Yes we are. Just go ahead with the merge.

Done.
-Chris
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^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v4] drm/i915: Remove i915.enable_ppgtt override
  2018-09-26  8:02       ` Joonas Lahtinen
  2018-09-26 12:29         ` Zhi Wang
@ 2018-10-08  9:53         ` Zhenyu Wang
  2018-10-08 13:58           ` Wang, Zhi A
  1 sibling, 1 reply; 24+ messages in thread
From: Zhenyu Wang @ 2018-10-08  9:53 UTC (permalink / raw)
  To: Joonas Lahtinen; +Cc: intel-gfx, Auld, Matthew


[-- Attachment #1.1: Type: text/plain, Size: 37096 bytes --]

On 2018.09.26 11:02:15 +0300, Joonas Lahtinen wrote:
> Quoting He, Min (2018-09-26 04:06:25)
> > No. We changed to full 48bit ppgtt long time ago. :)
> 
> So would that mean the change is OK to do?

Looks that one unfortunately caused gvt regression, gvt context has
no i915 managed i915_hw_ppgtt but only shadowed one, so need to check
if ppgtt is valid before access.

> 
> Acked-by from you, Zhi, would be good to have for documentation purposes
> in that case :)
> 
> Regards, Joonas
> 
> > 
> > > -----Original Message-----
> > > From: Wang, Zhi A
> > > Sent: Wednesday, September 26, 2018 2:01 AM
> > > To: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>; Chris Wilson
> > > <chris@chris-wilson.co.uk>; intel-gfx@lists.freedesktop.org; Zhenyu Wang
> > > <zhenyuw@linux.intel.com>
> > > Cc: Auld, Matthew <matthew.auld@intel.com>; He, Min <min.he@intel.com>
> > > Subject: Re: [PATCH v4] drm/i915: Remove i915.enable_ppgtt override
> > > 
> > > Hi Min:
> > > 
> > > I remembered the IOTG guest kernel is using aliasing-ppgtt in the last
> > > technical sharing (probably I didn't remember it correctly). Can you
> > > confirm?
> > > 
> > > Also, thanks Joonas for the reminding. :)
> > > 
> > > thanks,
> > > Zhi.
> > > 
> > > On 09/25/18 09:22, Joonas Lahtinen wrote:
> > > > + Zhi and Zhenyu
> > > >
> > > > For me the patch looks ok.
> > > >
> > > > It refuses to load GVT on systems where 48-bit is not supported, for not
> > > > worsening the system security when virtualization is enabled (as anybody
> > > > would probably expect virtualization to improve that). Please see code.
> > > >
> > > > Do we have such systems in the wild? Should we instruct the user to
> > > > updating the hypervisor to specific kernel version when they hit the
> > > > error?
> > > >
> > > > Regards, Joonas
> > > >
> > > > Quoting Chris Wilson (2018-09-25 14:48:20)
> > > >> Now that we are confident in providing full-ppgtt where supported,
> > > >> remove the ability to override the context isolation.
> > > >>
> > > >> v2: Remove faked aliasing-ppgtt for testing as it no longer is accepted.
> > > >> v3: s/USES/HAS/ to match usage and reject attempts to load the module
> > > on
> > > >> old GVT-g setups that do not provide support for full-ppgtt.
> > > >>
> > > >> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > >> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > > >> Cc: Matthew Auld <matthew.auld@intel.com>
> > > >> ---
> > > >>   drivers/gpu/drm/i915/i915_drv.c               | 22 +++--
> > > >>   drivers/gpu/drm/i915/i915_drv.h               | 14 +--
> > > >>   drivers/gpu/drm/i915/i915_gem_context.c       |  2 +-
> > > >>   drivers/gpu/drm/i915/i915_gem_gtt.c           | 88 ++-----------------
> > > >>   drivers/gpu/drm/i915/i915_gpu_error.c         |  4 +-
> > > >>   drivers/gpu/drm/i915/i915_params.c            |  4 -
> > > >>   drivers/gpu/drm/i915/i915_params.h            |  1 -
> > > >>   drivers/gpu/drm/i915/i915_pci.c               | 17 ++--
> > > >>   drivers/gpu/drm/i915/intel_device_info.c      |  6 ++
> > > >>   drivers/gpu/drm/i915/intel_device_info.h      | 11 ++-
> > > >>   drivers/gpu/drm/i915/intel_lrc.c              | 13 ++-
> > > >>   drivers/gpu/drm/i915/selftests/huge_pages.c   | 12 +--
> > > >>   .../gpu/drm/i915/selftests/i915_gem_context.c | 59 +------------
> > > >>   .../gpu/drm/i915/selftests/i915_gem_evict.c   |  2 +-
> > > >>   drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |  4 +-
> > > >>   15 files changed, 62 insertions(+), 197 deletions(-)
> > > >>
> > > >> diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > > b/drivers/gpu/drm/i915/i915_drv.c
> > > >> index 44e2c0f5ec50..3efbbc71c3b4 100644
> > > >> --- a/drivers/gpu/drm/i915/i915_drv.c
> > > >> +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > >> @@ -345,7 +345,7 @@ static int i915_getparam_ioctl(struct drm_device
> > > *dev, void *data,
> > > >>                  value = HAS_WT(dev_priv);
> > > >>                  break;
> > > >>          case I915_PARAM_HAS_ALIASING_PPGTT:
> > > >> -               value = USES_PPGTT(dev_priv);
> > > >> +               value = INTEL_PPGTT(dev_priv);
> > > >>                  break;
> > > >>          case I915_PARAM_HAS_SEMAPHORES:
> > > >>                  value = HAS_LEGACY_SEMAPHORES(dev_priv);
> > > >> @@ -1049,17 +1049,6 @@ static void i915_driver_cleanup_mmio(struct
> > > drm_i915_private *dev_priv)
> > > >>
> > > >>   static void intel_sanitize_options(struct drm_i915_private *dev_priv)
> > > >>   {
> > > >> -       /*
> > > >> -        * i915.enable_ppgtt is read-only, so do an early pass to validate the
> > > >> -        * user's requested state against the hardware/driver capabilities.
> > > We
> > > >> -        * do this now so that we can print out any log messages once rather
> > > >> -        * than every time we check intel_enable_ppgtt().
> > > >> -        */
> > > >> -       i915_modparams.enable_ppgtt =
> > > >> -               intel_sanitize_enable_ppgtt(dev_priv,
> > > >> -                                           i915_modparams.enable_ppgtt);
> > > >> -       DRM_DEBUG_DRIVER("ppgtt mode: %i\n",
> > > i915_modparams.enable_ppgtt);
> > > >> -
> > > >>          intel_gvt_sanitize_options(dev_priv);
> > > >>   }
> > > >>
> > > >> @@ -1374,6 +1363,15 @@ static int i915_driver_init_hw(struct
> > > drm_i915_private *dev_priv)
> > > >>
> > > >>          intel_device_info_runtime_init(mkwrite_device_info(dev_priv));
> > > >>
> > > >> +       if (HAS_PPGTT(dev_priv)) {
> > > >> +               if (intel_vgpu_active(dev_priv) &&
> > > >> +                   !intel_vgpu_has_full_48bit_ppgtt(dev_priv)) {
> > > >> +                       i915_report_error(dev_priv,
> > > >> +                                         "incompatible vGPU found, support for isolated
> > > ppGTT required\n");
> > > >> +                       return -ENXIO;
> > > >> +               }
> > > >> +       }
> > > >> +
> > > >>          intel_sanitize_options(dev_priv);
> > > >>
> > > >>          i915_perf_init(dev_priv);
> > > >> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > > b/drivers/gpu/drm/i915/i915_drv.h
> > > >> index 8624b4bdc242..f28b3c2a3cd2 100644
> > > >> --- a/drivers/gpu/drm/i915/i915_drv.h
> > > >> +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > >> @@ -2593,9 +2593,14 @@ intel_info(const struct drm_i915_private
> > > *dev_priv)
> > > >>
> > > >>   #define HAS_EXECLISTS(dev_priv)
> > > HAS_LOGICAL_RING_CONTEXTS(dev_priv)
> > > >>
> > > >> -#define USES_PPGTT(dev_priv)           (i915_modparams.enable_ppgtt)
> > > >> -#define USES_FULL_PPGTT(dev_priv)
> > > (i915_modparams.enable_ppgtt >= 2)
> > > >> -#define USES_FULL_48BIT_PPGTT(dev_priv)
> > > (i915_modparams.enable_ppgtt == 3)
> > > >> +#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt)
> > > >> +#define HAS_PPGTT(dev_priv) \
> > > >> +       (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
> > > >> +#define HAS_FULL_PPGTT(dev_priv) \
> > > >> +       (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
> > > >> +#define HAS_FULL_48BIT_PPGTT(dev_priv) \
> > > >> +       (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL_4LVL)
> > > >> +
> > > >>   #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
> > > >>          GEM_BUG_ON((sizes) == 0); \
> > > >>          ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
> > > >> @@ -2743,9 +2748,6 @@ intel_ggtt_update_needs_vtd_wa(struct
> > > drm_i915_private *dev_priv)
> > > >>          return IS_BROXTON(dev_priv) && intel_vtd_active();
> > > >>   }
> > > >>
> > > >> -int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
> > > >> -                               int enable_ppgtt);
> > > >> -
> > > >>   /* i915_drv.c */
> > > >>   void __printf(3, 4)
> > > >>   __i915_printk(struct drm_i915_private *dev_priv, const char *level,
> > > >> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
> > > b/drivers/gpu/drm/i915/i915_gem_context.c
> > > >> index f772593b99ab..15c92f75b1b8 100644
> > > >> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> > > >> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> > > >> @@ -414,7 +414,7 @@ i915_gem_create_context(struct
> > > drm_i915_private *dev_priv,
> > > >>          if (IS_ERR(ctx))
> > > >>                  return ctx;
> > > >>
> > > >> -       if (USES_FULL_PPGTT(dev_priv)) {
> > > >> +       if (HAS_FULL_PPGTT(dev_priv)) {
> > > >>                  struct i915_hw_ppgtt *ppgtt;
> > > >>
> > > >>                  ppgtt = i915_ppgtt_create(dev_priv, file_priv);
> > > >> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > >> index f6c7ab413081..c9363504949f 100644
> > > >> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > >> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > >> @@ -133,55 +133,6 @@ static inline void i915_ggtt_invalidate(struct
> > > drm_i915_private *i915)
> > > >>          i915->ggtt.invalidate(i915);
> > > >>   }
> > > >>
> > > >> -int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
> > > >> -                               int enable_ppgtt)
> > > >> -{
> > > >> -       bool has_full_ppgtt;
> > > >> -       bool has_full_48bit_ppgtt;
> > > >> -
> > > >> -       if (!dev_priv->info.has_aliasing_ppgtt)
> > > >> -               return 0;
> > > >> -
> > > >> -       has_full_ppgtt = dev_priv->info.has_full_ppgtt;
> > > >> -       has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt;
> > > >> -
> > > >> -       if (intel_vgpu_active(dev_priv)) {
> > > >> -               /* GVT-g has no support for 32bit ppgtt */
> > > >> -               has_full_ppgtt = false;
> > > >> -               has_full_48bit_ppgtt =
> > > intel_vgpu_has_full_48bit_ppgtt(dev_priv);
> > > >> -       }
> > > >> -
> > > >> -       /*
> > > >> -        * We don't allow disabling PPGTT for gen8+ as it's a requirement for
> > > >> -        * execlists, the sole mechanism available to submit work.
> > > >> -        */
> > > >> -       if (enable_ppgtt == 0 && !HAS_EXECLISTS(dev_priv))
> > > >> -               return 0;
> > > >> -
> > > >> -       if (enable_ppgtt == 1)
> > > >> -               return 1;
> > > >> -
> > > >> -       if (enable_ppgtt == 2 && has_full_ppgtt)
> > > >> -               return 2;
> > > >> -
> > > >> -       if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
> > > >> -               return 3;
> > > >> -
> > > >> -       /* Disable ppgtt on SNB if VT-d is on. */
> > > >> -       if (IS_GEN6(dev_priv) && intel_vtd_active()) {
> > > >> -               DRM_INFO("Disabling PPGTT because VT-d is on\n");
> > > >> -               return 0;
> > > >> -       }
> > > >> -
> > > >> -       if (has_full_48bit_ppgtt)
> > > >> -               return 3;
> > > >> -
> > > >> -       if (has_full_ppgtt)
> > > >> -               return 2;
> > > >> -
> > > >> -       return 1;
> > > >> -}
> > > >> -
> > > >>   static int ppgtt_bind_vma(struct i915_vma *vma,
> > > >>                            enum i915_cache_level cache_level,
> > > >>                            u32 unused)
> > > >> @@ -1647,7 +1598,7 @@ static struct i915_hw_ppgtt
> > > *gen8_ppgtt_create(struct drm_i915_private *i915)
> > > >>          ppgtt->vm.i915 = i915;
> > > >>          ppgtt->vm.dma = &i915->drm.pdev->dev;
> > > >>
> > > >> -       ppgtt->vm.total = USES_FULL_48BIT_PPGTT(i915) ?
> > > >> +       ppgtt->vm.total = HAS_FULL_48BIT_PPGTT(i915) ?
> > > >>                  1ULL << 48 :
> > > >>                  1ULL << 32;
> > > >>
> > > >> @@ -1782,19 +1733,6 @@ static inline void gen6_write_pde(const struct
> > > gen6_hw_ppgtt *ppgtt,
> > > >>                    ppgtt->pd_addr + pde);
> > > >>   }
> > > >>
> > > >> -static void gen8_ppgtt_enable(struct drm_i915_private *dev_priv)
> > > >> -{
> > > >> -       struct intel_engine_cs *engine;
> > > >> -       enum intel_engine_id id;
> > > >> -
> > > >> -       for_each_engine(engine, dev_priv, id) {
> > > >> -               u32 four_level = USES_FULL_48BIT_PPGTT(dev_priv) ?
> > > >> -                                GEN8_GFX_PPGTT_48B : 0;
> > > >> -               I915_WRITE(RING_MODE_GEN7(engine),
> > > >> -                          _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
> > > >> -       }
> > > >> -}
> > > >> -
> > > >>   static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv)
> > > >>   {
> > > >>          struct intel_engine_cs *engine;
> > > >> @@ -1834,7 +1772,8 @@ static void gen6_ppgtt_enable(struct
> > > drm_i915_private *dev_priv)
> > > >>          ecochk = I915_READ(GAM_ECOCHK);
> > > >>          I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
> > > ECOCHK_PPGTT_CACHE64B);
> > > >>
> > > >> -       I915_WRITE(GFX_MODE,
> > > _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
> > > >> +       if (HAS_PPGTT(dev_priv)) /* may be disabled for VT-d */
> > > >> +               I915_WRITE(GFX_MODE,
> > > _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
> > > >>   }
> > > >>
> > > >>   /* PPGTT support for Sandybdrige/Gen6 and later */
> > > >> @@ -2237,23 +2176,10 @@ int i915_ppgtt_init_hw(struct
> > > drm_i915_private *dev_priv)
> > > >>   {
> > > >>          gtt_write_workarounds(dev_priv);
> > > >>
> > > >> -       /* In the case of execlists, PPGTT is enabled by the context descriptor
> > > >> -        * and the PDPs are contained within the context itself.  We don't
> > > >> -        * need to do anything here. */
> > > >> -       if (HAS_LOGICAL_RING_CONTEXTS(dev_priv))
> > > >> -               return 0;
> > > >> -
> > > >> -       if (!USES_PPGTT(dev_priv))
> > > >> -               return 0;
> > > >> -
> > > >>          if (IS_GEN6(dev_priv))
> > > >>                  gen6_ppgtt_enable(dev_priv);
> > > >>          else if (IS_GEN7(dev_priv))
> > > >>                  gen7_ppgtt_enable(dev_priv);
> > > >> -       else if (INTEL_GEN(dev_priv) >= 8)
> > > >> -               gen8_ppgtt_enable(dev_priv);
> > > >> -       else
> > > >> -               MISSING_CASE(INTEL_GEN(dev_priv));
> > > >>
> > > >>          return 0;
> > > >>   }
> > > >> @@ -2952,7 +2878,7 @@ int i915_gem_init_ggtt(struct drm_i915_private
> > > *dev_priv)
> > > >>          /* And finally clear the reserved guard page */
> > > >>          ggtt->vm.clear_range(&ggtt->vm, ggtt->vm.total - PAGE_SIZE,
> > > PAGE_SIZE);
> > > >>
> > > >> -       if (USES_PPGTT(dev_priv) && !USES_FULL_PPGTT(dev_priv)) {
> > > >> +       if (INTEL_PPGTT(dev_priv) == INTEL_PPGTT_ALIASING) {
> > > >>                  ret = i915_gem_init_aliasing_ppgtt(dev_priv);
> > > >>                  if (ret)
> > > >>                          goto err;
> > > >> @@ -3275,7 +3201,7 @@ static void bdw_setup_private_ppat(struct
> > > intel_ppat *ppat)
> > > >>          ppat->match = bdw_private_pat_match;
> > > >>          ppat->clear_value = GEN8_PPAT_WB | GEN8_PPAT_LLCELLC |
> > > GEN8_PPAT_AGE(3);
> > > >>
> > > >> -       if (!USES_PPGTT(ppat->i915)) {
> > > >> +       if (!HAS_PPGTT(ppat->i915)) {
> > > >>                  /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
> > > >>                   * so RTL will always use the value corresponding to
> > > >>                   * pat_sel = 000".
> > > >> @@ -3402,7 +3328,7 @@ static int gen8_gmch_probe(struct i915_ggtt
> > > *ggtt)
> > > >>          ggtt->vm.cleanup = gen6_gmch_remove;
> > > >>          ggtt->vm.insert_page = gen8_ggtt_insert_page;
> > > >>          ggtt->vm.clear_range = nop_clear_range;
> > > >> -       if (!USES_FULL_PPGTT(dev_priv) ||
> > > intel_scanout_needs_vtd_wa(dev_priv))
> > > >> +       if (intel_scanout_needs_vtd_wa(dev_priv))
> > > >>                  ggtt->vm.clear_range = gen8_ggtt_clear_range;
> > > >>
> > > >>          ggtt->vm.insert_entries = gen8_ggtt_insert_entries;
> > > >> @@ -3609,7 +3535,7 @@ int i915_ggtt_init_hw(struct drm_i915_private
> > > *dev_priv)
> > > >>          /* Only VLV supports read-only GGTT mappings */
> > > >>          ggtt->vm.has_read_only = IS_VALLEYVIEW(dev_priv);
> > > >>
> > > >> -       if (!HAS_LLC(dev_priv) && !USES_PPGTT(dev_priv))
> > > >> +       if (!HAS_LLC(dev_priv) && !HAS_PPGTT(dev_priv))
> > > >>                  ggtt->vm.mm.color_adjust = i915_gtt_color_adjust;
> > > >>          mutex_unlock(&dev_priv->drm.struct_mutex);
> > > >>
> > > >> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
> > > b/drivers/gpu/drm/i915/i915_gpu_error.c
> > > >> index 2835cacd0d08..3d5554f14dfd 100644
> > > >> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> > > >> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> > > >> @@ -474,7 +474,7 @@ static void error_print_engine(struct
> > > drm_i915_error_state_buf *m,
> > > >>                          err_printf(m, "  SYNC_2: 0x%08x\n",
> > > >>                                     ee->semaphore_mboxes[2]);
> > > >>          }
> > > >> -       if (USES_PPGTT(m->i915)) {
> > > >> +       if (HAS_PPGTT(m->i915)) {
> > > >>                  err_printf(m, "  GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
> > > >>
> > > >>                  if (INTEL_GEN(m->i915) >= 8) {
> > > >> @@ -1230,7 +1230,7 @@ static void
> > > error_record_engine_registers(struct i915_gpu_state *error,
> > > >>          ee->reset_count = i915_reset_engine_count(&dev_priv->gpu_error,
> > > >>                                                    engine);
> > > >>
> > > >> -       if (USES_PPGTT(dev_priv)) {
> > > >> +       if (HAS_PPGTT(dev_priv)) {
> > > >>                  int i;
> > > >>
> > > >>                  ee->vm_info.gfx_mode =
> > > I915_READ(RING_MODE_GEN7(engine));
> > > >> diff --git a/drivers/gpu/drm/i915/i915_params.c
> > > b/drivers/gpu/drm/i915/i915_params.c
> > > >> index 295e981e4a39..bd6bd8879cab 100644
> > > >> --- a/drivers/gpu/drm/i915/i915_params.c
> > > >> +++ b/drivers/gpu/drm/i915/i915_params.c
> > > >> @@ -82,10 +82,6 @@ i915_param_named_unsafe(enable_hangcheck,
> > > bool, 0644,
> > > >>          "WARNING: Disabling this can cause system wide hangs. "
> > > >>          "(default: true)");
> > > >>
> > > >> -i915_param_named_unsafe(enable_ppgtt, int, 0400,
> > > >> -       "Override PPGTT usage. "
> > > >> -       "(-1=auto [default], 0=disabled, 1=aliasing, 2=full, 3=full with
> > > extended address space)");
> > > >> -
> > > >>   i915_param_named_unsafe(enable_psr, int, 0600,
> > > >>          "Enable PSR "
> > > >>          "(0=disabled, 1=enabled) "
> > > >> diff --git a/drivers/gpu/drm/i915/i915_params.h
> > > b/drivers/gpu/drm/i915/i915_params.h
> > > >> index 6c4d4a21474b..7e56c516c815 100644
> > > >> --- a/drivers/gpu/drm/i915/i915_params.h
> > > >> +++ b/drivers/gpu/drm/i915/i915_params.h
> > > >> @@ -41,7 +41,6 @@ struct drm_printer;
> > > >>          param(int, vbt_sdvo_panel_type, -1) \
> > > >>          param(int, enable_dc, -1) \
> > > >>          param(int, enable_fbc, -1) \
> > > >> -       param(int, enable_ppgtt, -1) \
> > > >>          param(int, enable_psr, -1) \
> > > >>          param(int, disable_power_well, -1) \
> > > >>          param(int, enable_ips, 1) \
> > > >> diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > > b/drivers/gpu/drm/i915/i915_pci.c
> > > >> index d6f7b9fe1d26..eeec902896b9 100644
> > > >> --- a/drivers/gpu/drm/i915/i915_pci.c
> > > >> +++ b/drivers/gpu/drm/i915/i915_pci.c
> > > >> @@ -252,7 +252,7 @@ static const struct intel_device_info
> > > intel_ironlake_m_info = {
> > > >>          .has_llc = 1, \
> > > >>          .has_rc6 = 1, \
> > > >>          .has_rc6p = 1, \
> > > >> -       .has_aliasing_ppgtt = 1, \
> > > >> +       .ppgtt = INTEL_PPGTT_ALIASING, \
> > > >>          GEN_DEFAULT_PIPEOFFSETS, \
> > > >>          GEN_DEFAULT_PAGE_SIZES, \
> > > >>          CURSOR_OFFSETS
> > > >> @@ -297,8 +297,7 @@ static const struct intel_device_info
> > > intel_sandybridge_m_gt2_info = {
> > > >>          .has_llc = 1, \
> > > >>          .has_rc6 = 1, \
> > > >>          .has_rc6p = 1, \
> > > >> -       .has_aliasing_ppgtt = 1, \
> > > >> -       .has_full_ppgtt = 1, \
> > > >> +       .ppgtt = INTEL_PPGTT_FULL, \
> > > >>          GEN_DEFAULT_PIPEOFFSETS, \
> > > >>          GEN_DEFAULT_PAGE_SIZES, \
> > > >>          IVB_CURSOR_OFFSETS
> > > >> @@ -351,8 +350,7 @@ static const struct intel_device_info
> > > intel_valleyview_info = {
> > > >>          .has_rc6 = 1,
> > > >>          .has_gmch_display = 1,
> > > >>          .has_hotplug = 1,
> > > >> -       .has_aliasing_ppgtt = 1,
> > > >> -       .has_full_ppgtt = 1,
> > > >> +       .ppgtt = INTEL_PPGTT_FULL,
> > > >>          .has_snoop = true,
> > > >>          .has_coherent_ggtt = false,
> > > >>          .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
> > > >> @@ -399,7 +397,7 @@ static const struct intel_device_info
> > > intel_haswell_gt3_info = {
> > > >>          .page_sizes = I915_GTT_PAGE_SIZE_4K | \
> > > >>                        I915_GTT_PAGE_SIZE_2M, \
> > > >>          .has_logical_ring_contexts = 1, \
> > > >> -       .has_full_48bit_ppgtt = 1, \
> > > >> +       .ppgtt = INTEL_PPGTT_FULL_4LVL, \
> > > >>          .has_64bit_reloc = 1, \
> > > >>          .has_reset_engine = 1
> > > >>
> > > >> @@ -443,8 +441,7 @@ static const struct intel_device_info
> > > intel_cherryview_info = {
> > > >>          .has_rc6 = 1,
> > > >>          .has_logical_ring_contexts = 1,
> > > >>          .has_gmch_display = 1,
> > > >> -       .has_aliasing_ppgtt = 1,
> > > >> -       .has_full_ppgtt = 1,
> > > >> +       .ppgtt = INTEL_PPGTT_FULL,
> > > >>          .has_reset_engine = 1,
> > > >>          .has_snoop = true,
> > > >>          .has_coherent_ggtt = false,
> > > >> @@ -518,9 +515,7 @@ static const struct intel_device_info
> > > intel_skylake_gt4_info = {
> > > >>          .has_logical_ring_contexts = 1, \
> > > >>          .has_logical_ring_preemption = 1, \
> > > >>          .has_guc = 1, \
> > > >> -       .has_aliasing_ppgtt = 1, \
> > > >> -       .has_full_ppgtt = 1, \
> > > >> -       .has_full_48bit_ppgtt = 1, \
> > > >> +       .ppgtt = INTEL_PPGTT_FULL_4LVL, \
> > > >>          .has_reset_engine = 1, \
> > > >>          .has_snoop = true, \
> > > >>          .has_coherent_ggtt = false, \
> > > >> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> > > b/drivers/gpu/drm/i915/intel_device_info.c
> > > >> index 0ef0c6448d53..a841d181efd3 100644
> > > >> --- a/drivers/gpu/drm/i915/intel_device_info.c
> > > >> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > > >> @@ -26,6 +26,7 @@
> > > >>
> > > >>   #include "intel_device_info.h"
> > > >>   #include "i915_drv.h"
> > > >> +#include "i915_vgpu.h"
> > > >>
> > > >>   #define PLATFORM_NAME(x) [INTEL_##x] = #x
> > > >>   static const char * const platform_names[] = {
> > > >> @@ -851,6 +852,11 @@ void intel_device_info_runtime_init(struct
> > > intel_device_info *info)
> > > >>          else if (INTEL_GEN(dev_priv) >= 11)
> > > >>                  gen11_sseu_info_init(dev_priv);
> > > >>
> > > >> +       if (IS_GEN6(dev_priv) && intel_vtd_active()) {
> > > >> +               DRM_INFO("Disabling ppGTT for VT-d support\n");
> > > >> +               info->ppgtt = INTEL_PPGTT_NONE;
> > > >> +       }
> > > >> +
> > > >>          /* Initialize command stream timestamp frequency */
> > > >>          info->cs_timestamp_frequency_khz =
> > > read_timestamp_frequency(dev_priv);
> > > >>   }
> > > >> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> > > b/drivers/gpu/drm/i915/intel_device_info.h
> > > >> index 6eecd64734d5..6bab97687328 100644
> > > >> --- a/drivers/gpu/drm/i915/intel_device_info.h
> > > >> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > > >> @@ -74,21 +74,25 @@ enum intel_platform {
> > > >>          INTEL_MAX_PLATFORMS
> > > >>   };
> > > >>
> > > >> +enum intel_ppgtt {
> > > >> +       INTEL_PPGTT_NONE = 0,
> > > >> +       INTEL_PPGTT_ALIASING,
> > > >> +       INTEL_PPGTT_FULL,
> > > >> +       INTEL_PPGTT_FULL_4LVL,
> > > >> +};
> > > >> +
> > > >>   #define DEV_INFO_FOR_EACH_FLAG(func) \
> > > >>          func(is_mobile); \
> > > >>          func(is_lp); \
> > > >>          func(is_alpha_support); \
> > > >>          /* Keep has_* in alphabetical order */ \
> > > >>          func(has_64bit_reloc); \
> > > >> -       func(has_aliasing_ppgtt); \
> > > >>          func(has_csr); \
> > > >>          func(has_ddi); \
> > > >>          func(has_dp_mst); \
> > > >>          func(has_reset_engine); \
> > > >>          func(has_fbc); \
> > > >>          func(has_fpga_dbg); \
> > > >> -       func(has_full_ppgtt); \
> > > >> -       func(has_full_48bit_ppgtt); \
> > > >>          func(has_gmch_display); \
> > > >>          func(has_guc); \
> > > >>          func(has_guc_ct); \
> > > >> @@ -154,6 +158,7 @@ struct intel_device_info {
> > > >>          enum intel_platform platform;
> > > >>          u32 platform_mask;
> > > >>
> > > >> +       enum intel_ppgtt ppgtt;
> > > >>          unsigned int page_sizes; /* page sizes supported by the HW */
> > > >>
> > > >>          u32 display_mmio_offset;
> > > >> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> > > b/drivers/gpu/drm/i915/intel_lrc.c
> > > >> index 4b28225320ff..3836a8a3761a 100644
> > > >> --- a/drivers/gpu/drm/i915/intel_lrc.c
> > > >> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> > > >> @@ -418,9 +418,8 @@ execlists_update_context_pdps(struct
> > > i915_hw_ppgtt *ppgtt, u32 *reg_state)
> > > >>
> > > >>   static u64 execlists_update_context(struct i915_request *rq)
> > > >>   {
> > > >> +       struct i915_hw_ppgtt *ppgtt = rq->gem_context->ppgtt;
> > > >>          struct intel_context *ce = rq->hw_context;
> > > >> -       struct i915_hw_ppgtt *ppgtt =
> > > >> -               rq->gem_context->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
> > > >>          u32 *reg_state = ce->lrc_reg_state;
> > > >>
> > > >>          reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail);
> > > >> @@ -1376,7 +1375,7 @@ execlists_context_pin(struct intel_engine_cs
> > > *engine,
> > > >>          struct intel_context *ce = to_intel_context(ctx, engine);
> > > >>
> > > >>          lockdep_assert_held(&ctx->i915->drm.struct_mutex);
> > > >> -       GEM_BUG_ON(!(ctx->ppgtt ?: ctx->i915->mm.aliasing_ppgtt));
> > > >> +       GEM_BUG_ON(!ctx->ppgtt);
> > > >>
> > > >>          if (likely(ce->pin_count++))
> > > >>                  return ce;
> > > >> @@ -2031,8 +2030,7 @@ static int gen8_emit_bb_start(struct
> > > i915_request *rq,
> > > >>           * it is unsafe in case of lite-restore (because the ctx is
> > > >>           * not idle). PML4 is allocated during ppgtt init so this is
> > > >>           * not needed in 48-bit.*/
> > > >> -       if (rq->gem_context->ppgtt &&
> > > >> -           (intel_engine_flag(rq->engine) & rq->gem_context->ppgtt-
> > > >pd_dirty_rings) &&
> > > >> +       if ((intel_engine_flag(rq->engine) & rq->gem_context->ppgtt-
> > > >pd_dirty_rings) &&
> > > >>              !i915_vm_is_48bit(&rq->gem_context->ppgtt->vm) &&
> > > >>              !intel_vgpu_active(rq->i915)) {
> > > >>                  ret = intel_logical_ring_emit_pdps(rq);
> > > >> @@ -2634,7 +2632,6 @@ static void execlists_init_reg_state(u32 *regs,
> > > >>                                       struct intel_ring *ring)
> > > >>   {
> > > >>          struct drm_i915_private *dev_priv = engine->i915;
> > > >> -       struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: dev_priv-
> > > >mm.aliasing_ppgtt;
> > > >>          u32 base = engine->mmio_base;
> > > >>          bool rcs = engine->class == RENDER_CLASS;
> > > >>
> > > >> @@ -2706,12 +2703,12 @@ static void execlists_init_reg_state(u32 *regs,
> > > >>          CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0),
> > > 0);
> > > >>          CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0),
> > > 0);
> > > >>
> > > >> -       if (i915_vm_is_48bit(&ppgtt->vm)) {
> > > >> +       if (i915_vm_is_48bit(&ctx->ppgtt->vm)) {
> > > >>                  /* 64b PPGTT (48bit canonical)
> > > >>                   * PDP0_DESCRIPTOR contains the base address to PML4 and
> > > >>                   * other PDP Descriptors are ignored.
> > > >>                   */
> > > >> -               ASSIGN_CTX_PML4(ppgtt, regs);
> > > >> +               ASSIGN_CTX_PML4(ctx->ppgtt, regs);
> > > >>          }
> > > >>
> > > >>          if (rcs) {
> > > >> diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c
> > > b/drivers/gpu/drm/i915/selftests/huge_pages.c
> > > >> index 8d03f64eabd7..09ea65a29d98 100644
> > > >> --- a/drivers/gpu/drm/i915/selftests/huge_pages.c
> > > >> +++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
> > > >> @@ -1436,7 +1436,7 @@ static int igt_ppgtt_pin_update(void *arg)
> > > >>           * huge-gtt-pages.
> > > >>           */
> > > >>
> > > >> -       if (!USES_FULL_48BIT_PPGTT(dev_priv)) {
> > > >> +       if (!HAS_FULL_48BIT_PPGTT(dev_priv)) {
> > > >>                  pr_info("48b PPGTT not supported, skipping\n");
> > > >>                  return 0;
> > > >>          }
> > > >> @@ -1687,10 +1687,9 @@ int
> > > i915_gem_huge_page_mock_selftests(void)
> > > >>                  SUBTEST(igt_mock_ppgtt_huge_fill),
> > > >>                  SUBTEST(igt_mock_ppgtt_64K),
> > > >>          };
> > > >> -       int saved_ppgtt = i915_modparams.enable_ppgtt;
> > > >>          struct drm_i915_private *dev_priv;
> > > >> -       struct pci_dev *pdev;
> > > >>          struct i915_hw_ppgtt *ppgtt;
> > > >> +       struct pci_dev *pdev;
> > > >>          int err;
> > > >>
> > > >>          dev_priv = mock_gem_device();
> > > >> @@ -1698,7 +1697,7 @@ int i915_gem_huge_page_mock_selftests(void)
> > > >>                  return -ENOMEM;
> > > >>
> > > >>          /* Pretend to be a device which supports the 48b PPGTT */
> > > >> -       i915_modparams.enable_ppgtt = 3;
> > > >> +       mkwrite_device_info(dev_priv)->ppgtt = INTEL_PPGTT_FULL_4LVL;
> > > >>
> > > >>          pdev = dev_priv->drm.pdev;
> > > >>          dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(39));
> > > >> @@ -1731,9 +1730,6 @@ int i915_gem_huge_page_mock_selftests(void)
> > > >>
> > > >>   out_unlock:
> > > >>          mutex_unlock(&dev_priv->drm.struct_mutex);
> > > >> -
> > > >> -       i915_modparams.enable_ppgtt = saved_ppgtt;
> > > >> -
> > > >>          drm_dev_put(&dev_priv->drm);
> > > >>
> > > >>          return err;
> > > >> @@ -1753,7 +1749,7 @@ int i915_gem_huge_page_live_selftests(struct
> > > drm_i915_private *dev_priv)
> > > >>          struct i915_gem_context *ctx;
> > > >>          int err;
> > > >>
> > > >> -       if (!USES_PPGTT(dev_priv)) {
> > > >> +       if (!HAS_PPGTT(dev_priv)) {
> > > >>                  pr_info("PPGTT not supported, skipping live-selftests\n");
> > > >>                  return 0;
> > > >>          }
> > > >> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> > > b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> > > >> index 76df25aa90c9..913c0f83f86a 100644
> > > >> --- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> > > >> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> > > >> @@ -535,7 +535,6 @@ static int igt_ctx_exec(void *arg)
> > > >>          IGT_TIMEOUT(end_time);
> > > >>          LIST_HEAD(objects);
> > > >>          unsigned long ncontexts, ndwords, dw;
> > > >> -       bool first_shared_gtt = true;
> > > >>          int err = -ENODEV;
> > > >>
> > > >>          /*
> > > >> @@ -561,12 +560,7 @@ static int igt_ctx_exec(void *arg)
> > > >>                  struct i915_gem_context *ctx;
> > > >>                  unsigned int id;
> > > >>
> > > >> -               if (first_shared_gtt) {
> > > >> -                       ctx = __create_hw_context(i915, file->driver_priv);
> > > >> -                       first_shared_gtt = false;
> > > >> -               } else {
> > > >> -                       ctx = i915_gem_create_context(i915, file->driver_priv);
> > > >> -               }
> > > >> +               ctx = i915_gem_create_context(i915, file->driver_priv);
> > > >>                  if (IS_ERR(ctx)) {
> > > >>                          err = PTR_ERR(ctx);
> > > >>                          goto out_unlock;
> > > >> @@ -865,33 +859,6 @@ static int igt_switch_to_kernel_context(void
> > > *arg)
> > > >>          return err;
> > > >>   }
> > > >>
> > > >> -static int fake_aliasing_ppgtt_enable(struct drm_i915_private *i915)
> > > >> -{
> > > >> -       struct drm_i915_gem_object *obj;
> > > >> -       int err;
> > > >> -
> > > >> -       err = i915_gem_init_aliasing_ppgtt(i915);
> > > >> -       if (err)
> > > >> -               return err;
> > > >> -
> > > >> -       list_for_each_entry(obj, &i915->mm.bound_list, mm.link) {
> > > >> -               struct i915_vma *vma;
> > > >> -
> > > >> -               vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
> > > >> -               if (IS_ERR(vma))
> > > >> -                       continue;
> > > >> -
> > > >> -               vma->flags &= ~I915_VMA_LOCAL_BIND;
> > > >> -       }
> > > >> -
> > > >> -       return 0;
> > > >> -}
> > > >> -
> > > >> -static void fake_aliasing_ppgtt_disable(struct drm_i915_private *i915)
> > > >> -{
> > > >> -       i915_gem_fini_aliasing_ppgtt(i915);
> > > >> -}
> > > >> -
> > > >>   int i915_gem_context_mock_selftests(void)
> > > >>   {
> > > >>          static const struct i915_subtest tests[] = {
> > > >> @@ -918,31 +885,9 @@ int i915_gem_context_live_selftests(struct
> > > drm_i915_private *dev_priv)
> > > >>                  SUBTEST(igt_ctx_exec),
> > > >>                  SUBTEST(igt_ctx_readonly),
> > > >>          };
> > > >> -       bool fake_alias = false;
> > > >> -       int err;
> > > >>
> > > >>          if (i915_terminally_wedged(&dev_priv->gpu_error))
> > > >>                  return 0;
> > > >>
> > > >> -       /* Install a fake aliasing gtt for exercise */
> > > >> -       if (USES_PPGTT(dev_priv) && !dev_priv->mm.aliasing_ppgtt) {
> > > >> -               mutex_lock(&dev_priv->drm.struct_mutex);
> > > >> -               err = fake_aliasing_ppgtt_enable(dev_priv);
> > > >> -               mutex_unlock(&dev_priv->drm.struct_mutex);
> > > >> -               if (err)
> > > >> -                       return err;
> > > >> -
> > > >> -               GEM_BUG_ON(!dev_priv->mm.aliasing_ppgtt);
> > > >> -               fake_alias = true;
> > > >> -       }
> > > >> -
> > > >> -       err = i915_subtests(tests, dev_priv);
> > > >> -
> > > >> -       if (fake_alias) {
> > > >> -               mutex_lock(&dev_priv->drm.struct_mutex);
> > > >> -               fake_aliasing_ppgtt_disable(dev_priv);
> > > >> -               mutex_unlock(&dev_priv->drm.struct_mutex);
> > > >> -       }
> > > >> -
> > > >> -       return err;
> > > >> +       return i915_subtests(tests, dev_priv);
> > > >>   }
> > > >> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
> > > b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
> > > >> index 128ad1cf0647..4365979d8222 100644
> > > >> --- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
> > > >> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
> > > >> @@ -351,7 +351,7 @@ static int igt_evict_contexts(void *arg)
> > > >>           * where the GTT space of the request is separate from the GGTT
> > > >>           * allocation required to build the request.
> > > >>           */
> > > >> -       if (!USES_FULL_PPGTT(i915))
> > > >> +       if (!HAS_FULL_PPGTT(i915))
> > > >>                  return 0;
> > > >>
> > > >>          mutex_lock(&i915->drm.struct_mutex);
> > > >> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> > > b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> > > >> index 8e2e269db97e..17b5aaaa7a50 100644
> > > >> --- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> > > >> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> > > >> @@ -153,7 +153,7 @@ static int igt_ppgtt_alloc(void *arg)
> > > >>
> > > >>          /* Allocate a ppggt and try to fill the entire range */
> > > >>
> > > >> -       if (!USES_PPGTT(dev_priv))
> > > >> +       if (!HAS_PPGTT(dev_priv))
> > > >>                  return 0;
> > > >>
> > > >>          ppgtt = __hw_ppgtt_create(dev_priv);
> > > >> @@ -1001,7 +1001,7 @@ static int exercise_ppgtt(struct
> > > drm_i915_private *dev_priv,
> > > >>          IGT_TIMEOUT(end_time);
> > > >>          int err;
> > > >>
> > > >> -       if (!USES_FULL_PPGTT(dev_priv))
> > > >> +       if (!HAS_FULL_PPGTT(dev_priv))
> > > >>                  return 0;
> > > >>
> > > >>          file = mock_file(dev_priv);
> > > >> --
> > > >> 2.19.0
> > > >>

-- 
Open Source Technology Center, Intel ltd.

$gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827

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^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v4] drm/i915: Remove i915.enable_ppgtt override
  2018-10-08  9:53         ` Zhenyu Wang
@ 2018-10-08 13:58           ` Wang, Zhi A
  2018-10-09  2:15             ` Zhenyu Wang
  0 siblings, 1 reply; 24+ messages in thread
From: Wang, Zhi A @ 2018-10-08 13:58 UTC (permalink / raw)
  To: Zhenyu Wang, Joonas Lahtinen; +Cc: Auld, Matthew, intel-gfx

Thanks for pointing this. My bad.

I take a look on the code and it looks like the GVT-g context is now quite similar with the kernel context except the force single submission and ring buffer size. (When we upstream the code, there was no kernel context at that time. :/) Now there is already one API for single submission. If we can introduce another one to configure the ring buffer size. Then maybe we can remove the *create_gvt() in i915_gem_context.c and used kernel context instead.

Feel free to drop comments. :)

Thanks,
Zhi.

-----Original Message-----
From: Zhenyu Wang [mailto:zhenyuw@linux.intel.com] 
Sent: Monday, October 8, 2018 12:54 PM
To: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: He, Min <min.he@intel.com>; Wang, Zhi A <zhi.a.wang@intel.com>; intel-gfx@lists.freedesktop.org; Chris Wilson <chris@chris-wilson.co.uk>; Zhenyu Wang <zhenyuw@linux.intel.com>; Auld, Matthew <matthew.auld@intel.com>
Subject: Re: [PATCH v4] drm/i915: Remove i915.enable_ppgtt override

On 2018.09.26 11:02:15 +0300, Joonas Lahtinen wrote:
> Quoting He, Min (2018-09-26 04:06:25)
> > No. We changed to full 48bit ppgtt long time ago. :)
> 
> So would that mean the change is OK to do?

Looks that one unfortunately caused gvt regression, gvt context has no i915 managed i915_hw_ppgtt but only shadowed one, so need to check if ppgtt is valid before access.

> 
> Acked-by from you, Zhi, would be good to have for documentation 
> purposes in that case :)
> 
> Regards, Joonas
> 
> > 
> > > -----Original Message-----
> > > From: Wang, Zhi A
> > > Sent: Wednesday, September 26, 2018 2:01 AM
> > > To: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>; Chris 
> > > Wilson <chris@chris-wilson.co.uk>; 
> > > intel-gfx@lists.freedesktop.org; Zhenyu Wang 
> > > <zhenyuw@linux.intel.com>
> > > Cc: Auld, Matthew <matthew.auld@intel.com>; He, Min 
> > > <min.he@intel.com>
> > > Subject: Re: [PATCH v4] drm/i915: Remove i915.enable_ppgtt 
> > > override
> > > 
> > > Hi Min:
> > > 
> > > I remembered the IOTG guest kernel is using aliasing-ppgtt in the 
> > > last technical sharing (probably I didn't remember it correctly). 
> > > Can you confirm?
> > > 
> > > Also, thanks Joonas for the reminding. :)
> > > 
> > > thanks,
> > > Zhi.
> > > 
> > > On 09/25/18 09:22, Joonas Lahtinen wrote:
> > > > + Zhi and Zhenyu
> > > >
> > > > For me the patch looks ok.
> > > >
> > > > It refuses to load GVT on systems where 48-bit is not supported, 
> > > > for not worsening the system security when virtualization is 
> > > > enabled (as anybody would probably expect virtualization to improve that). Please see code.
> > > >
> > > > Do we have such systems in the wild? Should we instruct the user 
> > > > to updating the hypervisor to specific kernel version when they 
> > > > hit the error?
> > > >
> > > > Regards, Joonas
> > > >
> > > > Quoting Chris Wilson (2018-09-25 14:48:20)
> > > >> Now that we are confident in providing full-ppgtt where 
> > > >> supported, remove the ability to override the context isolation.
> > > >>
> > > >> v2: Remove faked aliasing-ppgtt for testing as it no longer is accepted.
> > > >> v3: s/USES/HAS/ to match usage and reject attempts to load the 
> > > >> module
> > > on
> > > >> old GVT-g setups that do not provide support for full-ppgtt.
> > > >>
> > > >> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > >> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > > >> Cc: Matthew Auld <matthew.auld@intel.com>
> > > >> ---
> > > >>   drivers/gpu/drm/i915/i915_drv.c               | 22 +++--
> > > >>   drivers/gpu/drm/i915/i915_drv.h               | 14 +--
> > > >>   drivers/gpu/drm/i915/i915_gem_context.c       |  2 +-
> > > >>   drivers/gpu/drm/i915/i915_gem_gtt.c           | 88 ++-----------------
> > > >>   drivers/gpu/drm/i915/i915_gpu_error.c         |  4 +-
> > > >>   drivers/gpu/drm/i915/i915_params.c            |  4 -
> > > >>   drivers/gpu/drm/i915/i915_params.h            |  1 -
> > > >>   drivers/gpu/drm/i915/i915_pci.c               | 17 ++--
> > > >>   drivers/gpu/drm/i915/intel_device_info.c      |  6 ++
> > > >>   drivers/gpu/drm/i915/intel_device_info.h      | 11 ++-
> > > >>   drivers/gpu/drm/i915/intel_lrc.c              | 13 ++-
> > > >>   drivers/gpu/drm/i915/selftests/huge_pages.c   | 12 +--
> > > >>   .../gpu/drm/i915/selftests/i915_gem_context.c | 59 +------------
> > > >>   .../gpu/drm/i915/selftests/i915_gem_evict.c   |  2 +-
> > > >>   drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |  4 +-
> > > >>   15 files changed, 62 insertions(+), 197 deletions(-)
> > > >>
> > > >> diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > > b/drivers/gpu/drm/i915/i915_drv.c
> > > >> index 44e2c0f5ec50..3efbbc71c3b4 100644
> > > >> --- a/drivers/gpu/drm/i915/i915_drv.c
> > > >> +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > >> @@ -345,7 +345,7 @@ static int i915_getparam_ioctl(struct 
> > > >> drm_device
> > > *dev, void *data,
> > > >>                  value = HAS_WT(dev_priv);
> > > >>                  break;
> > > >>          case I915_PARAM_HAS_ALIASING_PPGTT:
> > > >> -               value = USES_PPGTT(dev_priv);
> > > >> +               value = INTEL_PPGTT(dev_priv);
> > > >>                  break;
> > > >>          case I915_PARAM_HAS_SEMAPHORES:
> > > >>                  value = HAS_LEGACY_SEMAPHORES(dev_priv); @@ 
> > > >> -1049,17 +1049,6 @@ static void i915_driver_cleanup_mmio(struct
> > > drm_i915_private *dev_priv)
> > > >>
> > > >>   static void intel_sanitize_options(struct drm_i915_private *dev_priv)
> > > >>   {
> > > >> -       /*
> > > >> -        * i915.enable_ppgtt is read-only, so do an early pass to validate the
> > > >> -        * user's requested state against the hardware/driver capabilities.
> > > We
> > > >> -        * do this now so that we can print out any log messages once rather
> > > >> -        * than every time we check intel_enable_ppgtt().
> > > >> -        */
> > > >> -       i915_modparams.enable_ppgtt =
> > > >> -               intel_sanitize_enable_ppgtt(dev_priv,
> > > >> -                                           i915_modparams.enable_ppgtt);
> > > >> -       DRM_DEBUG_DRIVER("ppgtt mode: %i\n",
> > > i915_modparams.enable_ppgtt);
> > > >> -
> > > >>          intel_gvt_sanitize_options(dev_priv);
> > > >>   }
> > > >>
> > > >> @@ -1374,6 +1363,15 @@ static int i915_driver_init_hw(struct
> > > drm_i915_private *dev_priv)
> > > >>
> > > >>          
> > > >> intel_device_info_runtime_init(mkwrite_device_info(dev_priv));
> > > >>
> > > >> +       if (HAS_PPGTT(dev_priv)) {
> > > >> +               if (intel_vgpu_active(dev_priv) &&
> > > >> +                   !intel_vgpu_has_full_48bit_ppgtt(dev_priv)) {
> > > >> +                       i915_report_error(dev_priv,
> > > >> +                                         "incompatible vGPU 
> > > >> + found, support for isolated
> > > ppGTT required\n");
> > > >> +                       return -ENXIO;
> > > >> +               }
> > > >> +       }
> > > >> +
> > > >>          intel_sanitize_options(dev_priv);
> > > >>
> > > >>          i915_perf_init(dev_priv); diff --git 
> > > >> a/drivers/gpu/drm/i915/i915_drv.h
> > > b/drivers/gpu/drm/i915/i915_drv.h
> > > >> index 8624b4bdc242..f28b3c2a3cd2 100644
> > > >> --- a/drivers/gpu/drm/i915/i915_drv.h
> > > >> +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > >> @@ -2593,9 +2593,14 @@ intel_info(const struct drm_i915_private
> > > *dev_priv)
> > > >>
> > > >>   #define HAS_EXECLISTS(dev_priv)
> > > HAS_LOGICAL_RING_CONTEXTS(dev_priv)
> > > >>
> > > >> -#define USES_PPGTT(dev_priv)           (i915_modparams.enable_ppgtt)
> > > >> -#define USES_FULL_PPGTT(dev_priv)
> > > (i915_modparams.enable_ppgtt >= 2)
> > > >> -#define USES_FULL_48BIT_PPGTT(dev_priv)
> > > (i915_modparams.enable_ppgtt == 3)
> > > >> +#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt) 
> > > >> +#define HAS_PPGTT(dev_priv) \
> > > >> +       (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE) #define 
> > > >> +HAS_FULL_PPGTT(dev_priv) \
> > > >> +       (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL) #define 
> > > >> +HAS_FULL_48BIT_PPGTT(dev_priv) \
> > > >> +       (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL_4LVL)
> > > >> +
> > > >>   #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
> > > >>          GEM_BUG_ON((sizes) == 0); \
> > > >>          ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \ @@ 
> > > >> -2743,9 +2748,6 @@ intel_ggtt_update_needs_vtd_wa(struct
> > > drm_i915_private *dev_priv)
> > > >>          return IS_BROXTON(dev_priv) && intel_vtd_active();
> > > >>   }
> > > >>
> > > >> -int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
> > > >> -                               int enable_ppgtt);
> > > >> -
> > > >>   /* i915_drv.c */
> > > >>   void __printf(3, 4)
> > > >>   __i915_printk(struct drm_i915_private *dev_priv, const char 
> > > >> *level, diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
> > > b/drivers/gpu/drm/i915/i915_gem_context.c
> > > >> index f772593b99ab..15c92f75b1b8 100644
> > > >> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> > > >> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> > > >> @@ -414,7 +414,7 @@ i915_gem_create_context(struct
> > > drm_i915_private *dev_priv,
> > > >>          if (IS_ERR(ctx))
> > > >>                  return ctx;
> > > >>
> > > >> -       if (USES_FULL_PPGTT(dev_priv)) {
> > > >> +       if (HAS_FULL_PPGTT(dev_priv)) {
> > > >>                  struct i915_hw_ppgtt *ppgtt;
> > > >>
> > > >>                  ppgtt = i915_ppgtt_create(dev_priv, 
> > > >> file_priv); diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > >> index f6c7ab413081..c9363504949f 100644
> > > >> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > >> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > >> @@ -133,55 +133,6 @@ static inline void 
> > > >> i915_ggtt_invalidate(struct
> > > drm_i915_private *i915)
> > > >>          i915->ggtt.invalidate(i915);
> > > >>   }
> > > >>
> > > >> -int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
> > > >> -                               int enable_ppgtt)
> > > >> -{
> > > >> -       bool has_full_ppgtt;
> > > >> -       bool has_full_48bit_ppgtt;
> > > >> -
> > > >> -       if (!dev_priv->info.has_aliasing_ppgtt)
> > > >> -               return 0;
> > > >> -
> > > >> -       has_full_ppgtt = dev_priv->info.has_full_ppgtt;
> > > >> -       has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt;
> > > >> -
> > > >> -       if (intel_vgpu_active(dev_priv)) {
> > > >> -               /* GVT-g has no support for 32bit ppgtt */
> > > >> -               has_full_ppgtt = false;
> > > >> -               has_full_48bit_ppgtt =
> > > intel_vgpu_has_full_48bit_ppgtt(dev_priv);
> > > >> -       }
> > > >> -
> > > >> -       /*
> > > >> -        * We don't allow disabling PPGTT for gen8+ as it's a requirement for
> > > >> -        * execlists, the sole mechanism available to submit work.
> > > >> -        */
> > > >> -       if (enable_ppgtt == 0 && !HAS_EXECLISTS(dev_priv))
> > > >> -               return 0;
> > > >> -
> > > >> -       if (enable_ppgtt == 1)
> > > >> -               return 1;
> > > >> -
> > > >> -       if (enable_ppgtt == 2 && has_full_ppgtt)
> > > >> -               return 2;
> > > >> -
> > > >> -       if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
> > > >> -               return 3;
> > > >> -
> > > >> -       /* Disable ppgtt on SNB if VT-d is on. */
> > > >> -       if (IS_GEN6(dev_priv) && intel_vtd_active()) {
> > > >> -               DRM_INFO("Disabling PPGTT because VT-d is on\n");
> > > >> -               return 0;
> > > >> -       }
> > > >> -
> > > >> -       if (has_full_48bit_ppgtt)
> > > >> -               return 3;
> > > >> -
> > > >> -       if (has_full_ppgtt)
> > > >> -               return 2;
> > > >> -
> > > >> -       return 1;
> > > >> -}
> > > >> -
> > > >>   static int ppgtt_bind_vma(struct i915_vma *vma,
> > > >>                            enum i915_cache_level cache_level,
> > > >>                            u32 unused) @@ -1647,7 +1598,7 @@ 
> > > >> static struct i915_hw_ppgtt
> > > *gen8_ppgtt_create(struct drm_i915_private *i915)
> > > >>          ppgtt->vm.i915 = i915;
> > > >>          ppgtt->vm.dma = &i915->drm.pdev->dev;
> > > >>
> > > >> -       ppgtt->vm.total = USES_FULL_48BIT_PPGTT(i915) ?
> > > >> +       ppgtt->vm.total = HAS_FULL_48BIT_PPGTT(i915) ?
> > > >>                  1ULL << 48 :
> > > >>                  1ULL << 32;
> > > >>
> > > >> @@ -1782,19 +1733,6 @@ static inline void gen6_write_pde(const 
> > > >> struct
> > > gen6_hw_ppgtt *ppgtt,
> > > >>                    ppgtt->pd_addr + pde);
> > > >>   }
> > > >>
> > > >> -static void gen8_ppgtt_enable(struct drm_i915_private 
> > > >> *dev_priv) -{
> > > >> -       struct intel_engine_cs *engine;
> > > >> -       enum intel_engine_id id;
> > > >> -
> > > >> -       for_each_engine(engine, dev_priv, id) {
> > > >> -               u32 four_level = USES_FULL_48BIT_PPGTT(dev_priv) ?
> > > >> -                                GEN8_GFX_PPGTT_48B : 0;
> > > >> -               I915_WRITE(RING_MODE_GEN7(engine),
> > > >> -                          _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
> > > >> -       }
> > > >> -}
> > > >> -
> > > >>   static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv)
> > > >>   {
> > > >>          struct intel_engine_cs *engine; @@ -1834,7 +1772,8 @@ 
> > > >> static void gen6_ppgtt_enable(struct
> > > drm_i915_private *dev_priv)
> > > >>          ecochk = I915_READ(GAM_ECOCHK);
> > > >>          I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
> > > ECOCHK_PPGTT_CACHE64B);
> > > >>
> > > >> -       I915_WRITE(GFX_MODE,
> > > _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
> > > >> +       if (HAS_PPGTT(dev_priv)) /* may be disabled for VT-d */
> > > >> +               I915_WRITE(GFX_MODE,
> > > _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
> > > >>   }
> > > >>
> > > >>   /* PPGTT support for Sandybdrige/Gen6 and later */ @@ 
> > > >> -2237,23 +2176,10 @@ int i915_ppgtt_init_hw(struct
> > > drm_i915_private *dev_priv)
> > > >>   {
> > > >>          gtt_write_workarounds(dev_priv);
> > > >>
> > > >> -       /* In the case of execlists, PPGTT is enabled by the context descriptor
> > > >> -        * and the PDPs are contained within the context itself.  We don't
> > > >> -        * need to do anything here. */
> > > >> -       if (HAS_LOGICAL_RING_CONTEXTS(dev_priv))
> > > >> -               return 0;
> > > >> -
> > > >> -       if (!USES_PPGTT(dev_priv))
> > > >> -               return 0;
> > > >> -
> > > >>          if (IS_GEN6(dev_priv))
> > > >>                  gen6_ppgtt_enable(dev_priv);
> > > >>          else if (IS_GEN7(dev_priv))
> > > >>                  gen7_ppgtt_enable(dev_priv);
> > > >> -       else if (INTEL_GEN(dev_priv) >= 8)
> > > >> -               gen8_ppgtt_enable(dev_priv);
> > > >> -       else
> > > >> -               MISSING_CASE(INTEL_GEN(dev_priv));
> > > >>
> > > >>          return 0;
> > > >>   }
> > > >> @@ -2952,7 +2878,7 @@ int i915_gem_init_ggtt(struct 
> > > >> drm_i915_private
> > > *dev_priv)
> > > >>          /* And finally clear the reserved guard page */
> > > >>          ggtt->vm.clear_range(&ggtt->vm, ggtt->vm.total - 
> > > >> PAGE_SIZE,
> > > PAGE_SIZE);
> > > >>
> > > >> -       if (USES_PPGTT(dev_priv) && !USES_FULL_PPGTT(dev_priv)) {
> > > >> +       if (INTEL_PPGTT(dev_priv) == INTEL_PPGTT_ALIASING) {
> > > >>                  ret = i915_gem_init_aliasing_ppgtt(dev_priv);
> > > >>                  if (ret)
> > > >>                          goto err; @@ -3275,7 +3201,7 @@ static 
> > > >> void bdw_setup_private_ppat(struct
> > > intel_ppat *ppat)
> > > >>          ppat->match = bdw_private_pat_match;
> > > >>          ppat->clear_value = GEN8_PPAT_WB | GEN8_PPAT_LLCELLC |
> > > GEN8_PPAT_AGE(3);
> > > >>
> > > >> -       if (!USES_PPGTT(ppat->i915)) {
> > > >> +       if (!HAS_PPGTT(ppat->i915)) {
> > > >>                  /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
> > > >>                   * so RTL will always use the value corresponding to
> > > >>                   * pat_sel = 000".
> > > >> @@ -3402,7 +3328,7 @@ static int gen8_gmch_probe(struct 
> > > >> i915_ggtt
> > > *ggtt)
> > > >>          ggtt->vm.cleanup = gen6_gmch_remove;
> > > >>          ggtt->vm.insert_page = gen8_ggtt_insert_page;
> > > >>          ggtt->vm.clear_range = nop_clear_range;
> > > >> -       if (!USES_FULL_PPGTT(dev_priv) ||
> > > intel_scanout_needs_vtd_wa(dev_priv))
> > > >> +       if (intel_scanout_needs_vtd_wa(dev_priv))
> > > >>                  ggtt->vm.clear_range = gen8_ggtt_clear_range;
> > > >>
> > > >>          ggtt->vm.insert_entries = gen8_ggtt_insert_entries; @@ 
> > > >> -3609,7 +3535,7 @@ int i915_ggtt_init_hw(struct 
> > > >> drm_i915_private
> > > *dev_priv)
> > > >>          /* Only VLV supports read-only GGTT mappings */
> > > >>          ggtt->vm.has_read_only = IS_VALLEYVIEW(dev_priv);
> > > >>
> > > >> -       if (!HAS_LLC(dev_priv) && !USES_PPGTT(dev_priv))
> > > >> +       if (!HAS_LLC(dev_priv) && !HAS_PPGTT(dev_priv))
> > > >>                  ggtt->vm.mm.color_adjust = i915_gtt_color_adjust;
> > > >>          mutex_unlock(&dev_priv->drm.struct_mutex);
> > > >>
> > > >> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
> > > b/drivers/gpu/drm/i915/i915_gpu_error.c
> > > >> index 2835cacd0d08..3d5554f14dfd 100644
> > > >> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> > > >> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> > > >> @@ -474,7 +474,7 @@ static void error_print_engine(struct
> > > drm_i915_error_state_buf *m,
> > > >>                          err_printf(m, "  SYNC_2: 0x%08x\n",
> > > >>                                     ee->semaphore_mboxes[2]);
> > > >>          }
> > > >> -       if (USES_PPGTT(m->i915)) {
> > > >> +       if (HAS_PPGTT(m->i915)) {
> > > >>                  err_printf(m, "  GFX_MODE: 0x%08x\n", 
> > > >> ee->vm_info.gfx_mode);
> > > >>
> > > >>                  if (INTEL_GEN(m->i915) >= 8) { @@ -1230,7 
> > > >> +1230,7 @@ static void
> > > error_record_engine_registers(struct i915_gpu_state *error,
> > > >>          ee->reset_count = i915_reset_engine_count(&dev_priv->gpu_error,
> > > >>                                                    engine);
> > > >>
> > > >> -       if (USES_PPGTT(dev_priv)) {
> > > >> +       if (HAS_PPGTT(dev_priv)) {
> > > >>                  int i;
> > > >>
> > > >>                  ee->vm_info.gfx_mode =
> > > I915_READ(RING_MODE_GEN7(engine));
> > > >> diff --git a/drivers/gpu/drm/i915/i915_params.c
> > > b/drivers/gpu/drm/i915/i915_params.c
> > > >> index 295e981e4a39..bd6bd8879cab 100644
> > > >> --- a/drivers/gpu/drm/i915/i915_params.c
> > > >> +++ b/drivers/gpu/drm/i915/i915_params.c
> > > >> @@ -82,10 +82,6 @@ i915_param_named_unsafe(enable_hangcheck,
> > > bool, 0644,
> > > >>          "WARNING: Disabling this can cause system wide hangs. "
> > > >>          "(default: true)");
> > > >>
> > > >> -i915_param_named_unsafe(enable_ppgtt, int, 0400,
> > > >> -       "Override PPGTT usage. "
> > > >> -       "(-1=auto [default], 0=disabled, 1=aliasing, 2=full, 3=full with
> > > extended address space)");
> > > >> -
> > > >>   i915_param_named_unsafe(enable_psr, int, 0600,
> > > >>          "Enable PSR "
> > > >>          "(0=disabled, 1=enabled) "
> > > >> diff --git a/drivers/gpu/drm/i915/i915_params.h
> > > b/drivers/gpu/drm/i915/i915_params.h
> > > >> index 6c4d4a21474b..7e56c516c815 100644
> > > >> --- a/drivers/gpu/drm/i915/i915_params.h
> > > >> +++ b/drivers/gpu/drm/i915/i915_params.h
> > > >> @@ -41,7 +41,6 @@ struct drm_printer;
> > > >>          param(int, vbt_sdvo_panel_type, -1) \
> > > >>          param(int, enable_dc, -1) \
> > > >>          param(int, enable_fbc, -1) \
> > > >> -       param(int, enable_ppgtt, -1) \
> > > >>          param(int, enable_psr, -1) \
> > > >>          param(int, disable_power_well, -1) \
> > > >>          param(int, enable_ips, 1) \ diff --git 
> > > >> a/drivers/gpu/drm/i915/i915_pci.c
> > > b/drivers/gpu/drm/i915/i915_pci.c
> > > >> index d6f7b9fe1d26..eeec902896b9 100644
> > > >> --- a/drivers/gpu/drm/i915/i915_pci.c
> > > >> +++ b/drivers/gpu/drm/i915/i915_pci.c
> > > >> @@ -252,7 +252,7 @@ static const struct intel_device_info
> > > intel_ironlake_m_info = {
> > > >>          .has_llc = 1, \
> > > >>          .has_rc6 = 1, \
> > > >>          .has_rc6p = 1, \
> > > >> -       .has_aliasing_ppgtt = 1, \
> > > >> +       .ppgtt = INTEL_PPGTT_ALIASING, \
> > > >>          GEN_DEFAULT_PIPEOFFSETS, \
> > > >>          GEN_DEFAULT_PAGE_SIZES, \
> > > >>          CURSOR_OFFSETS
> > > >> @@ -297,8 +297,7 @@ static const struct intel_device_info
> > > intel_sandybridge_m_gt2_info = {
> > > >>          .has_llc = 1, \
> > > >>          .has_rc6 = 1, \
> > > >>          .has_rc6p = 1, \
> > > >> -       .has_aliasing_ppgtt = 1, \
> > > >> -       .has_full_ppgtt = 1, \
> > > >> +       .ppgtt = INTEL_PPGTT_FULL, \
> > > >>          GEN_DEFAULT_PIPEOFFSETS, \
> > > >>          GEN_DEFAULT_PAGE_SIZES, \
> > > >>          IVB_CURSOR_OFFSETS
> > > >> @@ -351,8 +350,7 @@ static const struct intel_device_info
> > > intel_valleyview_info = {
> > > >>          .has_rc6 = 1,
> > > >>          .has_gmch_display = 1,
> > > >>          .has_hotplug = 1,
> > > >> -       .has_aliasing_ppgtt = 1,
> > > >> -       .has_full_ppgtt = 1,
> > > >> +       .ppgtt = INTEL_PPGTT_FULL,
> > > >>          .has_snoop = true,
> > > >>          .has_coherent_ggtt = false,
> > > >>          .ring_mask = RENDER_RING | BSD_RING | BLT_RING, @@ 
> > > >> -399,7 +397,7 @@ static const struct intel_device_info
> > > intel_haswell_gt3_info = {
> > > >>          .page_sizes = I915_GTT_PAGE_SIZE_4K | \
> > > >>                        I915_GTT_PAGE_SIZE_2M, \
> > > >>          .has_logical_ring_contexts = 1, \
> > > >> -       .has_full_48bit_ppgtt = 1, \
> > > >> +       .ppgtt = INTEL_PPGTT_FULL_4LVL, \
> > > >>          .has_64bit_reloc = 1, \
> > > >>          .has_reset_engine = 1
> > > >>
> > > >> @@ -443,8 +441,7 @@ static const struct intel_device_info
> > > intel_cherryview_info = {
> > > >>          .has_rc6 = 1,
> > > >>          .has_logical_ring_contexts = 1,
> > > >>          .has_gmch_display = 1,
> > > >> -       .has_aliasing_ppgtt = 1,
> > > >> -       .has_full_ppgtt = 1,
> > > >> +       .ppgtt = INTEL_PPGTT_FULL,
> > > >>          .has_reset_engine = 1,
> > > >>          .has_snoop = true,
> > > >>          .has_coherent_ggtt = false, @@ -518,9 +515,7 @@ static 
> > > >> const struct intel_device_info
> > > intel_skylake_gt4_info = {
> > > >>          .has_logical_ring_contexts = 1, \
> > > >>          .has_logical_ring_preemption = 1, \
> > > >>          .has_guc = 1, \
> > > >> -       .has_aliasing_ppgtt = 1, \
> > > >> -       .has_full_ppgtt = 1, \
> > > >> -       .has_full_48bit_ppgtt = 1, \
> > > >> +       .ppgtt = INTEL_PPGTT_FULL_4LVL, \
> > > >>          .has_reset_engine = 1, \
> > > >>          .has_snoop = true, \
> > > >>          .has_coherent_ggtt = false, \ diff --git 
> > > >> a/drivers/gpu/drm/i915/intel_device_info.c
> > > b/drivers/gpu/drm/i915/intel_device_info.c
> > > >> index 0ef0c6448d53..a841d181efd3 100644
> > > >> --- a/drivers/gpu/drm/i915/intel_device_info.c
> > > >> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > > >> @@ -26,6 +26,7 @@
> > > >>
> > > >>   #include "intel_device_info.h"
> > > >>   #include "i915_drv.h"
> > > >> +#include "i915_vgpu.h"
> > > >>
> > > >>   #define PLATFORM_NAME(x) [INTEL_##x] = #x
> > > >>   static const char * const platform_names[] = { @@ -851,6 
> > > >> +852,11 @@ void intel_device_info_runtime_init(struct
> > > intel_device_info *info)
> > > >>          else if (INTEL_GEN(dev_priv) >= 11)
> > > >>                  gen11_sseu_info_init(dev_priv);
> > > >>
> > > >> +       if (IS_GEN6(dev_priv) && intel_vtd_active()) {
> > > >> +               DRM_INFO("Disabling ppGTT for VT-d support\n");
> > > >> +               info->ppgtt = INTEL_PPGTT_NONE;
> > > >> +       }
> > > >> +
> > > >>          /* Initialize command stream timestamp frequency */
> > > >>          info->cs_timestamp_frequency_khz =
> > > read_timestamp_frequency(dev_priv);
> > > >>   }
> > > >> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> > > b/drivers/gpu/drm/i915/intel_device_info.h
> > > >> index 6eecd64734d5..6bab97687328 100644
> > > >> --- a/drivers/gpu/drm/i915/intel_device_info.h
> > > >> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > > >> @@ -74,21 +74,25 @@ enum intel_platform {
> > > >>          INTEL_MAX_PLATFORMS
> > > >>   };
> > > >>
> > > >> +enum intel_ppgtt {
> > > >> +       INTEL_PPGTT_NONE = 0,
> > > >> +       INTEL_PPGTT_ALIASING,
> > > >> +       INTEL_PPGTT_FULL,
> > > >> +       INTEL_PPGTT_FULL_4LVL,
> > > >> +};
> > > >> +
> > > >>   #define DEV_INFO_FOR_EACH_FLAG(func) \
> > > >>          func(is_mobile); \
> > > >>          func(is_lp); \
> > > >>          func(is_alpha_support); \
> > > >>          /* Keep has_* in alphabetical order */ \
> > > >>          func(has_64bit_reloc); \
> > > >> -       func(has_aliasing_ppgtt); \
> > > >>          func(has_csr); \
> > > >>          func(has_ddi); \
> > > >>          func(has_dp_mst); \
> > > >>          func(has_reset_engine); \
> > > >>          func(has_fbc); \
> > > >>          func(has_fpga_dbg); \
> > > >> -       func(has_full_ppgtt); \
> > > >> -       func(has_full_48bit_ppgtt); \
> > > >>          func(has_gmch_display); \
> > > >>          func(has_guc); \
> > > >>          func(has_guc_ct); \
> > > >> @@ -154,6 +158,7 @@ struct intel_device_info {
> > > >>          enum intel_platform platform;
> > > >>          u32 platform_mask;
> > > >>
> > > >> +       enum intel_ppgtt ppgtt;
> > > >>          unsigned int page_sizes; /* page sizes supported by 
> > > >> the HW */
> > > >>
> > > >>          u32 display_mmio_offset; diff --git 
> > > >> a/drivers/gpu/drm/i915/intel_lrc.c
> > > b/drivers/gpu/drm/i915/intel_lrc.c
> > > >> index 4b28225320ff..3836a8a3761a 100644
> > > >> --- a/drivers/gpu/drm/i915/intel_lrc.c
> > > >> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> > > >> @@ -418,9 +418,8 @@ execlists_update_context_pdps(struct
> > > i915_hw_ppgtt *ppgtt, u32 *reg_state)
> > > >>
> > > >>   static u64 execlists_update_context(struct i915_request *rq)
> > > >>   {
> > > >> +       struct i915_hw_ppgtt *ppgtt = rq->gem_context->ppgtt;
> > > >>          struct intel_context *ce = rq->hw_context;
> > > >> -       struct i915_hw_ppgtt *ppgtt =
> > > >> -               rq->gem_context->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
> > > >>          u32 *reg_state = ce->lrc_reg_state;
> > > >>
> > > >>          reg_state[CTX_RING_TAIL+1] = 
> > > >> intel_ring_set_tail(rq->ring, rq->tail); @@ -1376,7 +1375,7 @@ 
> > > >> execlists_context_pin(struct intel_engine_cs
> > > *engine,
> > > >>          struct intel_context *ce = to_intel_context(ctx, 
> > > >> engine);
> > > >>
> > > >>          lockdep_assert_held(&ctx->i915->drm.struct_mutex);
> > > >> -       GEM_BUG_ON(!(ctx->ppgtt ?: ctx->i915->mm.aliasing_ppgtt));
> > > >> +       GEM_BUG_ON(!ctx->ppgtt);
> > > >>
> > > >>          if (likely(ce->pin_count++))
> > > >>                  return ce;
> > > >> @@ -2031,8 +2030,7 @@ static int gen8_emit_bb_start(struct
> > > i915_request *rq,
> > > >>           * it is unsafe in case of lite-restore (because the ctx is
> > > >>           * not idle). PML4 is allocated during ppgtt init so this is
> > > >>           * not needed in 48-bit.*/
> > > >> -       if (rq->gem_context->ppgtt &&
> > > >> -           (intel_engine_flag(rq->engine) & rq->gem_context->ppgtt-
> > > >pd_dirty_rings) &&
> > > >> +       if ((intel_engine_flag(rq->engine) & 
> > > >> + rq->gem_context->ppgtt-
> > > >pd_dirty_rings) &&
> > > >>              !i915_vm_is_48bit(&rq->gem_context->ppgtt->vm) &&
> > > >>              !intel_vgpu_active(rq->i915)) {
> > > >>                  ret = intel_logical_ring_emit_pdps(rq); @@ 
> > > >> -2634,7 +2632,6 @@ static void execlists_init_reg_state(u32 *regs,
> > > >>                                       struct intel_ring *ring)
> > > >>   {
> > > >>          struct drm_i915_private *dev_priv = engine->i915;
> > > >> -       struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: dev_priv-
> > > >mm.aliasing_ppgtt;
> > > >>          u32 base = engine->mmio_base;
> > > >>          bool rcs = engine->class == RENDER_CLASS;
> > > >>
> > > >> @@ -2706,12 +2703,12 @@ static void execlists_init_reg_state(u32 *regs,
> > > >>          CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 
> > > >> 0),
> > > 0);
> > > >>          CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 
> > > >> 0),
> > > 0);
> > > >>
> > > >> -       if (i915_vm_is_48bit(&ppgtt->vm)) {
> > > >> +       if (i915_vm_is_48bit(&ctx->ppgtt->vm)) {
> > > >>                  /* 64b PPGTT (48bit canonical)
> > > >>                   * PDP0_DESCRIPTOR contains the base address to PML4 and
> > > >>                   * other PDP Descriptors are ignored.
> > > >>                   */
> > > >> -               ASSIGN_CTX_PML4(ppgtt, regs);
> > > >> +               ASSIGN_CTX_PML4(ctx->ppgtt, regs);
> > > >>          }
> > > >>
> > > >>          if (rcs) {
> > > >> diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c
> > > b/drivers/gpu/drm/i915/selftests/huge_pages.c
> > > >> index 8d03f64eabd7..09ea65a29d98 100644
> > > >> --- a/drivers/gpu/drm/i915/selftests/huge_pages.c
> > > >> +++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
> > > >> @@ -1436,7 +1436,7 @@ static int igt_ppgtt_pin_update(void *arg)
> > > >>           * huge-gtt-pages.
> > > >>           */
> > > >>
> > > >> -       if (!USES_FULL_48BIT_PPGTT(dev_priv)) {
> > > >> +       if (!HAS_FULL_48BIT_PPGTT(dev_priv)) {
> > > >>                  pr_info("48b PPGTT not supported, skipping\n");
> > > >>                  return 0;
> > > >>          }
> > > >> @@ -1687,10 +1687,9 @@ int
> > > i915_gem_huge_page_mock_selftests(void)
> > > >>                  SUBTEST(igt_mock_ppgtt_huge_fill),
> > > >>                  SUBTEST(igt_mock_ppgtt_64K),
> > > >>          };
> > > >> -       int saved_ppgtt = i915_modparams.enable_ppgtt;
> > > >>          struct drm_i915_private *dev_priv;
> > > >> -       struct pci_dev *pdev;
> > > >>          struct i915_hw_ppgtt *ppgtt;
> > > >> +       struct pci_dev *pdev;
> > > >>          int err;
> > > >>
> > > >>          dev_priv = mock_gem_device(); @@ -1698,7 +1697,7 @@ 
> > > >> int i915_gem_huge_page_mock_selftests(void)
> > > >>                  return -ENOMEM;
> > > >>
> > > >>          /* Pretend to be a device which supports the 48b PPGTT */
> > > >> -       i915_modparams.enable_ppgtt = 3;
> > > >> +       mkwrite_device_info(dev_priv)->ppgtt = 
> > > >> + INTEL_PPGTT_FULL_4LVL;
> > > >>
> > > >>          pdev = dev_priv->drm.pdev;
> > > >>          dma_coerce_mask_and_coherent(&pdev->dev, 
> > > >> DMA_BIT_MASK(39)); @@ -1731,9 +1730,6 @@ int 
> > > >> i915_gem_huge_page_mock_selftests(void)
> > > >>
> > > >>   out_unlock:
> > > >>          mutex_unlock(&dev_priv->drm.struct_mutex);
> > > >> -
> > > >> -       i915_modparams.enable_ppgtt = saved_ppgtt;
> > > >> -
> > > >>          drm_dev_put(&dev_priv->drm);
> > > >>
> > > >>          return err;
> > > >> @@ -1753,7 +1749,7 @@ int 
> > > >> i915_gem_huge_page_live_selftests(struct
> > > drm_i915_private *dev_priv)
> > > >>          struct i915_gem_context *ctx;
> > > >>          int err;
> > > >>
> > > >> -       if (!USES_PPGTT(dev_priv)) {
> > > >> +       if (!HAS_PPGTT(dev_priv)) {
> > > >>                  pr_info("PPGTT not supported, skipping live-selftests\n");
> > > >>                  return 0;
> > > >>          }
> > > >> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> > > b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> > > >> index 76df25aa90c9..913c0f83f86a 100644
> > > >> --- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> > > >> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> > > >> @@ -535,7 +535,6 @@ static int igt_ctx_exec(void *arg)
> > > >>          IGT_TIMEOUT(end_time);
> > > >>          LIST_HEAD(objects);
> > > >>          unsigned long ncontexts, ndwords, dw;
> > > >> -       bool first_shared_gtt = true;
> > > >>          int err = -ENODEV;
> > > >>
> > > >>          /*
> > > >> @@ -561,12 +560,7 @@ static int igt_ctx_exec(void *arg)
> > > >>                  struct i915_gem_context *ctx;
> > > >>                  unsigned int id;
> > > >>
> > > >> -               if (first_shared_gtt) {
> > > >> -                       ctx = __create_hw_context(i915, file->driver_priv);
> > > >> -                       first_shared_gtt = false;
> > > >> -               } else {
> > > >> -                       ctx = i915_gem_create_context(i915, file->driver_priv);
> > > >> -               }
> > > >> +               ctx = i915_gem_create_context(i915, 
> > > >> + file->driver_priv);
> > > >>                  if (IS_ERR(ctx)) {
> > > >>                          err = PTR_ERR(ctx);
> > > >>                          goto out_unlock; @@ -865,33 +859,6 @@ 
> > > >> static int igt_switch_to_kernel_context(void
> > > *arg)
> > > >>          return err;
> > > >>   }
> > > >>
> > > >> -static int fake_aliasing_ppgtt_enable(struct drm_i915_private 
> > > >> *i915) -{
> > > >> -       struct drm_i915_gem_object *obj;
> > > >> -       int err;
> > > >> -
> > > >> -       err = i915_gem_init_aliasing_ppgtt(i915);
> > > >> -       if (err)
> > > >> -               return err;
> > > >> -
> > > >> -       list_for_each_entry(obj, &i915->mm.bound_list, mm.link) {
> > > >> -               struct i915_vma *vma;
> > > >> -
> > > >> -               vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
> > > >> -               if (IS_ERR(vma))
> > > >> -                       continue;
> > > >> -
> > > >> -               vma->flags &= ~I915_VMA_LOCAL_BIND;
> > > >> -       }
> > > >> -
> > > >> -       return 0;
> > > >> -}
> > > >> -
> > > >> -static void fake_aliasing_ppgtt_disable(struct 
> > > >> drm_i915_private *i915) -{
> > > >> -       i915_gem_fini_aliasing_ppgtt(i915);
> > > >> -}
> > > >> -
> > > >>   int i915_gem_context_mock_selftests(void)
> > > >>   {
> > > >>          static const struct i915_subtest tests[] = { @@ 
> > > >> -918,31 +885,9 @@ int i915_gem_context_live_selftests(struct
> > > drm_i915_private *dev_priv)
> > > >>                  SUBTEST(igt_ctx_exec),
> > > >>                  SUBTEST(igt_ctx_readonly),
> > > >>          };
> > > >> -       bool fake_alias = false;
> > > >> -       int err;
> > > >>
> > > >>          if (i915_terminally_wedged(&dev_priv->gpu_error))
> > > >>                  return 0;
> > > >>
> > > >> -       /* Install a fake aliasing gtt for exercise */
> > > >> -       if (USES_PPGTT(dev_priv) && !dev_priv->mm.aliasing_ppgtt) {
> > > >> -               mutex_lock(&dev_priv->drm.struct_mutex);
> > > >> -               err = fake_aliasing_ppgtt_enable(dev_priv);
> > > >> -               mutex_unlock(&dev_priv->drm.struct_mutex);
> > > >> -               if (err)
> > > >> -                       return err;
> > > >> -
> > > >> -               GEM_BUG_ON(!dev_priv->mm.aliasing_ppgtt);
> > > >> -               fake_alias = true;
> > > >> -       }
> > > >> -
> > > >> -       err = i915_subtests(tests, dev_priv);
> > > >> -
> > > >> -       if (fake_alias) {
> > > >> -               mutex_lock(&dev_priv->drm.struct_mutex);
> > > >> -               fake_aliasing_ppgtt_disable(dev_priv);
> > > >> -               mutex_unlock(&dev_priv->drm.struct_mutex);
> > > >> -       }
> > > >> -
> > > >> -       return err;
> > > >> +       return i915_subtests(tests, dev_priv);
> > > >>   }
> > > >> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
> > > b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
> > > >> index 128ad1cf0647..4365979d8222 100644
> > > >> --- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
> > > >> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
> > > >> @@ -351,7 +351,7 @@ static int igt_evict_contexts(void *arg)
> > > >>           * where the GTT space of the request is separate from the GGTT
> > > >>           * allocation required to build the request.
> > > >>           */
> > > >> -       if (!USES_FULL_PPGTT(i915))
> > > >> +       if (!HAS_FULL_PPGTT(i915))
> > > >>                  return 0;
> > > >>
> > > >>          mutex_lock(&i915->drm.struct_mutex);
> > > >> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> > > b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> > > >> index 8e2e269db97e..17b5aaaa7a50 100644
> > > >> --- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> > > >> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> > > >> @@ -153,7 +153,7 @@ static int igt_ppgtt_alloc(void *arg)
> > > >>
> > > >>          /* Allocate a ppggt and try to fill the entire range 
> > > >> */
> > > >>
> > > >> -       if (!USES_PPGTT(dev_priv))
> > > >> +       if (!HAS_PPGTT(dev_priv))
> > > >>                  return 0;
> > > >>
> > > >>          ppgtt = __hw_ppgtt_create(dev_priv); @@ -1001,7 
> > > >> +1001,7 @@ static int exercise_ppgtt(struct
> > > drm_i915_private *dev_priv,
> > > >>          IGT_TIMEOUT(end_time);
> > > >>          int err;
> > > >>
> > > >> -       if (!USES_FULL_PPGTT(dev_priv))
> > > >> +       if (!HAS_FULL_PPGTT(dev_priv))
> > > >>                  return 0;
> > > >>
> > > >>          file = mock_file(dev_priv);
> > > >> --
> > > >> 2.19.0
> > > >>

--
Open Source Technology Center, Intel ltd.

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^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v4] drm/i915: Remove i915.enable_ppgtt override
  2018-10-08 13:58           ` Wang, Zhi A
@ 2018-10-09  2:15             ` Zhenyu Wang
  2018-10-09  6:55               ` Zhi Wang
  0 siblings, 1 reply; 24+ messages in thread
From: Zhenyu Wang @ 2018-10-09  2:15 UTC (permalink / raw)
  To: Wang, Zhi A; +Cc: Auld, Matthew, intel-gfx


[-- Attachment #1.1: Type: text/plain, Size: 832 bytes --]

On 2018.10.08 13:58:25 +0000, Wang, Zhi A wrote:
> Thanks for pointing this. My bad.
> 
> I take a look on the code and it looks like the GVT-g context is now quite similar with the kernel context except the force single submission and ring buffer size. (When we upstream the code, there was no kernel context at that time. :/) Now there is already one API for single submission. If we can introduce another one to configure the ring buffer size. Then maybe we can remove the *create_gvt() in i915_gem_context.c and used kernel context instead.
> 
> Feel free to drop comments. :)
>

For ppgtt, you'd better change to use i915 ppgtt interface to handle
shadow pages, then gvt context would be much like normal one.

-- 
Open Source Technology Center, Intel ltd.

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^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v4] drm/i915: Remove i915.enable_ppgtt override
  2018-10-09  2:15             ` Zhenyu Wang
@ 2018-10-09  6:55               ` Zhi Wang
  2018-10-09  7:35                 ` Chris Wilson
  0 siblings, 1 reply; 24+ messages in thread
From: Zhi Wang @ 2018-10-09  6:55 UTC (permalink / raw)
  To: Zhenyu Wang; +Cc: Auld, Matthew, intel-gfx

This is ideal and had been discussed in the beginning of upstream. 
Mostly people didn't like this approach because it needs to modify i915 
ppgtt code a lot and have to introduce a lot gvt-only code in i915 ppgtt.

The idea of the series of Joonas patch is to make PPGTT selection 
per-platform. I guess that's the reason why he removed that check.
 From his idea, there shouldn't be any platform which has execlist 
support, but is still using aliasing PPGTT.

So it looks like there two approaches.

One is following the idea of this patch series: Platform with execlist 
shouldn't touch aliasing PPGTT anymore, which needs GVT-g to create a 
dummy PPGTT instance. (One dummy PPGTT instance for the architectural 
design)

Another one is keeping the check as workaround like before.

I would like to choose a but b is also reasonable to me.

Thanks,
Zhi.

On 10/08/18 22:15, Zhenyu Wang wrote:
> On 2018.10.08 13:58:25 +0000, Wang, Zhi A wrote:
>> Thanks for pointing this. My bad.
>>
>> I take a look on the code and it looks like the GVT-g context is now quite similar with the kernel context except the force single submission and ring buffer size. (When we upstream the code, there was no kernel context at that time. :/) Now there is already one API for single submission. If we can introduce another one to configure the ring buffer size. Then maybe we can remove the *create_gvt() in i915_gem_context.c and used kernel context instead.
>>
>> Feel free to drop comments. :)
>>
> 
> For ppgtt, you'd better change to use i915 ppgtt interface to handle
> shadow pages, then gvt context would be much like normal one.
> 
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^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH v4] drm/i915: Remove i915.enable_ppgtt override
  2018-10-09  6:55               ` Zhi Wang
@ 2018-10-09  7:35                 ` Chris Wilson
  0 siblings, 0 replies; 24+ messages in thread
From: Chris Wilson @ 2018-10-09  7:35 UTC (permalink / raw)
  To: Zhenyu Wang, Zhi Wang; +Cc: intel-gfx, Auld, Matthew

Quoting Zhi Wang (2018-10-09 07:55:00)
> This is ideal and had been discussed in the beginning of upstream. 
> Mostly people didn't like this approach because it needs to modify i915 
> ppgtt code a lot and have to introduce a lot gvt-only code in i915 ppgtt.
> 
> The idea of the series of Joonas patch is to make PPGTT selection 
> per-platform. I guess that's the reason why he removed that check.
>  From his idea, there shouldn't be any platform which has execlist 
> support, but is still using aliasing PPGTT.
> 
> So it looks like there two approaches.
> 
> One is following the idea of this patch series: Platform with execlist 
> shouldn't touch aliasing PPGTT anymore, which needs GVT-g to create a 
> dummy PPGTT instance. (One dummy PPGTT instance for the architectural 
> design)
> 
> Another one is keeping the check as workaround like before.
> 
> I would like to choose a but b is also reasonable to me.

Creating a stub ppgtt to isolate the gvt context from the rest of the
system is very simple and ensures that (at least from our perspective)
the PDP always point to valid entries and not whatever lies at 0.
-Chris
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^ permalink raw reply	[flat|nested] 24+ messages in thread
end of thread, other threads:[~2018-10-09  7:35 UTC | newest]

Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-09-25 11:48 [PATCH v4] drm/i915: Remove i915.enable_ppgtt override Chris Wilson
2018-09-25 12:06 ` ✗ Fi.CI.SPARSE: warning for " Patchwork
2018-09-25 12:28 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-09-25 13:14 ` Patchwork
2018-09-25 13:22 ` [PATCH v4] " Joonas Lahtinen
2018-09-25 18:01   ` Zhi Wang
2018-09-26  1:06     ` He, Min
2018-09-26  8:02       ` Joonas Lahtinen
2018-09-26 12:29         ` Zhi Wang
2018-10-08  9:53         ` Zhenyu Wang
2018-10-08 13:58           ` Wang, Zhi A
2018-10-09  2:15             ` Zhenyu Wang
2018-10-09  6:55               ` Zhi Wang
2018-10-09  7:35                 ` Chris Wilson
2018-09-25 13:27 ` Joonas Lahtinen
2018-09-26 13:16   ` Joonas Lahtinen
2018-09-26 20:12 ` [PATCH v5] " Chris Wilson
2018-09-27  8:20   ` Joonas Lahtinen
2018-09-27  8:55     ` Chris Wilson
2018-09-27 10:57       ` Joonas Lahtinen
2018-09-27 11:07         ` Chris Wilson
2018-09-26 21:34 ` ✗ Fi.CI.SPARSE: warning for drm/i915: Remove i915.enable_ppgtt override (rev2) Patchwork
2018-09-26 21:55 ` ✓ Fi.CI.BAT: success " Patchwork
2018-09-27  3:00 ` ✓ Fi.CI.IGT: " Patchwork

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