From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alexandre Belloni Date: Tue, 25 Sep 2018 17:15:05 +0200 Subject: [U-Boot] [PATCH] DW SPI: Allow to overload the management of the external CS In-Reply-To: <20180925131731.20933-1-gregory.clement@bootlin.com> References: <20180925131731.20933-1-gregory.clement@bootlin.com> Message-ID: <20180925151505.GB3112@piout.net> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi, On 25/09/2018 15:17:31+0200, Gregory CLEMENT wrote: > On some platforms, as the Ocelot ones, when wanting to control the CS > through software, it is not possible to do it through the GPIO > controller. Indeed, this signal is managed through a dedicated range of > registers inside the SoC.. > > By declaring the external_cs_manage function as weak, it is possible to > manage the CS at platform level and then using the appropriate registers. > > Signed-off-by: Gregory CLEMENT > --- > drivers/spi/designware_spi.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c > index d8b73ea326..fe6e753bff 100644 > --- a/drivers/spi/designware_spi.c > +++ b/drivers/spi/designware_spi.c > @@ -334,7 +334,13 @@ static int poll_transfer(struct dw_spi_priv *priv) > return 0; > } > > -static void external_cs_manage(struct udevice *dev, bool on) > +/* > + * We define external_cs_manage function as 'weak' as some targets > + * (like OCELOT) don't control the external CS pin using a GPIO MSCC Ocelot maybe? > + * controller. These SoCs use specific registers to controll by ^ control > + * software the SPI pins (and especially the CS). > + */ > +__weak void external_cs_manage(struct udevice *dev, bool on) > { > #if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD) > struct dw_spi_priv *priv = dev_get_priv(dev->parent); > -- > 2.19.0 > -- Alexandre Belloni, Bootlin Embedded Linux and Kernel engineering https://bootlin.com