[PATCH v3 0/4] R-Car D3/E3 display DT enablement

[PATCH v3 0/4] R-Car D3/E3 display DT enablement

[Laurent Pinchart]

Hello,

The patches in this series enable display support for the D3 and E3 SoCs, on
the Draak and Ebisu boards respectively. They were previously part of the
"[PATCH v2 00/16] R-Car D3/E3 display support (with LVDS PLL)" series, and
have been split out now that the DT bindings have been accepted andon their
way to v4.20 through the DRM tree, along with the code changes.

Compared to v2, the VSPI MSTP clock index has been fixed, and the
patches rebased on top of Simon's latest devel branch.

Simon, could you please consider this as an update for v4.20 ?

Kieran Bingham (1):
  arm64: dts: renesas: r8a77995: Add LVDS support

Laurent Pinchart (2):
  arm64: dts: renesas: r8a77990: Add display output support
  arm64: dts: renesas: r8a77990: ebisu: Enable VGA and HDMI outputs

Ulrich Hecht (1):
  arm64: dts: renesas: r8a77995: draak: Enable HDMI display output

 arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 162 ++++++++++++++++++++++++
 arch/arm64/boot/dts/renesas/r8a77990.dtsi      | 167 +++++++++++++++++++++++++
 arch/arm64/boot/dts/renesas/r8a77995-draak.dts |  98 ++++++++++++++-
 arch/arm64/boot/dts/renesas/r8a77995.dtsi      |  56 +++++++++
 4 files changed, 482 insertions(+), 1 deletion(-)

-- 
Regards,

Laurent Pinchart

[PATCH v3 1/4] arm64: dts: renesas: r8a77990: Add display output support

[Laurent Pinchart]

The R8A77990 (E3) platform has one RGB output and two LVDS outputs
connected to the DU. Add the DT nodes for the DU, LVDS encoders and
supporting VSP and FCP.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
---
Changes since v2:

- Fixed VSPI clock index
---
 arch/arm64/boot/dts/renesas/r8a77990.dtsi | 167 ++++++++++++++++++++++++++++++
 1 file changed, 167 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index 0c726ea5d315..9509dc05665f 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -843,6 +843,82 @@
 			resets = <&cpg 408>;
 		};
 
+		vspb0: vsp@fe960000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfe960000 0 0x8000>;
+			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 626>;
+			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+			resets = <&cpg 626>;
+			renesas,fcp = <&fcpvb0>;
+		};
+
+		fcpvb0: fcp@fe96f000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xfe96f000 0 0x200>;
+			clocks = <&cpg CPG_MOD 607>;
+			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+			resets = <&cpg 607>;
+			iommus = <&ipmmu_vp0 5>;
+		};
+
+		vspi0: vsp@fe9a0000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfe9a0000 0 0x8000>;
+			interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 631>;
+			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+			resets = <&cpg 631>;
+			renesas,fcp = <&fcpvi0>;
+		};
+
+		fcpvi0: fcp@fe9af000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xfe9af000 0 0x200>;
+			clocks = <&cpg CPG_MOD 611>;
+			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+			resets = <&cpg 611>;
+			iommus = <&ipmmu_vp0 8>;
+		};
+
+		vspd0: vsp@fea20000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfea20000 0 0x7000>;
+			interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 623>;
+			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+			resets = <&cpg 623>;
+			renesas,fcp = <&fcpvd0>;
+		};
+
+		fcpvd0: fcp@fea27000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xfea27000 0 0x200>;
+			clocks = <&cpg CPG_MOD 603>;
+			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+			resets = <&cpg 603>;
+			iommus = <&ipmmu_vi0 8>;
+		};
+
+		vspd1: vsp@fea28000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfea28000 0 0x7000>;
+			interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 622>;
+			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+			resets = <&cpg 622>;
+			renesas,fcp = <&fcpvd1>;
+		};
+
+		fcpvd1: fcp@fea2f000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xfea2f000 0 0x200>;
+			clocks = <&cpg CPG_MOD 602>;
+			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+			resets = <&cpg 602>;
+			iommus = <&ipmmu_vi0 9>;
+		};
+
 		csi40: csi2@feaa0000 {
 			compatible = "renesas,r8a77990-csi2", "renesas,rcar-gen3-csi2";
 			reg = <0 0xfeaa0000 0 0x10000>;
@@ -874,6 +950,97 @@
 			};
 		};
 
+		du: display@feb00000 {
+			compatible = "renesas,du-r8a77990";
+			reg = <0 0xfeb00000 0 0x80000>;
+			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 724>,
+				 <&cpg CPG_MOD 723>;
+			clock-names = "du.0", "du.1";
+			vsps = <&vspd0 0 &vspd1 0>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					du_out_rgb: endpoint {
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					du_out_lvds0: endpoint {
+						remote-endpoint = <&lvds0_in>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+					du_out_lvds1: endpoint {
+						remote-endpoint = <&lvds1_in>;
+					};
+				};
+			};
+		};
+
+		lvds0: lvds-encoder@feb90000 {
+			compatible = "renesas,r8a77990-lvds";
+			reg = <0 0xfeb90000 0 0x20>;
+			clocks = <&cpg CPG_MOD 727>;
+			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+			resets = <&cpg 727>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					lvds0_in: endpoint {
+						remote-endpoint = <&du_out_lvds0>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					lvds0_out: endpoint {
+					};
+				};
+			};
+		};
+
+		lvds1: lvds-encoder@feb90100 {
+			compatible = "renesas,r8a77990-lvds";
+			reg = <0 0xfeb90100 0 0x20>;
+			clocks = <&cpg CPG_MOD 727>;
+			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+			resets = <&cpg 726>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					lvds1_in: endpoint {
+						remote-endpoint = <&du_out_lvds1>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					lvds1_out: endpoint {
+					};
+				};
+			};
+		};
+
 		prr: chipid@fff00044 {
 			compatible = "renesas,prr";
 			reg = <0 0xfff00044 0 4>;
-- 
Regards,

Laurent Pinchart

[PATCH v3 2/4] arm64: dts: renesas: r8a77995: Add LVDS support

[Laurent Pinchart]

From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>

The r8a77995 D3 platform has 2 LVDS channels connected to the DU.

Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
[uli: moved lvds* into the soc node, added PM domains, resets]
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
---
 arch/arm64/boot/dts/renesas/r8a77995.dtsi | 56 +++++++++++++++++++++++++++++++
 1 file changed, 56 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index 89a04a4496fd..214f4954b321 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -972,12 +972,68 @@
 				port@1 {
 					reg = <1>;
 					du_out_lvds0: endpoint {
+						remote-endpoint = <&lvds0_in>;
 					};
 				};
 
 				port@2 {
 					reg = <2>;
 					du_out_lvds1: endpoint {
+						remote-endpoint = <&lvds1_in>;
+					};
+				};
+			};
+		};
+
+		lvds0: lvds-encoder@feb90000 {
+			compatible = "renesas,r8a77995-lvds";
+			reg = <0 0xfeb90000 0 0x20>;
+			clocks = <&cpg CPG_MOD 727>;
+			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+			resets = <&cpg 727>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					lvds0_in: endpoint {
+						remote-endpoint = <&du_out_lvds0>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					lvds0_out: endpoint {
+					};
+				};
+			};
+		};
+
+		lvds1: lvds-encoder@feb90100 {
+			compatible = "renesas,r8a77995-lvds";
+			reg = <0 0xfeb90100 0 0x20>;
+			clocks = <&cpg CPG_MOD 727>;
+			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+			resets = <&cpg 726>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					lvds1_in: endpoint {
+						remote-endpoint = <&du_out_lvds1>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					lvds1_out: endpoint {
 					};
 				};
 			};
-- 
Regards,

Laurent Pinchart

[PATCH v3 3/4] arm64: dts: renesas: r8a77990: ebisu: Enable VGA and HDMI outputs

[Laurent Pinchart]

Add the LVDS decoder, HDMI encoder, VGA encoder and HDMI and VGA
connectors, and wire up the display-related nodes with clocks, pinmux
and regulators.

The LVDS0 and LVDS1 encoders can use the DU_DOTCLKIN0, DU_DOTCLKIN1 and
EXTAL externals clocks. Two of them are provided to the SoC on the Ebisu
board, hook them up in DT.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
---
 arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 162 +++++++++++++++++++++++++
 1 file changed, 162 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
index fd60079169f6..f342dd85b152 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
@@ -51,6 +51,88 @@
 			};
 		};
 	};
+
+	hdmi-out {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_out: endpoint {
+				remote-endpoint = <&adv7511_out>;
+			};
+		};
+	};
+
+	lvds-decoder {
+		compatible = "thine,thc63lvd1024";
+		vcc-supply = <&reg_3p3v>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				thc63lvd1024_in: endpoint {
+					remote-endpoint = <&lvds0_out>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+				thc63lvd1024_out: endpoint {
+					remote-endpoint = <&adv7511_in>;
+				};
+			};
+		};
+	};
+
+	vga {
+		compatible = "vga-connector";
+
+		port {
+			vga_in: endpoint {
+				remote-endpoint = <&adv7123_out>;
+			};
+		};
+	};
+
+	vga-encoder {
+		compatible = "adi,adv7123";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				adv7123_in: endpoint {
+					remote-endpoint = <&du_out_rgb>;
+				};
+			};
+			port@1 {
+				reg = <1>;
+				adv7123_out: endpoint {
+					remote-endpoint = <&vga_in>;
+				};
+			};
+		};
+	};
+
+	reg_3p3v: regulator1 {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	x13_clk: x13 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <74250000>;
+	};
 };
 
 &avb {
@@ -86,6 +168,25 @@
 	};
 };
 
+&du {
+	pinctrl-0 = <&du_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	clocks = <&cpg CPG_MOD 724>,
+		 <&cpg CPG_MOD 723>,
+		 <&x13_clk>;
+	clock-names = "du.0", "du.1", "dclkin.0";
+
+	ports {
+		port@0 {
+			endpoint {
+				remote-endpoint = <&adv7123_in>;
+			};
+		};
+	};
+};
+
 &ehci0 {
 	status = "okay";
 };
@@ -97,6 +198,38 @@
 &i2c0 {
 	status = "okay";
 
+	hdmi-encoder@39 {
+		compatible = "adi,adv7511w";
+		reg = <0x39>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+
+		adi,input-depth = <8>;
+		adi,input-colorspace = "rgb";
+		adi,input-clock = "1x";
+		adi,input-style = <1>;
+		adi,input-justification = "evenly";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				adv7511_in: endpoint {
+					remote-endpoint = <&thc63lvd1024_out>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				adv7511_out: endpoint {
+					remote-endpoint = <&hdmi_con_out>;
+				};
+			};
+		};
+	};
+
 	video-receiver@70 {
 		compatible = "adi,adv7482";
 		reg = <0x70>;
@@ -137,6 +270,30 @@
 	};
 };
 
+&lvds0 {
+	status = "okay";
+
+	clocks = <&cpg CPG_MOD 727>,
+		 <&x13_clk>,
+		 <&extal_clk>;
+	clock-names = "fck", "dclkin.0", "extal";
+
+	ports {
+		port@1 {
+			lvds0_out: endpoint {
+				remote-endpoint = <&thc63lvd1024_in>;
+			};
+		};
+	};
+};
+
+&lvds1 {
+	clocks = <&cpg CPG_MOD 727>,
+		 <&x13_clk>,
+		 <&extal_clk>;
+	clock-names = "fck", "dclkin.0", "extal";
+};
+
 &ohci0 {
 	status = "okay";
 };
@@ -149,6 +306,11 @@
 		};
 	};
 
+	du_pins: du {
+		groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
+		function = "du";
+	};
+
 	pwm3_pins: pwm3 {
 		groups = "pwm3_b";
 		function = "pwm3";
-- 
Regards,

Laurent Pinchart

[PATCH v3 4/4] arm64: dts: renesas: r8a77995: draak: Enable HDMI display output

[Laurent Pinchart]

From: Ulrich Hecht <uli+renesas@fpond.eu>

Adds LVDS decoder, HDMI encoder and connector for the Draak board.

The LVDS0 and LVDS1 encoders can use the DU_DOTCLKIN0, DU_DOTCLKIN1 and
EXTAL externals clocks. Two of them are provided to the SoC on the Draak
board, hook them up in DT.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
---
 arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 98 +++++++++++++++++++++++++-
 1 file changed, 97 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
index e39b73005381..2405eaad0296 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
@@ -2,7 +2,7 @@
 /*
  * Device Tree Source for the Draak board
  *
- * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2016-2018 Renesas Electronics Corp.
  * Copyright (C) 2017 Glider bvba
  */
 
@@ -45,6 +45,41 @@
 		};
 	};
 
+	hdmi-out {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_out: endpoint {
+				remote-endpoint = <&adv7511_out>;
+			};
+		};
+	};
+
+	lvds-decoder {
+		compatible = "thine,thc63lvd1024";
+		vcc-supply = <&reg_3p3v>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				thc63lvd1024_in: endpoint {
+					remote-endpoint = <&lvds0_out>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+				thc63lvd1024_out: endpoint {
+					remote-endpoint = <&adv7511_in>;
+				};
+			};
+		};
+	};
+
 	memory@48000000 {
 		device_type = "memory";
 		/* first 128MB is reserved for secure area. */
@@ -190,6 +225,43 @@
 
 	};
 
+	hdmi-encoder@39 {
+		compatible = "adi,adv7511w";
+		reg = <0x39>, <0x3f>, <0x38>, <0x3c>;
+		reg-names = "main", "edid", "packet", "cec";
+		interrupt-parent = <&gpio1>;
+		interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
+
+		/* Depends on LVDS */
+		max-clock = <135000000>;
+		min-vrefresh = <50>;
+
+		adi,input-depth = <8>;
+		adi,input-colorspace = "rgb";
+		adi,input-clock = "1x";
+		adi,input-style = <1>;
+		adi,input-justification = "evenly";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				adv7511_in: endpoint {
+					remote-endpoint = <&thc63lvd1024_out>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				adv7511_out: endpoint {
+					remote-endpoint = <&hdmi_con_out>;
+				};
+			};
+		};
+	};
+
 	hdmi-decoder@4c {
 		compatible = "adi,adv7612";
 		reg = <0x4c>;
@@ -240,6 +312,30 @@
 	status = "okay";
 };
 
+&lvds0 {
+	status = "okay";
+
+	clocks = <&cpg CPG_MOD 727>,
+		 <&x12_clk>,
+		 <&extal_clk>;
+	clock-names = "fck", "dclkin.0", "extal";
+
+	ports {
+		port@1 {
+			lvds0_out: endpoint {
+				remote-endpoint = <&thc63lvd1024_in>;
+			};
+		};
+	};
+};
+
+&lvds1 {
+	clocks = <&cpg CPG_MOD 727>,
+		 <&x12_clk>,
+		 <&extal_clk>;
+	clock-names = "fck", "dclkin.0", "extal";
+};
+
 &ohci0 {
 	status = "okay";
 };
-- 
Regards,

Laurent Pinchart

Re: [PATCH v3 2/4] arm64: dts: renesas: r8a77995: Add LVDS support

[Sergei Shtylyov]

On 9/25/2018 7:33 PM, Laurent Pinchart wrote:

> From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
> 
> The r8a77995 D3 platform has 2 LVDS channels connected to the DU.
> 
> Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
> [uli: moved lvds* into the soc node, added PM domains, resets]
> Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
> ---
>   arch/arm64/boot/dts/renesas/r8a77995.dtsi | 56 +++++++++++++++++++++++++++++++
>   1 file changed, 56 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> index 89a04a4496fd..214f4954b321 100644
> --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> @@ -972,12 +972,68 @@
>   				port@1 {
>   					reg = <1>;
>   					du_out_lvds0: endpoint {
> +						remote-endpoint = <&lvds0_in>;
>   					};
>   				};
>   
>   				port@2 {
>   					reg = <2>;
>   					du_out_lvds1: endpoint {
> +						remote-endpoint = <&lvds1_in>;
> +					};
> +				};
> +			};
> +		};
> +
> +		lvds0: lvds-encoder@feb90000 {
> +			compatible = "renesas,r8a77995-lvds";
> +			reg = <0 0xfeb90000 0 0x20>;
> +			clocks = <&cpg CPG_MOD 727>;
> +			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
> +			resets = <&cpg 727>;
> +			status = "disabled";
> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				port@0 {
> +					reg = <0>;
> +					lvds0_in: endpoint {
> +						remote-endpoint = <&du_out_lvds0>;
> +					};
> +				};
> +
> +				port@1 {
> +					reg = <1>;
> +					lvds0_out: endpoint {
> +					};
> +				};
> +			};
> +		};
> +
> +		lvds1: lvds-encoder@feb90100 {
> +			compatible = "renesas,r8a77995-lvds";
> +			reg = <0 0xfeb90100 0 0x20>;
> +			clocks = <&cpg CPG_MOD 727>;

    Not 726?

> +			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
> +			resets = <&cpg 726>;

    ... like here?

[...]

MBR, Sergei

Re: [PATCH v3 2/4] arm64: dts: renesas: r8a77995: Add LVDS support

[Simon Horman]

On Wed, Sep 26, 2018 at 11:27:53AM +0300, Sergei Shtylyov wrote:
> On 9/25/2018 7:33 PM, Laurent Pinchart wrote:
> 
> > From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
> > 
> > The r8a77995 D3 platform has 2 LVDS channels connected to the DU.
> > 
> > Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
> > [uli: moved lvds* into the soc node, added PM domains, resets]
> > Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
> > Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
> > ---
> >   arch/arm64/boot/dts/renesas/r8a77995.dtsi | 56 +++++++++++++++++++++++++++++++
> >   1 file changed, 56 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> > index 89a04a4496fd..214f4954b321 100644
> > --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> > @@ -972,12 +972,68 @@
> >   				port@1 {
> >   					reg = <1>;
> >   					du_out_lvds0: endpoint {
> > +						remote-endpoint = <&lvds0_in>;
> >   					};
> >   				};
> >   				port@2 {
> >   					reg = <2>;
> >   					du_out_lvds1: endpoint {
> > +						remote-endpoint = <&lvds1_in>;
> > +					};
> > +				};
> > +			};
> > +		};
> > +
> > +		lvds0: lvds-encoder@feb90000 {
> > +			compatible = "renesas,r8a77995-lvds";
> > +			reg = <0 0xfeb90000 0 0x20>;
> > +			clocks = <&cpg CPG_MOD 727>;
> > +			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
> > +			resets = <&cpg 727>;
> > +			status = "disabled";
> > +
> > +			ports {
> > +				#address-cells = <1>;
> > +				#size-cells = <0>;
> > +
> > +				port@0 {
> > +					reg = <0>;
> > +					lvds0_in: endpoint {
> > +						remote-endpoint = <&du_out_lvds0>;
> > +					};
> > +				};
> > +
> > +				port@1 {
> > +					reg = <1>;
> > +					lvds0_out: endpoint {
> > +					};
> > +				};
> > +			};
> > +		};
> > +
> > +		lvds1: lvds-encoder@feb90100 {
> > +			compatible = "renesas,r8a77995-lvds";
> > +			reg = <0 0xfeb90100 0 0x20>;
> > +			clocks = <&cpg CPG_MOD 727>;
> 
>    Not 726?
> 
> > +			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
> > +			resets = <&cpg 726>;
> 
>    ... like here?

I believe that discussion was already had for v2 of the similar patch
for r8a77990 and that it is intentional.

Re: [PATCH v3 0/4] R-Car D3/E3 display DT enablement

[Simon Horman]

On Tue, Sep 25, 2018 at 07:33:33PM +0300, Laurent Pinchart wrote:
> Hello,
> 
> The patches in this series enable display support for the D3 and E3 SoCs, on
> the Draak and Ebisu boards respectively. They were previously part of the
> "[PATCH v2 00/16] R-Car D3/E3 display support (with LVDS PLL)" series, and
> have been split out now that the DT bindings have been accepted andon their
> way to v4.20 through the DRM tree, along with the code changes.
> 
> Compared to v2, the VSPI MSTP clock index has been fixed, and the
> patches rebased on top of Simon's latest devel branch.
> 
> Simon, could you please consider this as an update for v4.20 ?

Thanks, applied for v4.20.

Re: [PATCH v3 2/4] arm64: dts: renesas: r8a77995: Add LVDS support

[Sergei Shtylyov]

On 9/26/2018 12:13 PM, Simon Horman wrote:

>>> From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
>>>
>>> The r8a77995 D3 platform has 2 LVDS channels connected to the DU.
>>>
>>> Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
>>> [uli: moved lvds* into the soc node, added PM domains, resets]
>>> Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
>>> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
>>> Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
>>> ---
>>>    arch/arm64/boot/dts/renesas/r8a77995.dtsi | 56 +++++++++++++++++++++++++++++++
>>>    1 file changed, 56 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
>>> index 89a04a4496fd..214f4954b321 100644
>>> --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
>>> +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
>>> @@ -972,12 +972,68 @@
>>>    				port@1 {
>>>    					reg = <1>;
>>>    					du_out_lvds0: endpoint {
>>> +						remote-endpoint = <&lvds0_in>;
>>>    					};
>>>    				};
>>>    				port@2 {
>>>    					reg = <2>;
>>>    					du_out_lvds1: endpoint {
>>> +						remote-endpoint = <&lvds1_in>;
>>> +					};
>>> +				};
>>> +			};
>>> +		};
>>> +
>>> +		lvds0: lvds-encoder@feb90000 {
>>> +			compatible = "renesas,r8a77995-lvds";
>>> +			reg = <0 0xfeb90000 0 0x20>;
>>> +			clocks = <&cpg CPG_MOD 727>;
>>> +			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
>>> +			resets = <&cpg 727>;
>>> +			status = "disabled";
>>> +
>>> +			ports {
>>> +				#address-cells = <1>;
>>> +				#size-cells = <0>;
>>> +
>>> +				port@0 {
>>> +					reg = <0>;
>>> +					lvds0_in: endpoint {
>>> +						remote-endpoint = <&du_out_lvds0>;
>>> +					};
>>> +				};
>>> +
>>> +				port@1 {
>>> +					reg = <1>;
>>> +					lvds0_out: endpoint {
>>> +					};
>>> +				};
>>> +			};
>>> +		};
>>> +
>>> +		lvds1: lvds-encoder@feb90100 {
>>> +			compatible = "renesas,r8a77995-lvds";
>>> +			reg = <0 0xfeb90100 0 0x20>;
>>> +			clocks = <&cpg CPG_MOD 727>;
>>
>>     Not 726?
>>
>>> +			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
>>> +			resets = <&cpg 726>;
>>
>>     ... like here?
> 
> I believe that discussion was already had for v2 of the similar patch
> for r8a77990 and that it is intentional.

    Ah, sorry, missed that. Still looks like a documentation error... :-)

MBR, Sergei

Re: [PATCH v3 2/4] arm64: dts: renesas: r8a77995: Add LVDS support

[Simon Horman]

On Wed, Sep 26, 2018 at 12:46:12PM +0300, Sergei Shtylyov wrote:
> On 9/26/2018 12:13 PM, Simon Horman wrote:
> 
> > > > From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
> > > > 
> > > > The r8a77995 D3 platform has 2 LVDS channels connected to the DU.
> > > > 
> > > > Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
> > > > [uli: moved lvds* into the soc node, added PM domains, resets]
> > > > Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
> > > > Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > > > Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
> > > > ---
> > > >    arch/arm64/boot/dts/renesas/r8a77995.dtsi | 56 +++++++++++++++++++++++++++++++
> > > >    1 file changed, 56 insertions(+)
> > > > 
> > > > diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> > > > index 89a04a4496fd..214f4954b321 100644
> > > > --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> > > > +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> > > > @@ -972,12 +972,68 @@
> > > >    				port@1 {
> > > >    					reg = <1>;
> > > >    					du_out_lvds0: endpoint {
> > > > +						remote-endpoint = <&lvds0_in>;
> > > >    					};
> > > >    				};
> > > >    				port@2 {
> > > >    					reg = <2>;
> > > >    					du_out_lvds1: endpoint {
> > > > +						remote-endpoint = <&lvds1_in>;
> > > > +					};
> > > > +				};
> > > > +			};
> > > > +		};
> > > > +
> > > > +		lvds0: lvds-encoder@feb90000 {
> > > > +			compatible = "renesas,r8a77995-lvds";
> > > > +			reg = <0 0xfeb90000 0 0x20>;
> > > > +			clocks = <&cpg CPG_MOD 727>;
> > > > +			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
> > > > +			resets = <&cpg 727>;
> > > > +			status = "disabled";
> > > > +
> > > > +			ports {
> > > > +				#address-cells = <1>;
> > > > +				#size-cells = <0>;
> > > > +
> > > > +				port@0 {
> > > > +					reg = <0>;
> > > > +					lvds0_in: endpoint {
> > > > +						remote-endpoint = <&du_out_lvds0>;
> > > > +					};
> > > > +				};
> > > > +
> > > > +				port@1 {
> > > > +					reg = <1>;
> > > > +					lvds0_out: endpoint {
> > > > +					};
> > > > +				};
> > > > +			};
> > > > +		};
> > > > +
> > > > +		lvds1: lvds-encoder@feb90100 {
> > > > +			compatible = "renesas,r8a77995-lvds";
> > > > +			reg = <0 0xfeb90100 0 0x20>;
> > > > +			clocks = <&cpg CPG_MOD 727>;
> > > 
> > >     Not 726?
> > > 
> > > > +			power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
> > > > +			resets = <&cpg 726>;
> > > 
> > >     ... like here?
> > 
> > I believe that discussion was already had for v2 of the similar patch
> > for r8a77990 and that it is intentional.
> 
>    Ah, sorry, missed that. Still looks like a documentation error... :-)

Yes, that is my understanding too.

Re: [PATCH v3 4/4] arm64: dts: renesas: r8a77995: draak: Enable HDMI display output

[Geert Uytterhoeven]

Hi Laurent, Ulrich,

On Tue, Sep 25, 2018 at 6:34 PM Laurent Pinchart
<laurent.pinchart+renesas@ideasonboard.com> wrote:
> From: Ulrich Hecht <uli+renesas@fpond.eu>
>
> Adds LVDS decoder, HDMI encoder and connector for the Draak board.
>
> The LVDS0 and LVDS1 encoders can use the DU_DOTCLKIN0, DU_DOTCLKIN1 and
> EXTAL externals clocks. Two of them are provided to the SoC on the Draak
> board, hook them up in DT.
>
> Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org>

> --- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
> +++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts

> @@ -190,6 +225,43 @@
>
>         };
>
> +       hdmi-encoder@39 {
> +               compatible = "adi,adv7511w";
> +               reg = <0x39>, <0x3f>, <0x38>, <0x3c>;
> +               reg-names = "main", "edid", "packet", "cec";
> +               interrupt-parent = <&gpio1>;
> +               interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
> +
> +               /* Depends on LVDS */
> +               max-clock = <135000000>;
> +               min-vrefresh = <50>;

Where do these two come from? They fail to validate with commit
cfe34bb7a770c5d8 ("dt-bindings: drm: bridge: adi,adv7511.txt: convert
to yaml").
I can't find where it is used in the driver, nor in the driver history.
Perhaps it was set in some obscure place, and is no longer needed since
commit 67793bd3b3948dc8 ("drm/bridge: adv7511: Fix low refresh rate
selection")?

> +
> +               adi,input-depth = <8>;
> +               adi,input-colorspace = "rgb";
> +               adi,input-clock = "1x";
> +               adi,input-style = <1>;
> +               adi,input-justification = "evenly";

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v3 4/4] arm64: dts: renesas: r8a77995: draak: Enable HDMI display output

[Ulrich Hecht]

> On 06/18/2021 10:05 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Tue, Sep 25, 2018 at 6:34 PM Laurent Pinchart
> <laurent.pinchart+renesas@ideasonboard.com> wrote:
> > From: Ulrich Hecht <uli+renesas@fpond.eu>
> >
> > Adds LVDS decoder, HDMI encoder and connector for the Draak board.
> >
> > The LVDS0 and LVDS1 encoders can use the DU_DOTCLKIN0, DU_DOTCLKIN1 and
> > EXTAL externals clocks. Two of them are provided to the SoC on the Draak
> > board, hook them up in DT.
> >
> > Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
> > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
> 
> > --- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
> > +++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
> 
> > @@ -190,6 +225,43 @@
> >
> >         };
> >
> > +       hdmi-encoder@39 {
> > +               compatible = "adi,adv7511w";
> > +               reg = <0x39>, <0x3f>, <0x38>, <0x3c>;
> > +               reg-names = "main", "edid", "packet", "cec";
> > +               interrupt-parent = <&gpio1>;
> > +               interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
> > +
> > +               /* Depends on LVDS */
> > +               max-clock = <135000000>;
> > +               min-vrefresh = <50>;
> 
> Where do these two come from? They fail to validate with commit
> cfe34bb7a770c5d8 ("dt-bindings: drm: bridge: adi,adv7511.txt: convert
> to yaml").
> I can't find where it is used in the driver, nor in the driver history.

I have found a prototype patch in my archives that uses these properties. I guess the patch itself didn't make it into the final series, but the properties inadvertently did. I vaguely remember this was supposed to work around an issue with modes that use a higher clock than supported by one of the parts in the display pipeline.

I would say that if there are no issues with HDMI output, both the patch and the properties are obsolete.

For reference, this is the patch:

===snip===
From 8502e09a87a02216a195a985243e3e6567848154 Mon Sep 17 00:00:00 2001
From: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
Date: Thu, 7 Dec 2017 20:10:39 +0900
Subject: [PROTO][PATCH 05/10] drm/bridge: adv7511: Add max-clock, min-vrefresh
 options

This patch adds the option to specify a maximal clock and a minimal vertical
refresh rate.

Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
[uli: renamed properties, fixed transposed parsing]
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
---
 drivers/gpu/drm/bridge/adv7511/adv7511.h     |  7 +++++++
 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 22 ++++++++++++++++++++++
 2 files changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511.h b/drivers/gpu/drm/bridge/adv7511/adv7511.h
index 73d8ccb..7f29d4f 100644
--- a/drivers/gpu/drm/bridge/adv7511/adv7511.h
+++ b/drivers/gpu/drm/bridge/adv7511/adv7511.h
@@ -271,6 +271,8 @@ enum adv7511_sync_polarity {
  * @sync_pulse:			Select the sync pulse
  * @vsync_polarity:		vsync input signal configuration
  * @hsync_polarity:		hsync input signal configuration
+ * @min_vrefresh_option:	min vrefresh option
+ * @max_freq_option:		max frequency option
  */
 struct adv7511_link_config {
 	unsigned int input_color_depth;
@@ -285,6 +287,9 @@ struct adv7511_link_config {
 	enum adv7511_input_sync_pulse sync_pulse;
 	enum adv7511_sync_polarity vsync_polarity;
 	enum adv7511_sync_polarity hsync_polarity;
+
+	unsigned int min_vrefresh_option;
+	unsigned int max_freq_option;
 };
 
 /**
@@ -354,6 +359,8 @@ struct adv7511 {
 	enum adv7511_sync_polarity vsync_polarity;
 	enum adv7511_sync_polarity hsync_polarity;
 	bool rgb;
+	unsigned int min_vref;
+	unsigned int max_freq;
 
 	struct gpio_desc *gpio_pd;
 
diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
index 6437b87..2938b02 100644
--- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
+++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
@@ -323,6 +323,8 @@ static void adv7511_set_link_config(struct adv7511 *adv7511,
 	adv7511->hsync_polarity = config->hsync_polarity;
 	adv7511->vsync_polarity = config->vsync_polarity;
 	adv7511->rgb = config->input_colorspace == HDMI_COLORSPACE_RGB;
+	adv7511->min_vref = config->min_vrefresh_option;
+	adv7511->max_freq = config->max_freq_option;
 }
 
 static void __adv7511_power_on(struct adv7511 *adv7511)
@@ -660,6 +662,16 @@ static enum drm_mode_status adv7511_mode_valid(struct adv7511 *adv7511,
 	if (mode->clock > 165000)
 		return MODE_CLOCK_HIGH;
 
+	if (adv7511->max_freq) {
+		if (mode->clock > (adv7511->max_freq / 1000))
+			return MODE_CLOCK_HIGH;
+	}
+
+	if (adv7511->min_vref) {
+		if (drm_mode_vrefresh(mode) < adv7511->min_vref)
+			return MODE_BAD;
+	}
+
 	return MODE_OK;
 }
 
@@ -1074,6 +1086,16 @@ static int adv7511_parse_dt(struct device_node *np,
 	config->vsync_polarity = ADV7511_SYNC_POLARITY_PASSTHROUGH;
 	config->hsync_polarity = ADV7511_SYNC_POLARITY_PASSTHROUGH;
 
+	ret = of_property_read_u32(np, "max-clock",
+				   &config->max_freq_option);
+	if (ret < 0)
+		config->max_freq_option = 0;
+
+	ret = of_property_read_u32(np, "min-vrefresh",
+				   &config->min_vrefresh_option);
+	if (ret < 0)
+		config->min_vrefresh_option = 0;
+
 	return 0;
 }
 
-- 
2.7.4
===snip===

CU
Uli

Re: [PATCH v3 4/4] arm64: dts: renesas: r8a77995: draak: Enable HDMI display output

[Geert Uytterhoeven]

Hi Uli,

On Fri, Jun 18, 2021 at 2:01 PM Ulrich Hecht <uli@fpond.eu> wrote:
> > On 06/18/2021 10:05 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Tue, Sep 25, 2018 at 6:34 PM Laurent Pinchart
> > <laurent.pinchart+renesas@ideasonboard.com> wrote:
> > > From: Ulrich Hecht <uli+renesas@fpond.eu>
> > >
> > > Adds LVDS decoder, HDMI encoder and connector for the Draak board.
> > >
> > > The LVDS0 and LVDS1 encoders can use the DU_DOTCLKIN0, DU_DOTCLKIN1 and
> > > EXTAL externals clocks. Two of them are provided to the SoC on the Draak
> > > board, hook them up in DT.
> > >
> > > Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
> > > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > > Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
> >
> > > --- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
> > > +++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
> >
> > > @@ -190,6 +225,43 @@
> > >
> > >         };
> > >
> > > +       hdmi-encoder@39 {
> > > +               compatible = "adi,adv7511w";
> > > +               reg = <0x39>, <0x3f>, <0x38>, <0x3c>;
> > > +               reg-names = "main", "edid", "packet", "cec";
> > > +               interrupt-parent = <&gpio1>;
> > > +               interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
> > > +
> > > +               /* Depends on LVDS */
> > > +               max-clock = <135000000>;
> > > +               min-vrefresh = <50>;
> >
> > Where do these two come from? They fail to validate with commit
> > cfe34bb7a770c5d8 ("dt-bindings: drm: bridge: adi,adv7511.txt: convert
> > to yaml").
> > I can't find where it is used in the driver, nor in the driver history.
>
> I have found a prototype patch in my archives that uses these properties. I guess the patch itself didn't make it into the final series, but the properties inadvertently did. I vaguely remember this was supposed to work around an issue with modes that use a higher clock than supported by one of the parts in the display pipeline.

Thanks, I already suspected something like that...

> I would say that if there are no issues with HDMI output, both the patch and the properties are obsolete.

Anyone with a Draak to verify?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v3 4/4] arm64: dts: renesas: r8a77995: draak: Enable HDMI display output

[Laurent Pinchart]

Hello,

On Fri, Jun 18, 2021 at 02:07:48PM +0200, Geert Uytterhoeven wrote:
> On Fri, Jun 18, 2021 at 2:01 PM Ulrich Hecht wrote:
> > > On 06/18/2021 10:05 AM Geert Uytterhoeven wrote:
> > > On Tue, Sep 25, 2018 at 6:34 PM Laurent Pinchart
> > > <laurent.pinchart+renesas@ideasonboard.com> wrote:
> > > > From: Ulrich Hecht <uli+renesas@fpond.eu>
> > > >
> > > > Adds LVDS decoder, HDMI encoder and connector for the Draak board.
> > > >
> > > > The LVDS0 and LVDS1 encoders can use the DU_DOTCLKIN0, DU_DOTCLKIN1 and
> > > > EXTAL externals clocks. Two of them are provided to the SoC on the Draak
> > > > board, hook them up in DT.
> > > >
> > > > Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
> > > > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > > > Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
> > >
> > > > --- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
> > > > +++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
> > >
> > > > @@ -190,6 +225,43 @@
> > > >
> > > >         };
> > > >
> > > > +       hdmi-encoder@39 {
> > > > +               compatible = "adi,adv7511w";
> > > > +               reg = <0x39>, <0x3f>, <0x38>, <0x3c>;
> > > > +               reg-names = "main", "edid", "packet", "cec";
> > > > +               interrupt-parent = <&gpio1>;
> > > > +               interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
> > > > +
> > > > +               /* Depends on LVDS */
> > > > +               max-clock = <135000000>;
> > > > +               min-vrefresh = <50>;
> > >
> > > Where do these two come from? They fail to validate with commit
> > > cfe34bb7a770c5d8 ("dt-bindings: drm: bridge: adi,adv7511.txt: convert
> > > to yaml").
> > > I can't find where it is used in the driver, nor in the driver history.
> >
> > I have found a prototype patch in my archives that uses these
> > properties. I guess the patch itself didn't make it into the final
> > series, but the properties inadvertently did. I vaguely remember
> > this was supposed to work around an issue with modes that use a
> > higher clock than supported by one of the parts in the display
> > pipeline.
> 
> Thanks, I already suspected something like that...

Sounds like a BSP attempt to model limitations of the DU and/or the PCB
and implement them in the adv7511 driver. There's similar code in the
VGA encoder driver that really doesn't belong there.

> > I would say that if there are no issues with HDMI output, both the
> > patch and the properties are obsolete.
> 
> Anyone with a Draak to verify?

I don't carry Ulrich's patch in my branch, and last time I checked, HDMI
output was functional. Do you want me to retest ?

-- 
Regards,

Laurent Pinchart

Re: [PATCH v3 4/4] arm64: dts: renesas: r8a77995: draak: Enable HDMI display output

[Geert Uytterhoeven]

Hi Laurent,

On Fri, Jun 18, 2021 at 2:24 PM Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
> On Fri, Jun 18, 2021 at 02:07:48PM +0200, Geert Uytterhoeven wrote:
> > On Fri, Jun 18, 2021 at 2:01 PM Ulrich Hecht wrote:
> > > > On 06/18/2021 10:05 AM Geert Uytterhoeven wrote:
> > > > On Tue, Sep 25, 2018 at 6:34 PM Laurent Pinchart
> > > > <laurent.pinchart+renesas@ideasonboard.com> wrote:
> > > > > From: Ulrich Hecht <uli+renesas@fpond.eu>
> > > > >
> > > > > Adds LVDS decoder, HDMI encoder and connector for the Draak board.
> > > > >
> > > > > The LVDS0 and LVDS1 encoders can use the DU_DOTCLKIN0, DU_DOTCLKIN1 and
> > > > > EXTAL externals clocks. Two of them are provided to the SoC on the Draak
> > > > > board, hook them up in DT.
> > > > >
> > > > > Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
> > > > > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > > > > Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
> > > >
> > > > > --- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
> > > > > +++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
> > > >
> > > > > @@ -190,6 +225,43 @@
> > > > >
> > > > >         };
> > > > >
> > > > > +       hdmi-encoder@39 {
> > > > > +               compatible = "adi,adv7511w";
> > > > > +               reg = <0x39>, <0x3f>, <0x38>, <0x3c>;
> > > > > +               reg-names = "main", "edid", "packet", "cec";
> > > > > +               interrupt-parent = <&gpio1>;
> > > > > +               interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
> > > > > +
> > > > > +               /* Depends on LVDS */
> > > > > +               max-clock = <135000000>;
> > > > > +               min-vrefresh = <50>;
> > > >
> > > > Where do these two come from? They fail to validate with commit
> > > > cfe34bb7a770c5d8 ("dt-bindings: drm: bridge: adi,adv7511.txt: convert
> > > > to yaml").
> > > > I can't find where it is used in the driver, nor in the driver history.
> > >
> > > I have found a prototype patch in my archives that uses these
> > > properties. I guess the patch itself didn't make it into the final
> > > series, but the properties inadvertently did. I vaguely remember
> > > this was supposed to work around an issue with modes that use a
> > > higher clock than supported by one of the parts in the display
> > > pipeline.
> >
> > Thanks, I already suspected something like that...
>
> Sounds like a BSP attempt to model limitations of the DU and/or the PCB
> and implement them in the adv7511 driver. There's similar code in the
> VGA encoder driver that really doesn't belong there.
>
> > > I would say that if there are no issues with HDMI output, both the
> > > patch and the properties are obsolete.
> >
> > Anyone with a Draak to verify?
>
> I don't carry Ulrich's patch in my branch, and last time I checked, HDMI
> output was functional. Do you want me to retest ?

I guess no re-testing is needed, and the properties can just be removed.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v3 4/4] arm64: dts: renesas: r8a77995: draak: Enable HDMI display output

[Laurent Pinchart]

Hi Geert,

On Fri, Jun 18, 2021 at 02:48:18PM +0200, Geert Uytterhoeven wrote:
> On Fri, Jun 18, 2021 at 2:24 PM Laurent Pinchart wrote:
> > On Fri, Jun 18, 2021 at 02:07:48PM +0200, Geert Uytterhoeven wrote:
> > > On Fri, Jun 18, 2021 at 2:01 PM Ulrich Hecht wrote:
> > > > > On 06/18/2021 10:05 AM Geert Uytterhoeven wrote:
> > > > > On Tue, Sep 25, 2018 at 6:34 PM Laurent Pinchart wrote:
> > > > > > From: Ulrich Hecht <uli+renesas@fpond.eu>
> > > > > >
> > > > > > Adds LVDS decoder, HDMI encoder and connector for the Draak board.
> > > > > >
> > > > > > The LVDS0 and LVDS1 encoders can use the DU_DOTCLKIN0, DU_DOTCLKIN1 and
> > > > > > EXTAL externals clocks. Two of them are provided to the SoC on the Draak
> > > > > > board, hook them up in DT.
> > > > > >
> > > > > > Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
> > > > > > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > > > > > Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
> > > > >
> > > > > > --- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
> > > > > > +++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
> > > > >
> > > > > > @@ -190,6 +225,43 @@
> > > > > >
> > > > > >         };
> > > > > >
> > > > > > +       hdmi-encoder@39 {
> > > > > > +               compatible = "adi,adv7511w";
> > > > > > +               reg = <0x39>, <0x3f>, <0x38>, <0x3c>;
> > > > > > +               reg-names = "main", "edid", "packet", "cec";
> > > > > > +               interrupt-parent = <&gpio1>;
> > > > > > +               interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
> > > > > > +
> > > > > > +               /* Depends on LVDS */
> > > > > > +               max-clock = <135000000>;
> > > > > > +               min-vrefresh = <50>;
> > > > >
> > > > > Where do these two come from? They fail to validate with commit
> > > > > cfe34bb7a770c5d8 ("dt-bindings: drm: bridge: adi,adv7511.txt: convert
> > > > > to yaml").
> > > > > I can't find where it is used in the driver, nor in the driver history.
> > > >
> > > > I have found a prototype patch in my archives that uses these
> > > > properties. I guess the patch itself didn't make it into the final
> > > > series, but the properties inadvertently did. I vaguely remember
> > > > this was supposed to work around an issue with modes that use a
> > > > higher clock than supported by one of the parts in the display
> > > > pipeline.
> > >
> > > Thanks, I already suspected something like that...
> >
> > Sounds like a BSP attempt to model limitations of the DU and/or the PCB
> > and implement them in the adv7511 driver. There's similar code in the
> > VGA encoder driver that really doesn't belong there.
> >
> > > > I would say that if there are no issues with HDMI output, both the
> > > > patch and the properties are obsolete.
> > >
> > > Anyone with a Draak to verify?
> >
> > I don't carry Ulrich's patch in my branch, and last time I checked, HDMI
> > output was functional. Do you want me to retest ?
> 
> I guess no re-testing is needed, and the properties can just be removed.

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

-- 
Regards,

Laurent Pinchart