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[108.223.40.66]) by smtp.gmail.com with ESMTPSA id u62-v6sm13227276pfu.69.2018.09.29.11.18.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 29 Sep 2018 11:18:59 -0700 (PDT) Date: Sat, 29 Sep 2018 11:18:58 -0700 From: Guenter Roeck To: Christophe Leroy Cc: Wim Van Sebroeck , Radu Rendec , Rob Herring , Mark Rutland , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [v3,2/3] watchdog: mpc8xxx: provide boot status Message-ID: <20180929181858.GA5758@roeck-us.net> References: <207741bf9c994a869f574a93d4fb4152d4e169c9.1537163779.git.christophe.leroy@c-s.fr> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <207741bf9c994a869f574a93d4fb4152d4e169c9.1537163779.git.christophe.leroy@c-s.fr> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Sep 17, 2018 at 06:22:50AM +0000, Christophe Leroy wrote: > mpc8xxx watchdog driver supports the following platforms: > - mpc8xx > - mpc83xx > - mpc86xx > > Those three platforms have a 32 bits register which provides the > reason of the last boot, including whether it was caused by the > watchdog. > > mpc8xx: Register RSR, bit SWRS (bit 3) > mpc83xx: Register RSR, bit SWRS (bit 28) > mpc86xx: Register RSTRSCR, bit WDT_RR (bit 11) > > This patch maps the register as defined in the device tree and updates > wdt.bootstatus based on the value of the watchdog related bit. Then > the information can be retrieved via the WDIOC_GETBOOTSTATUS ioctl. > > Hereunder is an example of devicetree for mpc8xx, > the Reset Status Register being at offset 0x288: > > WDT: watchdog@0 { > compatible = "fsl,mpc823-wdt"; > reg = <0x0 0x10 0x288 0x4>; > }; > > On the mpc83xx, RSR is at offset 0x910 > On the mpc86xx, RSTRSCR is at offset 0xe0094 > > Suggested-by: Radu Rendec > Tested-by: Christophe Leroy # On mpc885 > Signed-off-by: Christophe Leroy Reviewed-by: Guenter Roeck > --- > drivers/watchdog/mpc8xxx_wdt.c | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/drivers/watchdog/mpc8xxx_wdt.c b/drivers/watchdog/mpc8xxx_wdt.c > index 1dcf5f10cdd9..069072e6747d 100644 > --- a/drivers/watchdog/mpc8xxx_wdt.c > +++ b/drivers/watchdog/mpc8xxx_wdt.c > @@ -47,6 +47,7 @@ struct mpc8xxx_wdt { > struct mpc8xxx_wdt_type { > int prescaler; > bool hw_enabled; > + u32 rsr_mask; > }; > > struct mpc8xxx_wdt_ddata { > @@ -159,6 +160,24 @@ static int mpc8xxx_wdt_probe(struct platform_device *ofdev) > return -ENODEV; > } > > + res = platform_get_resource(ofdev, IORESOURCE_MEM, 1); > + if (res) { > + bool status; > + u32 __iomem *rsr = ioremap(res->start, resource_size(res)); > + > + if (!rsr) > + return -ENOMEM; > + > + status = in_be32(rsr) & wdt_type->rsr_mask; > + ddata->wdd.bootstatus = status ? WDIOF_CARDRESET : 0; > + /* clear reset status bits related to watchdog timer */ > + out_be32(rsr, wdt_type->rsr_mask); > + iounmap(rsr); > + > + dev_info(dev, "Last boot was %scaused by watchdog\n", > + status ? "" : "not "); > + } > + > spin_lock_init(&ddata->lock); > > ddata->wdd.info = &mpc8xxx_wdt_info, > @@ -216,6 +235,7 @@ static const struct of_device_id mpc8xxx_wdt_match[] = { > .compatible = "mpc83xx_wdt", > .data = &(struct mpc8xxx_wdt_type) { > .prescaler = 0x10000, > + .rsr_mask = BIT(3), /* RSR Bit SWRS */ > }, > }, > { > @@ -223,6 +243,7 @@ static const struct of_device_id mpc8xxx_wdt_match[] = { > .data = &(struct mpc8xxx_wdt_type) { > .prescaler = 0x10000, > .hw_enabled = true, > + .rsr_mask = BIT(20), /* RSTRSCR Bit WDT_RR */ > }, > }, > { > @@ -230,6 +251,7 @@ static const struct of_device_id mpc8xxx_wdt_match[] = { > .data = &(struct mpc8xxx_wdt_type) { > .prescaler = 0x800, > .hw_enabled = true, > + .rsr_mask = BIT(28), /* RSR Bit SWRS */ > }, > }, > {}, From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.1 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_PASS,USER_AGENT_MUTT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 874A9C43143 for ; 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[108.223.40.66]) by smtp.gmail.com with ESMTPSA id u62-v6sm13227276pfu.69.2018.09.29.11.18.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 29 Sep 2018 11:18:59 -0700 (PDT) Date: Sat, 29 Sep 2018 11:18:58 -0700 From: Guenter Roeck To: Christophe Leroy Subject: Re: [v3,2/3] watchdog: mpc8xxx: provide boot status Message-ID: <20180929181858.GA5758@roeck-us.net> References: <207741bf9c994a869f574a93d4fb4152d4e169c9.1537163779.git.christophe.leroy@c-s.fr> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <207741bf9c994a869f574a93d4fb4152d4e169c9.1537163779.git.christophe.leroy@c-s.fr> User-Agent: Mutt/1.5.24 (2015-08-30) X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Radu Rendec , Wim Van Sebroeck , linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Mon, Sep 17, 2018 at 06:22:50AM +0000, Christophe Leroy wrote: > mpc8xxx watchdog driver supports the following platforms: > - mpc8xx > - mpc83xx > - mpc86xx > > Those three platforms have a 32 bits register which provides the > reason of the last boot, including whether it was caused by the > watchdog. > > mpc8xx: Register RSR, bit SWRS (bit 3) > mpc83xx: Register RSR, bit SWRS (bit 28) > mpc86xx: Register RSTRSCR, bit WDT_RR (bit 11) > > This patch maps the register as defined in the device tree and updates > wdt.bootstatus based on the value of the watchdog related bit. Then > the information can be retrieved via the WDIOC_GETBOOTSTATUS ioctl. > > Hereunder is an example of devicetree for mpc8xx, > the Reset Status Register being at offset 0x288: > > WDT: watchdog@0 { > compatible = "fsl,mpc823-wdt"; > reg = <0x0 0x10 0x288 0x4>; > }; > > On the mpc83xx, RSR is at offset 0x910 > On the mpc86xx, RSTRSCR is at offset 0xe0094 > > Suggested-by: Radu Rendec > Tested-by: Christophe Leroy # On mpc885 > Signed-off-by: Christophe Leroy Reviewed-by: Guenter Roeck > --- > drivers/watchdog/mpc8xxx_wdt.c | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/drivers/watchdog/mpc8xxx_wdt.c b/drivers/watchdog/mpc8xxx_wdt.c > index 1dcf5f10cdd9..069072e6747d 100644 > --- a/drivers/watchdog/mpc8xxx_wdt.c > +++ b/drivers/watchdog/mpc8xxx_wdt.c > @@ -47,6 +47,7 @@ struct mpc8xxx_wdt { > struct mpc8xxx_wdt_type { > int prescaler; > bool hw_enabled; > + u32 rsr_mask; > }; > > struct mpc8xxx_wdt_ddata { > @@ -159,6 +160,24 @@ static int mpc8xxx_wdt_probe(struct platform_device *ofdev) > return -ENODEV; > } > > + res = platform_get_resource(ofdev, IORESOURCE_MEM, 1); > + if (res) { > + bool status; > + u32 __iomem *rsr = ioremap(res->start, resource_size(res)); > + > + if (!rsr) > + return -ENOMEM; > + > + status = in_be32(rsr) & wdt_type->rsr_mask; > + ddata->wdd.bootstatus = status ? WDIOF_CARDRESET : 0; > + /* clear reset status bits related to watchdog timer */ > + out_be32(rsr, wdt_type->rsr_mask); > + iounmap(rsr); > + > + dev_info(dev, "Last boot was %scaused by watchdog\n", > + status ? "" : "not "); > + } > + > spin_lock_init(&ddata->lock); > > ddata->wdd.info = &mpc8xxx_wdt_info, > @@ -216,6 +235,7 @@ static const struct of_device_id mpc8xxx_wdt_match[] = { > .compatible = "mpc83xx_wdt", > .data = &(struct mpc8xxx_wdt_type) { > .prescaler = 0x10000, > + .rsr_mask = BIT(3), /* RSR Bit SWRS */ > }, > }, > { > @@ -223,6 +243,7 @@ static const struct of_device_id mpc8xxx_wdt_match[] = { > .data = &(struct mpc8xxx_wdt_type) { > .prescaler = 0x10000, > .hw_enabled = true, > + .rsr_mask = BIT(20), /* RSTRSCR Bit WDT_RR */ > }, > }, > { > @@ -230,6 +251,7 @@ static const struct of_device_id mpc8xxx_wdt_match[] = { > .data = &(struct mpc8xxx_wdt_type) { > .prescaler = 0x800, > .hw_enabled = true, > + .rsr_mask = BIT(28), /* RSR Bit SWRS */ > }, > }, > {},