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From: Alexandru-Cosmin Gheorghe <Alexandru-Cosmin.Gheorghe@arm.com>
To: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Cc: "intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>, nd <nd@arm.com>,
	"dri-devel@lists.freedesktop.org"
	<dri-devel@lists.freedesktop.org>
Subject: Re: [PATCH 1/4] drm: Add P010, P012, P016 format definitions and fourcc
Date: Tue, 2 Oct 2018 15:00:21 +0000	[thread overview]
Message-ID: <20181002150020.GA22819@e114479-lin.cambridge.arm.com> (raw)
In-Reply-To: <1535632874-29927-1-git-send-email-juhapekka.heikkila@gmail.com>

Hi,

How is this going on, anything holding it back from getting merged ?
I'm interested in adding/using P010, [1]

Thank you,
Alex Gheorghe

[1] https://lists.freedesktop.org/archives/dri-devel/2018-August/186963.html

On Thu, Aug 30, 2018 at 03:41:11PM +0300, Juha-Pekka Heikkila wrote:
> Add P010 definition, semi-planar yuv format where each component
> is 16 bits 10 msb containing color value. First come Y plane [10:6]
> followed by 2x2 subsampled Cr:Cb plane [10:6:10:6]
> 
> Add P012 definition, semi-planar yuv format where each component
> is 16 bits 12 msb containing color value. First come Y plane [12:4]
> followed by 2x2 subsampled Cr:Cb plane [12:4:12:4]
> 
> Add P016 definition, semi-planar yuv format where each component
> is 16 bits. First come Y plane followed by 2x2 subsampled Cr:Cb
> plane [16:16]
> 
> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
> ---
>  drivers/gpu/drm/drm_fourcc.c  |  3 +++
>  include/uapi/drm/drm_fourcc.h | 10 ++++++++++
>  2 files changed, 13 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> index 35c1e27..32e07a2 100644
> --- a/drivers/gpu/drm/drm_fourcc.c
> +++ b/drivers/gpu/drm/drm_fourcc.c
> @@ -173,6 +173,9 @@ const struct drm_format_info *__drm_format_info(u32 format)
>  		{ .format = DRM_FORMAT_UYVY,		.depth = 0,  .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
>  		{ .format = DRM_FORMAT_VYUY,		.depth = 0,  .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
>  		{ .format = DRM_FORMAT_AYUV,		.depth = 0,  .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true, .is_yuv = true },
> +		{ .format = DRM_FORMAT_P010,		.depth = 0,  .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true  },
> +		{ .format = DRM_FORMAT_P012,		.depth = 0,  .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true  },
> +		{ .format = DRM_FORMAT_P016,		.depth = 0,  .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true  },
>  	};
>  
>  	unsigned int i;
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 2ed46e9..daaabb1 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -178,6 +178,16 @@ extern "C" {
>  #define DRM_FORMAT_NV42		fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
>  
>  /*
> + * 2 plane YCbCr
> + * index 0 = Y plane, [15:0] Y little endian where Pxxx indicate
> + * component xxx msb Y [xxx:16-xxx]
> + * index 1 = Cr:Cb plane, [31:0] Cr:Cb little endian [xxx:16-xxx:xxx:16-xxx]
> + */
> +#define DRM_FORMAT_P010		fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane, 10 bit per channel */
> +#define DRM_FORMAT_P012		fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane, 12 bit per channel */
> +#define DRM_FORMAT_P016		fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane, 16 bit per channel */
> +
> +/*
>   * 3 plane YCbCr
>   * index 0: Y plane, [7:0] Y
>   * index 1: Cb plane, [7:0] Cb
> -- 
> 2.7.4
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

-- 
Cheers,
Alex G
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2018-10-02 15:00 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-08-30 12:41 [PATCH 1/4] drm: Add P010, P012, P016 format definitions and fourcc Juha-Pekka Heikkila
2018-08-30 12:41 ` [PATCH 2/4] drm/i915: Add P010, P012, P016 plane control definitions Juha-Pekka Heikkila
2018-08-30 12:41 ` [PATCH 3/4] drm/i915: preparations for enabling P010, P012, P016 formats Juha-Pekka Heikkila
2018-08-30 13:52   ` [Intel-gfx] " Ville Syrjälä
2018-09-04 11:16   ` Maarten Lankhorst
2018-08-30 12:41 ` [PATCH 4/4] drm/i915: enable P010, P012, P016 formats for primary and sprite planes Juha-Pekka Heikkila
2018-09-04 12:32   ` Maarten Lankhorst
2018-08-30 13:43 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm: Add P010, P012, P016 format definitions and fourcc Patchwork
2018-08-30 13:46 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-08-30 14:04 ` ✓ Fi.CI.BAT: success " Patchwork
2018-08-30 17:48 ` ✓ Fi.CI.IGT: " Patchwork
2018-10-02 15:00 ` Alexandru-Cosmin Gheorghe [this message]
2018-10-03 11:31   ` [PATCH 1/4] " Juha-Pekka Heikkila
2018-10-03 17:18     ` Alexandru-Cosmin Gheorghe
2018-10-03 19:20       ` Juha-Pekka Heikkilä
  -- strict thread matches above, loose matches on Subject: below --
2018-08-16 12:55 Juha-Pekka Heikkila
2018-05-29 13:28 [PATCH 0/4] Enable P010, P012 and P016 formats for GLK/CNL Juha-Pekka Heikkila
2018-05-29 13:28 ` [PATCH 1/4] drm: Add P010, P012, P016 format definitions and fourcc Juha-Pekka Heikkila
2018-05-29 15:48   ` Maarten Lankhorst

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