From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rajesh Bhagat Date: Wed, 3 Oct 2018 17:07:22 +0530 Subject: [U-Boot] [PATCH 39/53] armv8: layerscape: Enable routing SError exception In-Reply-To: <20181003113736.14981-1-rajesh.bhagat@nxp.com> References: <20181003113736.14981-1-rajesh.bhagat@nxp.com> Message-ID: <20181003113736.14981-40-rajesh.bhagat@nxp.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: York Sun In case SError happens at EL2, if SCR_EL3[EA] is not routing it to EL3, and SCR_EL3[RW] is set to aarch64, setting HCR_EL2[AMO] routes the exception to EL2. Otherwise this exception is not taken. Signed-off-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index acaa6d6e37..cbc9112eb1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -71,6 +71,15 @@ ENDPROC(smp_kick_all_cpus) ENTRY(lowlevel_init) mov x29, lr /* Save LR */ + /* unmask SError and abort */ + msr daifclr, #4 + + /* Set HCR_EL2[AMO] so SError @EL2 is taken */ + mrs x0, hcr_el2 + orr x0, x0, #0x20 /* AMO */ + msr hcr_el2, x0 + isb + switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */ 1: -- 2.17.1