From mboxrd@z Thu Jan 1 00:00:00 1970 From: Simon Horman Subject: Re: [PATCH v7 3/3] ARM: dts: r9a06g032: Add pinctrl node Date: Thu, 4 Oct 2018 12:18:33 +0200 Message-ID: <20181004101833.jlopmzmyx6nkjnux@verge.net.au> References: <20181001131026.14635-1-phil.edworthy@renesas.com> <20181001131026.14635-4-phil.edworthy@renesas.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <20181001131026.14635-4-phil.edworthy@renesas.com> Sender: linux-kernel-owner@vger.kernel.org To: Phil Edworthy Cc: Geert Uytterhoeven , Laurent Pinchart , Jacopo Mondi , Linus Walleij , linux-gpio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org List-Id: linux-gpio@vger.kernel.org On Mon, Oct 01, 2018 at 02:10:26PM +0100, Phil Edworthy wrote: > This provides a pinctrl driver for the Renesas R9A06G032 SoC > > Based on a patch originally written by Michel Pollet at Renesas. > > Signed-off-by: Phil Edworthy Hi Phil, I have accepted (a slightly older posting of) this patch for v4.21. > --- > v7: > - No changes. > > v6: > - No changes. > > v5: > - No changes. > > v4: > - No changes. > > v3: > - No changes. > > v2: > - Add "renesas,rzn1-pinctrl" compatible fallback string > - Register size corrected. > --- > arch/arm/boot/dts/r9a06g032.dtsi | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi > index eaf94976ed6d..2322268bc862 100644 > --- a/arch/arm/boot/dts/r9a06g032.dtsi > +++ b/arch/arm/boot/dts/r9a06g032.dtsi > @@ -165,6 +165,14 @@ > status = "disabled"; > }; > > + pinctrl: pin-controller@40067000 { > + compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl"; > + reg = <0x40067000 0x1000>, <0x51000000 0x480>; > + clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>; > + clock-names = "bus"; > + status = "okay"; > + }; > + > gic: gic@44101000 { > compatible = "arm,cortex-a7-gic", "arm,gic-400"; > interrupt-controller; > -- > 2.17.1 >