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From: Rajesh Bhagat <rajesh.bhagat@nxp.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 23/33] armv8: ls1046aqds: Add TFABOOT support
Date: Sun,  7 Oct 2018 15:29:19 +0530	[thread overview]
Message-ID: <20181007095929.17876-24-rajesh.bhagat@nxp.com> (raw)
In-Reply-To: <20181007095929.17876-1-rajesh.bhagat@nxp.com>

TFABOOT support includes:
 - ls1046aqds_tfa_defconfig to be loaded by trusted firmware
 - environment address and size changes for TFABOOT
 - FMAN address changes for TFABOOT
 - define BOOTCOMMAND for TFABOOT

Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
Change in v2:                                                                   
 - Merged ls1046aqds TFA boot support patches                                   
 - Removed extra CONFIG_TFABOOT flag usage

 board/freescale/ls1046aqds/ddr.c        |  11 ++
 board/freescale/ls1046aqds/ls1046aqds.c | 148 +++++++++++++++++++++++-
 configs/ls1046aqds_tfa_defconfig        |  57 +++++++++
 include/configs/ls1046aqds.h            |  59 +++++++++-
 4 files changed, 272 insertions(+), 3 deletions(-)
 create mode 100644 configs/ls1046aqds_tfa_defconfig

diff --git a/board/freescale/ls1046aqds/ddr.c b/board/freescale/ls1046aqds/ddr.c
index 08f7610e69..45b1f373a7 100644
--- a/board/freescale/ls1046aqds/ddr.c
+++ b/board/freescale/ls1046aqds/ddr.c
@@ -92,6 +92,16 @@ found:
 	popts->cpo_sample = 0x70;
 }
 
+#ifdef CONFIG_TFABOOT
+int fsl_initdram(void)
+{
+	gd->ram_size = tfa_get_dram_size();
+	if (!gd->ram_size)
+		gd->ram_size = fsl_ddr_sdram_size();
+
+	return 0;
+}
+#else
 int fsl_initdram(void)
 {
 	phys_size_t dram_size;
@@ -116,3 +126,4 @@ int fsl_initdram(void)
 
 	return 0;
 }
+#endif
diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c
index 0da82381af..b71c1746bb 100644
--- a/board/freescale/ls1046aqds/ls1046aqds.c
+++ b/board/freescale/ls1046aqds/ls1046aqds.c
@@ -13,6 +13,7 @@
 #include <asm/arch/ppa.h>
 #include <asm/arch/fdt.h>
 #include <asm/arch/mmu.h>
+#include <asm/arch/cpu.h>
 #include <asm/arch/soc.h>
 #include <asm/arch-fsl-layerscape/fsl_icid.h>
 #include <ahci.h>
@@ -32,12 +33,140 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_TFABOOT
+struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
+	{
+		"nor0",
+		CONFIG_SYS_NOR0_CSPR,
+		CONFIG_SYS_NOR0_CSPR_EXT,
+		CONFIG_SYS_NOR_AMASK,
+		CONFIG_SYS_NOR_CSOR,
+		{
+			CONFIG_SYS_NOR_FTIM0,
+			CONFIG_SYS_NOR_FTIM1,
+			CONFIG_SYS_NOR_FTIM2,
+			CONFIG_SYS_NOR_FTIM3
+		},
+
+	},
+	{
+		"nor1",
+		CONFIG_SYS_NOR1_CSPR,
+		CONFIG_SYS_NOR1_CSPR_EXT,
+		CONFIG_SYS_NOR_AMASK,
+		CONFIG_SYS_NOR_CSOR,
+		{
+			CONFIG_SYS_NOR_FTIM0,
+			CONFIG_SYS_NOR_FTIM1,
+			CONFIG_SYS_NOR_FTIM2,
+			CONFIG_SYS_NOR_FTIM3
+		},
+	},
+	{
+		"nand",
+		CONFIG_SYS_NAND_CSPR,
+		CONFIG_SYS_NAND_CSPR_EXT,
+		CONFIG_SYS_NAND_AMASK,
+		CONFIG_SYS_NAND_CSOR,
+		{
+			CONFIG_SYS_NAND_FTIM0,
+			CONFIG_SYS_NAND_FTIM1,
+			CONFIG_SYS_NAND_FTIM2,
+			CONFIG_SYS_NAND_FTIM3
+		},
+	},
+	{
+		"fpga",
+		CONFIG_SYS_FPGA_CSPR,
+		CONFIG_SYS_FPGA_CSPR_EXT,
+		CONFIG_SYS_FPGA_AMASK,
+		CONFIG_SYS_FPGA_CSOR,
+		{
+			CONFIG_SYS_FPGA_FTIM0,
+			CONFIG_SYS_FPGA_FTIM1,
+			CONFIG_SYS_FPGA_FTIM2,
+			CONFIG_SYS_FPGA_FTIM3
+		},
+	}
+};
+
+struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
+	{
+		"nand",
+		CONFIG_SYS_NAND_CSPR,
+		CONFIG_SYS_NAND_CSPR_EXT,
+		CONFIG_SYS_NAND_AMASK,
+		CONFIG_SYS_NAND_CSOR,
+		{
+			CONFIG_SYS_NAND_FTIM0,
+			CONFIG_SYS_NAND_FTIM1,
+			CONFIG_SYS_NAND_FTIM2,
+			CONFIG_SYS_NAND_FTIM3
+		},
+	},
+	{
+		"nor0",
+		CONFIG_SYS_NOR0_CSPR,
+		CONFIG_SYS_NOR0_CSPR_EXT,
+		CONFIG_SYS_NOR_AMASK,
+		CONFIG_SYS_NOR_CSOR,
+		{
+			CONFIG_SYS_NOR_FTIM0,
+			CONFIG_SYS_NOR_FTIM1,
+			CONFIG_SYS_NOR_FTIM2,
+			CONFIG_SYS_NOR_FTIM3
+		},
+	},
+	{
+		"nor1",
+		CONFIG_SYS_NOR1_CSPR,
+		CONFIG_SYS_NOR1_CSPR_EXT,
+		CONFIG_SYS_NOR_AMASK,
+		CONFIG_SYS_NOR_CSOR,
+		{
+			CONFIG_SYS_NOR_FTIM0,
+			CONFIG_SYS_NOR_FTIM1,
+			CONFIG_SYS_NOR_FTIM2,
+			CONFIG_SYS_NOR_FTIM3
+		},
+	},
+	{
+		"fpga",
+		CONFIG_SYS_FPGA_CSPR,
+		CONFIG_SYS_FPGA_CSPR_EXT,
+		CONFIG_SYS_FPGA_AMASK,
+		CONFIG_SYS_FPGA_CSOR,
+		{
+			CONFIG_SYS_FPGA_FTIM0,
+			CONFIG_SYS_FPGA_FTIM1,
+			CONFIG_SYS_FPGA_FTIM2,
+			CONFIG_SYS_FPGA_FTIM3
+		},
+	}
+};
+
+void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
+{
+	enum boot_src src = get_boot_src();
+
+	if (src == BOOT_SOURCE_IFC_NAND)
+		regs_info->regs = ifc_cfg_nand_boot;
+	else
+		regs_info->regs = ifc_cfg_nor_boot;
+	regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
+}
+
+#endif
+
 enum {
 	MUX_TYPE_GPIO,
 };
 
 int checkboard(void)
 {
+#ifdef CONFIG_TFABOOT
+	enum boot_src src = get_boot_src();
+#endif
 	char buf[64];
 #ifndef CONFIG_SD_BOOT
 	u8 sw;
@@ -45,6 +174,12 @@ int checkboard(void)
 
 	puts("Board: LS1046AQDS, boot from ");
 
+#ifdef CONFIG_TFABOOT
+	if (src == BOOT_SOURCE_SD_MMC)
+		puts("SD\n");
+	else {
+#endif
+
 #ifdef CONFIG_SD_BOOT
 	puts("SD\n");
 #else
@@ -63,6 +198,9 @@ int checkboard(void)
 		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 #endif
 
+#ifdef CONFIG_TFABOOT
+	}
+#endif
 	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
 	       QIXIS_READ(id), QIXIS_READ(arch));
 
@@ -153,7 +291,8 @@ int dram_init(void)
 	 */
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 	fsl_initdram();
-#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
+	defined(CONFIG_SPL_BUILD)
 	/* This will break-before-make MMU for DDR */
 	update_early_mmu_table();
 #endif
@@ -342,3 +481,10 @@ u16 flash_read16(void *addr)
 
 	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 }
+
+#ifdef CONFIG_TFABOOT
+void *env_sf_get_env_addr(void)
+{
+	return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
+}
+#endif
diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig
new file mode 100644
index 0000000000..c91bb76edf
--- /dev/null
+++ b/configs/ls1046aqds_tfa_defconfig
@@ -0,0 +1,57 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1046AQDS=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_TFABOOT=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m at 0x100000(nor_bank0_uboot),40m at 0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m at 0x4100000(nor_bank4_uboot),40m at 0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_MISC_INIT_R=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_CACHE=y
+CONFIG_MP=y
+CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m at 0x100000(nor_bank0_uboot),40m at 0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m at 0x4100000(nor_bank4_uboot),40m@0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:4m(nand_uboot),36m(nand_kernel),472m(nand_free);spi0.0:2m(uboot),14m(free)"
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
+CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DM=y
+CONFIG_FSL_CAAM=y
+CONFIG_FSL_ESDHC=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_E1000=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h
index 8edaf190d0..6f292a0af9 100644
--- a/include/configs/ls1046aqds.h
+++ b/include/configs/ls1046aqds.h
@@ -50,7 +50,8 @@ unsigned long get_board_ddr_clk(void);
 #endif
 
 /* QSPI */
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#if defined(CONFIG_TFABOOT) ||	\
+	defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 #ifdef CONFIG_FSL_QSPI
 #define CONFIG_SPI_FLASH_SPANSION
 #define FSL_QSPI_FLASH_SIZE		(1 << 24)
@@ -230,7 +231,8 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
 #endif
 
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#if defined(CONFIG_TFABOOT) || \
+	defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 #define CONFIG_QIXIS_I2C_ACCESS
 #define CONFIG_SYS_I2C_EARLY_INIT
 #endif
@@ -285,6 +287,40 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_FPGA_FTIM3		0x0
 #endif
 
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
+#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
+#define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
+#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
+#define CONFIG_SYS_CS3_FTIM0		CONFIG_SYS_FPGA_FTIM0
+#define CONFIG_SYS_CS3_FTIM1		CONFIG_SYS_FPGA_FTIM1
+#define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
+#define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
+#else
 #ifdef CONFIG_NAND_BOOT
 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
@@ -352,6 +388,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
 #define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
 #endif
+#endif
 
 /*
  * I2C bus multiplexer
@@ -402,6 +439,14 @@ unsigned long get_board_ddr_clk(void);
  */
 #define CONFIG_ENV_OVERWRITE
 
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		0x500000        /* 5MB */
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x500000)
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#else
 #ifdef CONFIG_NAND_BOOT
 #define CONFIG_ENV_SIZE			0x2000
 #define CONFIG_ENV_OFFSET		(12 * CONFIG_SYS_NAND_BLOCK_SIZE)
@@ -418,10 +463,19 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_ENV_SECT_SIZE		0x20000
 #define CONFIG_ENV_SIZE			0x20000
 #endif
+#endif
 
 #define CONFIG_CMDLINE_TAG
 
 #undef CONFIG_BOOTCOMMAND
+#ifdef CONFIG_TFABOOT
+#define QSPI_NOR_BOOTCOMMAND		"sf probe && sf read $kernel_load "    \
+					"e0000 f00000 && bootm $kernel_load"
+#define IFC_NOR_BOOTCOMMAND		"cp.b $kernel_start $kernel_load "     \
+					"$kernel_size && bootm $kernel_load"
+#define SD_BOOTCOMMAND		"mmc info; mmc read $kernel_load"     \
+					"$kernel_addr_sd $kernel_size_sd && bootm $kernel_load"
+#else
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 #define CONFIG_BOOTCOMMAND		"sf probe && sf read $kernel_load "    \
 					"e0000 f00000 && bootm $kernel_load"
@@ -429,6 +483,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_BOOTCOMMAND		"cp.b $kernel_start $kernel_load "     \
 					"$kernel_size && bootm $kernel_load"
 #endif
+#endif
 
 #include <asm/fsl_secure_boot.h>
 
-- 
2.17.1

  parent reply	other threads:[~2018-10-07  9:59 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-07  9:58 [U-Boot] [PATCH v2 00/33] TF-A Boot support for NXP Chassis 2 platforms Rajesh Bhagat
2018-10-07  9:58 ` [U-Boot] [PATCH v2 01/33] move data structure out of cpu.h Rajesh Bhagat
2018-10-07  9:58 ` [U-Boot] [PATCH v2 02/33] env: allow flash and nand env driver to compile together Rajesh Bhagat
2018-10-07  9:58 ` [U-Boot] [PATCH v2 03/33] env: sf: define API to override sf environment address Rajesh Bhagat
2018-10-07  9:59 ` [U-Boot] [PATCH v2 04/33] env: nand: remove unnecessary env_ptr definition Rajesh Bhagat
2018-10-07  9:59 ` [U-Boot] [PATCH v2 05/33] driver/ifc: replace __ilog2 with LOG2 macro Rajesh Bhagat
2018-10-07  9:59 ` [U-Boot] [PATCH v2 06/33] armv8: layerscape: Enable routing SError exception Rajesh Bhagat
2018-10-07  9:59 ` [U-Boot] [PATCH v2 07/33] armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3 Rajesh Bhagat
2018-10-07  9:59 ` [U-Boot] [PATCH v2 08/33] drivers: ifc: dynamic chipselect mapping support Rajesh Bhagat
2018-10-07  9:59 ` [U-Boot] [PATCH v2 09/33] armv8: fsl-layerscape: identify boot source from PORSR register Rajesh Bhagat
2018-10-07  9:59 ` [U-Boot] [PATCH v2 10/33] armv8: layerscape: remove EL3 specific erratas for TFABOOT Rajesh Bhagat
2018-10-07  9:59 ` [U-Boot] [PATCH v2 11/33] armv8: fsl-layerscape: bootcmd identification " Rajesh Bhagat
2018-10-07  9:59 ` [U-Boot] [PATCH v2 12/33] armv8: layerscape: secure boot support for environment selection Rajesh Bhagat
2018-10-07  9:59 ` [U-Boot] [PATCH v2 13/33] armv8: layerscape: add SMC calls for DDR size and bank info Rajesh Bhagat
2018-10-07  9:59 ` [U-Boot] [PATCH v2 14/33] armv8: layerscape: skip OCRAM init for TFABOOT Rajesh Bhagat
2018-10-07  9:59 ` [U-Boot] [PATCH v2 15/33] armv8: fsl-layerscape: Update parsing boot source Rajesh Bhagat
2018-10-07  9:59 ` [U-Boot] [PATCH v2 16/33] armv8: fsl-layerscape: add support of MC framework for TFA Rajesh Bhagat
2018-10-07  9:59 ` [U-Boot] [PATCH v2 17/33] armv8: sec_firmware: change el2_to_aarch32 SMC ID Rajesh Bhagat
2018-10-07  9:59 ` [U-Boot] [PATCH v2 18/33] armv8: sec_firmware: return job ring status as true in TFABOOT Rajesh Bhagat
2018-10-07  9:59 ` [U-Boot] [PATCH v2 19/33] net: fm: add TFABOOT support Rajesh Bhagat
2018-10-07  9:59 ` [U-Boot] [PATCH v2 20/33] drivers: qe: " Rajesh Bhagat
2018-10-07  9:59 ` [U-Boot] [PATCH v2 21/33] armv8: ls1046ardb: Add " Rajesh Bhagat
2018-10-07  9:59 ` [U-Boot] [PATCH v2 22/33] armv8: ls1046ardb: Add TFABOOT defconfig for secure boot Rajesh Bhagat
2018-10-07  9:59 ` Rajesh Bhagat [this message]
2018-10-07  9:59 ` [U-Boot] [PATCH v2 24/33] armv8: ls1046aqds: " Rajesh Bhagat
2018-10-07  9:59 ` [U-Boot] [PATCH v2 25/33] armv8: ls1043ardb: Add TFABOOT support Rajesh Bhagat
2018-10-07  9:59 ` [U-Boot] [PATCH v2 26/33] armv8: ls1043ardb: Add TFABOOT defconfig for secure boot Rajesh Bhagat
2018-10-07  9:59 ` [U-Boot] [PATCH v2 27/33] armv8: ls1043aqds: Add TFABOOT support Rajesh Bhagat
2018-10-07  9:59 ` [U-Boot] [PATCH v2 28/33] armv8: ls1043aqds: Add TFABOOT defconfig for secure boot Rajesh Bhagat
2018-10-07  9:59 ` [U-Boot] [PATCH v2 29/33] armv8: ls1012ardb: Add TFABOOT support Rajesh Bhagat
2018-10-07 10:20 [U-Boot] [PATCH v2 00/33] TF-A Boot support for NXP Chassis 2 platforms Rajesh Bhagat
2018-10-07 10:21 ` [U-Boot] [PATCH v2 23/33] armv8: ls1046aqds: Add TFABOOT support Rajesh Bhagat

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