From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [6/7] dmaengine: stm32-dma: fix max items per transfer From: Joel Fernandes Message-Id: <20181009054752.145978-7-joel@joelfernandes.org> Date: Mon, 8 Oct 2018 22:47:51 -0700 To: stable@vger.kernel.org Cc: Pierre Yves MORDRET , Vinod Koul , gregkh@linuxfoundation.org, Alexandre Torgue , Dan Williams , dmaengine@vger.kernel.org, "Joel Fernandes (Google)" , "moderated list:ARM/STM32 ARCHITECTURE" , linux-kernel@vger.kernel.org, Maxime Coquelin List-ID: RnJvbTogUGllcnJlIFl2ZXMgTU9SRFJFVCA8cGllcnJlLXl2ZXMubW9yZHJldEBzdC5jb20+CgpI YXZpbmcgMCBpbiBpdGVtIGNvdW50ZXIgcmVnaXN0ZXIgaXMgdmFsaWQgYW5kIHN0YW5kcyBmb3Ig YSAiTm8gb3IgRW5kZWQKdHJhbnNmZXIiLiBUaGVyZWZvcmUgdmFsaWQgdHJhbnNmZXIgc3RhcnRz IGZyb20gQCswIHRvIEArMHhGRkZFIGxlYWRpbmcgdG8KdW5hbGlnbmVkIHNjYXR0ZXIgZ2F0aGVy IGF0IGJvdW5kYXJ5LiBUaHVzIGl0J3Mgc2FmZXIgdG8gcm91bmQgZG93biB0aGlzCnZhbHVlIG9u IGl0cyBGSUZPIHNpemUgKDE2IEJ5dGVzKS4KClNpZ25lZC1vZmYtYnk6IFBpZXJyZS1ZdmVzIE1P UkRSRVQgPHBpZXJyZS15dmVzLm1vcmRyZXRAc3QuY29tPgpTaWduZWQtb2ZmLWJ5OiBWaW5vZCBL b3VsIDx2aW5vZC5rb3VsQGludGVsLmNvbT4KLS0tCiBkcml2ZXJzL2RtYS9zdG0zMi1kbWEuYyB8 IDE5ICsrKysrKysrKysrLS0tLS0tLS0KIDEgZmlsZSBjaGFuZ2VkLCAxMSBpbnNlcnRpb25zKCsp LCA4IGRlbGV0aW9ucygtKQoKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZG1hL3N0bTMyLWRtYS5jIGIv ZHJpdmVycy9kbWEvc3RtMzItZG1hLmMKaW5kZXggYjQwNDg2NDU0YTJjLi4wNWEyOTc0Y2QyYzAg MTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZG1hL3N0bTMyLWRtYS5jCisrKyBiL2RyaXZlcnMvZG1hL3N0 bTMyLWRtYS5jCkBAIC0zOCwxMCArMzgsNiBAQAogI2RlZmluZSBTVE0zMl9ETUFfVEVJCQkJQklU KDMpIC8qIFRyYW5zZmVyIEVycm9yIEludGVycnVwdCAqLwogI2RlZmluZSBTVE0zMl9ETUFfRE1F SQkJCUJJVCgyKSAvKiBEaXJlY3QgTW9kZSBFcnJvciBJbnRlcnJ1cHQgKi8KICNkZWZpbmUgU1RN MzJfRE1BX0ZFSQkJCUJJVCgwKSAvKiBGSUZPIEVycm9yIEludGVycnVwdCAqLwotI2RlZmluZSBT VE0zMl9ETUFfTUFTS0kJCQkoU1RNMzJfRE1BX1RDSSBcCi0JCQkJCSB8IFNUTTMyX0RNQV9URUkg XAotCQkJCQkgfCBTVE0zMl9ETUFfRE1FSSBcCi0JCQkJCSB8IFNUTTMyX0RNQV9GRUkpCiAKIC8q IERNQSBTdHJlYW0geCBDb25maWd1cmF0aW9uIFJlZ2lzdGVyICovCiAjZGVmaW5lIFNUTTMyX0RN QV9TQ1IoeCkJCSgweDAwMTAgKyAweDE4ICogKHgpKSAvKiB4ID0gMC4uNyAqLwpAQCAtMTE4LDYg KzExNCwxMyBAQAogI2RlZmluZSBTVE0zMl9ETUFfRklGT19USFJFU0hPTERfRlVMTAkJCTB4MDMK IAogI2RlZmluZSBTVE0zMl9ETUFfTUFYX0RBVEFfSVRFTVMJMHhmZmZmCisvKgorICogVmFsaWQg dHJhbnNmZXIgc3RhcnRzIGZyb20gQDAgdG8gQDB4RkZGRSBsZWFkaW5nIHRvIHVuYWxpZ25lZCBz Y2F0dGVyCisgKiBnYXRoZXIgYXQgYm91bmRhcnkuIFRodXMgaXQncyBzYWZlciB0byByb3VuZCBk b3duIHRoaXMgdmFsdWUgb24gRklGTworICogc2l6ZSAoMTYgQnl0ZXMpCisgKi8KKyNkZWZpbmUg U1RNMzJfRE1BX0FMSUdORURfTUFYX0RBVEFfSVRFTVMJXAorCUFMSUdOX0RPV04oU1RNMzJfRE1B X01BWF9EQVRBX0lURU1TLCAxNikKICNkZWZpbmUgU1RNMzJfRE1BX01BWF9DSEFOTkVMUwkJMHgw OAogI2RlZmluZSBTVE0zMl9ETUFfTUFYX1JFUVVFU1RfSUQJMHgwOAogI2RlZmluZSBTVE0zMl9E TUFfTUFYX0RBVEFfUEFSQU0JMHgwMwpAQCAtODY5LDcgKzg3Miw3IEBAIHN0YXRpYyBzdHJ1Y3Qg ZG1hX2FzeW5jX3R4X2Rlc2NyaXB0b3IgKnN0bTMyX2RtYV9wcmVwX3NsYXZlX3NnKAogCQlkZXNj LT5zZ19yZXFbaV0ubGVuID0gc2dfZG1hX2xlbihzZyk7CiAKIAkJbmJfZGF0YV9pdGVtcyA9IGRl c2MtPnNnX3JlcVtpXS5sZW4gLyBidXN3aWR0aDsKLQkJaWYgKG5iX2RhdGFfaXRlbXMgPiBTVE0z Ml9ETUFfTUFYX0RBVEFfSVRFTVMpIHsKKwkJaWYgKG5iX2RhdGFfaXRlbXMgPiBTVE0zMl9ETUFf QUxJR05FRF9NQVhfREFUQV9JVEVNUykgewogCQkJZGV2X2VycihjaGFuMmRldihjaGFuKSwgIm5i IGl0ZW1zIG5vdCBzdXBwb3J0ZWRcbiIpOwogCQkJZ290byBlcnI7CiAJCX0KQEAgLTkzNSw3ICs5 MzgsNyBAQCBzdGF0aWMgc3RydWN0IGRtYV9hc3luY190eF9kZXNjcmlwdG9yICpzdG0zMl9kbWFf cHJlcF9kbWFfY3ljbGljKAogCQlyZXR1cm4gTlVMTDsKIAogCW5iX2RhdGFfaXRlbXMgPSBwZXJp b2RfbGVuIC8gYnVzd2lkdGg7Ci0JaWYgKG5iX2RhdGFfaXRlbXMgPiBTVE0zMl9ETUFfTUFYX0RB VEFfSVRFTVMpIHsKKwlpZiAobmJfZGF0YV9pdGVtcyA+IFNUTTMyX0RNQV9BTElHTkVEX01BWF9E QVRBX0lURU1TKSB7CiAJCWRldl9lcnIoY2hhbjJkZXYoY2hhbiksICJudW1iZXIgb2YgaXRlbXMg bm90IHN1cHBvcnRlZFxuIik7CiAJCXJldHVybiBOVUxMOwogCX0KQEAgLTk4NSw3ICs5ODgsNyBA QCBzdGF0aWMgc3RydWN0IGRtYV9hc3luY190eF9kZXNjcmlwdG9yICpzdG0zMl9kbWFfcHJlcF9k bWFfbWVtY3B5KAogCXUzMiBudW1fc2dzLCBiZXN0X2J1cnN0LCBkbWFfYnVyc3QsIHRocmVzaG9s ZDsKIAlpbnQgaTsKIAotCW51bV9zZ3MgPSBESVZfUk9VTkRfVVAobGVuLCBTVE0zMl9ETUFfTUFY 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From: "Joel Fernandes (Google)" To: stable@vger.kernel.org Cc: Pierre Yves MORDRET , Vinod Koul , gregkh@linuxfoundation.org, Alexandre Torgue , Dan Williams , dmaengine@vger.kernel.org, "Joel Fernandes (Google)" , linux-arm-kernel@lists.infradead.org (moderated list:ARM/STM32 ARCHITECTURE), linux-kernel@vger.kernel.org, Maxime Coquelin Subject: [PATCH 6/7] dmaengine: stm32-dma: fix max items per transfer Date: Mon, 8 Oct 2018 22:47:51 -0700 Message-Id: <20181009054752.145978-7-joel@joelfernandes.org> X-Mailer: git-send-email 2.19.0.605.g01d371f741-goog In-Reply-To: <20181009054752.145978-1-joel@joelfernandes.org> References: <20181009054752.145978-1-joel@joelfernandes.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Pierre Yves MORDRET Having 0 in item counter register is valid and stands for a "No or Ended transfer". Therefore valid transfer starts from @+0 to @+0xFFFE leading to unaligned scatter gather at boundary. Thus it's safer to round down this value on its FIFO size (16 Bytes). Signed-off-by: Pierre-Yves MORDRET Signed-off-by: Vinod Koul --- drivers/dma/stm32-dma.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/dma/stm32-dma.c b/drivers/dma/stm32-dma.c index b40486454a2c..05a2974cd2c0 100644 --- a/drivers/dma/stm32-dma.c +++ b/drivers/dma/stm32-dma.c @@ -38,10 +38,6 @@ #define STM32_DMA_TEI BIT(3) /* Transfer Error Interrupt */ #define STM32_DMA_DMEI BIT(2) /* Direct Mode Error Interrupt */ #define STM32_DMA_FEI BIT(0) /* FIFO Error Interrupt */ -#define STM32_DMA_MASKI (STM32_DMA_TCI \ - | STM32_DMA_TEI \ - | STM32_DMA_DMEI \ - | STM32_DMA_FEI) /* DMA Stream x Configuration Register */ #define STM32_DMA_SCR(x) (0x0010 + 0x18 * (x)) /* x = 0..7 */ @@ -118,6 +114,13 @@ #define STM32_DMA_FIFO_THRESHOLD_FULL 0x03 #define STM32_DMA_MAX_DATA_ITEMS 0xffff +/* + * Valid transfer starts from @0 to @0xFFFE leading to unaligned scatter + * gather at boundary. Thus it's safer to round down this value on FIFO + * size (16 Bytes) + */ +#define STM32_DMA_ALIGNED_MAX_DATA_ITEMS \ + ALIGN_DOWN(STM32_DMA_MAX_DATA_ITEMS, 16) #define STM32_DMA_MAX_CHANNELS 0x08 #define STM32_DMA_MAX_REQUEST_ID 0x08 #define STM32_DMA_MAX_DATA_PARAM 0x03 @@ -869,7 +872,7 @@ static struct dma_async_tx_descriptor *stm32_dma_prep_slave_sg( desc->sg_req[i].len = sg_dma_len(sg); nb_data_items = desc->sg_req[i].len / buswidth; - if (nb_data_items > STM32_DMA_MAX_DATA_ITEMS) { + if (nb_data_items > STM32_DMA_ALIGNED_MAX_DATA_ITEMS) { dev_err(chan2dev(chan), "nb items not supported\n"); goto err; } @@ -935,7 +938,7 @@ static struct dma_async_tx_descriptor *stm32_dma_prep_dma_cyclic( return NULL; nb_data_items = period_len / buswidth; - if (nb_data_items > STM32_DMA_MAX_DATA_ITEMS) { + if (nb_data_items > STM32_DMA_ALIGNED_MAX_DATA_ITEMS) { dev_err(chan2dev(chan), "number of items not supported\n"); return NULL; } @@ -985,7 +988,7 @@ static struct dma_async_tx_descriptor *stm32_dma_prep_dma_memcpy( u32 num_sgs, best_burst, dma_burst, threshold; int i; - num_sgs = DIV_ROUND_UP(len, STM32_DMA_MAX_DATA_ITEMS); + num_sgs = DIV_ROUND_UP(len, STM32_DMA_ALIGNED_MAX_DATA_ITEMS); desc = stm32_dma_alloc_desc(num_sgs); if (!desc) return NULL; @@ -994,7 +997,7 @@ static struct dma_async_tx_descriptor *stm32_dma_prep_dma_memcpy( for (offset = 0, i = 0; offset < len; offset += xfer_count, i++) { xfer_count = min_t(size_t, len - offset, - STM32_DMA_MAX_DATA_ITEMS); + STM32_DMA_ALIGNED_MAX_DATA_ITEMS); /* Compute best burst size */ max_width = DMA_SLAVE_BUSWIDTH_1_BYTE; -- 2.19.0.605.g01d371f741-goog From mboxrd@z Thu Jan 1 00:00:00 1970 From: joel@joelfernandes.org (Joel Fernandes (Google)) Date: Mon, 8 Oct 2018 22:47:51 -0700 Subject: [PATCH 6/7] dmaengine: stm32-dma: fix max items per transfer In-Reply-To: <20181009054752.145978-1-joel@joelfernandes.org> References: <20181009054752.145978-1-joel@joelfernandes.org> Message-ID: <20181009054752.145978-7-joel@joelfernandes.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org From: Pierre Yves MORDRET Having 0 in item counter register is valid and stands for a "No or Ended transfer". Therefore valid transfer starts from @+0 to @+0xFFFE leading to unaligned scatter gather at boundary. Thus it's safer to round down this value on its FIFO size (16 Bytes). Signed-off-by: Pierre-Yves MORDRET Signed-off-by: Vinod Koul --- drivers/dma/stm32-dma.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/dma/stm32-dma.c b/drivers/dma/stm32-dma.c index b40486454a2c..05a2974cd2c0 100644 --- a/drivers/dma/stm32-dma.c +++ b/drivers/dma/stm32-dma.c @@ -38,10 +38,6 @@ #define STM32_DMA_TEI BIT(3) /* Transfer Error Interrupt */ #define STM32_DMA_DMEI BIT(2) /* Direct Mode Error Interrupt */ #define STM32_DMA_FEI BIT(0) /* FIFO Error Interrupt */ -#define STM32_DMA_MASKI (STM32_DMA_TCI \ - | STM32_DMA_TEI \ - | STM32_DMA_DMEI \ - | STM32_DMA_FEI) /* DMA Stream x Configuration Register */ #define STM32_DMA_SCR(x) (0x0010 + 0x18 * (x)) /* x = 0..7 */ @@ -118,6 +114,13 @@ #define STM32_DMA_FIFO_THRESHOLD_FULL 0x03 #define STM32_DMA_MAX_DATA_ITEMS 0xffff +/* + * Valid transfer starts from @0 to @0xFFFE leading to unaligned scatter + * gather at boundary. Thus it's safer to round down this value on FIFO + * size (16 Bytes) + */ +#define STM32_DMA_ALIGNED_MAX_DATA_ITEMS \ + ALIGN_DOWN(STM32_DMA_MAX_DATA_ITEMS, 16) #define STM32_DMA_MAX_CHANNELS 0x08 #define STM32_DMA_MAX_REQUEST_ID 0x08 #define STM32_DMA_MAX_DATA_PARAM 0x03 @@ -869,7 +872,7 @@ static struct dma_async_tx_descriptor *stm32_dma_prep_slave_sg( desc->sg_req[i].len = sg_dma_len(sg); nb_data_items = desc->sg_req[i].len / buswidth; - if (nb_data_items > STM32_DMA_MAX_DATA_ITEMS) { + if (nb_data_items > STM32_DMA_ALIGNED_MAX_DATA_ITEMS) { dev_err(chan2dev(chan), "nb items not supported\n"); goto err; } @@ -935,7 +938,7 @@ static struct dma_async_tx_descriptor *stm32_dma_prep_dma_cyclic( return NULL; nb_data_items = period_len / buswidth; - if (nb_data_items > STM32_DMA_MAX_DATA_ITEMS) { + if (nb_data_items > STM32_DMA_ALIGNED_MAX_DATA_ITEMS) { dev_err(chan2dev(chan), "number of items not supported\n"); return NULL; } @@ -985,7 +988,7 @@ static struct dma_async_tx_descriptor *stm32_dma_prep_dma_memcpy( u32 num_sgs, best_burst, dma_burst, threshold; int i; - num_sgs = DIV_ROUND_UP(len, STM32_DMA_MAX_DATA_ITEMS); + num_sgs = DIV_ROUND_UP(len, STM32_DMA_ALIGNED_MAX_DATA_ITEMS); desc = stm32_dma_alloc_desc(num_sgs); if (!desc) return NULL; @@ -994,7 +997,7 @@ static struct dma_async_tx_descriptor *stm32_dma_prep_dma_memcpy( for (offset = 0, i = 0; offset < len; offset += xfer_count, i++) { xfer_count = min_t(size_t, len - offset, - STM32_DMA_MAX_DATA_ITEMS); + STM32_DMA_ALIGNED_MAX_DATA_ITEMS); /* Compute best burst size */ max_width = DMA_SLAVE_BUSWIDTH_1_BYTE; -- 2.19.0.605.g01d371f741-goog