From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [7/7] dmaengine: stm32-dma: properly mask irq bits From: Joel Fernandes Message-Id: <20181009054752.145978-8-joel@joelfernandes.org> Date: Mon, 8 Oct 2018 22:47:52 -0700 To: stable@vger.kernel.org Cc: Pierre Yves MORDRET , Antonio Borneo , Vinod Koul , gregkh@linuxfoundation.org, Alexandre Torgue , Dan Williams , dmaengine@vger.kernel.org, "Joel Fernandes (Google)" , "moderated list:ARM/STM32 ARCHITECTURE" , linux-kernel@vger.kernel.org, Maxime Coquelin List-ID: RnJvbTogUGllcnJlIFl2ZXMgTU9SRFJFVCA8cGllcnJlLXl2ZXMubW9yZHJldEBzdC5jb20+CgpB IHNpbmdsZSByZWdpc3RlciBvZiB0aGUgY29udHJvbGxlciBob2xkcyB0aGUgaW5mb3JtYXRpb24g Zm9yIGZvdXIgZG1hCmNoYW5uZWxzLgpUaGUgZnVuY3Rpb25zIHN0bTMyX2RtYV9pcnFfc3RhdHVz KCkgZG9uJ3QgbWFzayB0aGUgcmVsZXZhbnQgYml0cyBhZnRlcgp0aGUgc2hpZnQsIHRodXMgYWRq YWNlbnQgY2hhbm5lbCdzIHN0YXR1cyBpcyBhbHNvIHJlcG9ydGVkIGluIHRoZSByZXR1cm5lZAp2 YWx1ZS4KRml4ZWQgYnkgbWFza2luZyB0aGUgdmFsdWUgYmVmb3JlIHJldHVybmluZyBpdC4KClNp bWlsYXJseSwgdGhlIGZ1bmN0aW9uIHN0bTMyX2RtYV9pcnFfY2xlYXIoKSBkb24ndCBtYXNrIHRo ZSBpbnB1dCB2YWx1ZQpiZWZvcmUgc2hpZnRpbmcgaXQsIHRodXMgYW4gaW5jb3JyZWN0IGlucHV0 IHZhbHVlIGNvdWxkIGRpc2FibGUgdGhlCmludGVycnVwdHMgb2YgYWRqYWNlbnQgY2hhbm5lbHMu CkZpeGVkIGJ5IG1hc2tpbmcgdGhlIGlucHV0IHZhbHVlIGJlZm9yZSB1c2luZyBpdC4KClNpZ25l ZC1vZmYtYnk6IFBpZXJyZS1ZdmVzIE1PUkRSRVQgPHBpZXJyZS15dmVzLm1vcmRyZXRAc3QuY29t PgpTaWduZWQtb2ZmLWJ5OiBBbnRvbmlvIEJvcm5lbyA8Ym9ybmVvLmFudG9uaW9AZ21haWwuY29t PgpTaWduZWQtb2ZmLWJ5OiBWaW5vZCBLb3VsIDx2aW5vZC5rb3VsQGludGVsLmNvbT4KLS0tCiBk cml2ZXJzL2RtYS9zdG0zMi1kbWEuYyB8IDcgKysrKysrLQogMSBmaWxlIGNoYW5nZWQsIDYgaW5z ZXJ0aW9ucygrKSwgMSBkZWxldGlvbigtKQoKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZG1hL3N0bTMy LWRtYS5jIGIvZHJpdmVycy9kbWEvc3RtMzItZG1hLmMKaW5kZXggMDVhMjk3NGNkMmMwLi44YzU4 MDczNjJhMjUgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZG1hL3N0bTMyLWRtYS5jCisrKyBiL2RyaXZl cnMvZG1hL3N0bTMyLWRtYS5jCkBAIC0zOCw2ICszOCwxMCBAQAogI2RlZmluZSBTVE0zMl9ETUFf VEVJCQkJQklUKDMpIC8qIFRyYW5zZmVyIEVycm9yIEludGVycnVwdCAqLwogI2RlZmluZSBTVE0z Ml9ETUFfRE1FSQkJCUJJVCgyKSAvKiBEaXJlY3QgTW9kZSBFcnJvciBJbnRlcnJ1cHQgKi8KICNk ZWZpbmUgU1RNMzJfRE1BX0ZFSQkJCUJJVCgwKSAvKiBGSUZPIEVycm9yIEludGVycnVwdCAqLwor I2RlZmluZSBTVE0zMl9ETUFfTUFTS0kJCQkoU1RNMzJfRE1BX1RDSSBcCisJCQkJCSB8IFNUTTMy X0RNQV9URUkgXAorCQkJCQkgfCBTVE0zMl9ETUFfRE1FSSBcCisJCQkJCSB8IFNUTTMyX0RNQV9G RUkpCiAKIC8qIERNQSBTdHJlYW0geCBDb25maWd1cmF0aW9uIFJlZ2lzdGVyICovCiAjZGVmaW5l IFNUTTMyX0RNQV9TQ1IoeCkJCSgweDAwMTAgKyAweDE4ICogKHgpKSAvKiB4ID0gMC4uNyAqLwpA QCAtNDA1LDcgKzQwOSw3IEBAIHN0YXRpYyB1MzIgc3RtMzJfZG1hX2lycV9zdGF0dXMoc3RydWN0 IHN0bTMyX2RtYV9jaGFuICpjaGFuKQogCiAJZmxhZ3MgPSBkbWFfaXNyID4+ICgoKGNoYW4tPmlk ICYgMikgPDwgMykgfCAoKGNoYW4tPmlkICYgMSkgKiA2KSk7CiAKLQlyZXR1cm4gZmxhZ3M7CisJ cmV0dXJuIGZsYWdzICYgU1RNMzJfRE1BX01BU0tJOwogfQogCiBzdGF0aWMgdm9pZCBzdG0zMl9k bWFfaXJxX2NsZWFyKHN0cnVjdCBzdG0zMl9kbWFfY2hhbiAqY2hhbiwgdTMyIGZsYWdzKQpAQCAt NDIwLDYgKzQyNCw3IEBAIHN0YXRpYyB2b2lkIHN0bTMyX2RtYV9pcnFfY2xlYXIoc3RydWN0IHN0 bTMyX2RtYV9jaGFuICpjaGFuLCB1MzIgZmxhZ3MpCiAJICogSWYgKGNoICUgNCkgaXMgMiBvciAz LCBsZWZ0IHNoaWZ0IHRoZSBtYXNrIGJ5IDE2IGJpdHMuCiAJICogSWYgKGNoICUgNCkgaXMgMSBv ciAzLCBhZGRpdGlvbmFsbHkgbGVmdCBzaGlmdCB0aGUgbWFzayBieSA2IGJpdHMuCiAJICovCisJ ZmxhZ3MgJj0gU1RNMzJfRE1BX01BU0tJOwogCWRtYV9pZmNyID0gZmxhZ3MgPDwgKCgoY2hhbi0+ aWQgJiAyKSA8PCAzKSB8ICgoY2hhbi0+aWQgJiAxKSAqIDYpKTsKIAogCWlmIChjaGFuLT5pZCAm IDQpCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3FB3AC64EB0 for ; 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Mon, 08 Oct 2018 22:48:17 -0700 (PDT) Received: from joelaf.mtv.corp.google.com ([2620:0:1000:1601:3aef:314f:b9ea:889f]) by smtp.gmail.com with ESMTPSA id a15-v6sm16886234pff.8.2018.10.08.22.48.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 08 Oct 2018 22:48:16 -0700 (PDT) From: "Joel Fernandes (Google)" To: stable@vger.kernel.org Cc: Pierre Yves MORDRET , Antonio Borneo , Vinod Koul , gregkh@linuxfoundation.org, Alexandre Torgue , Dan Williams , dmaengine@vger.kernel.org, "Joel Fernandes (Google)" , linux-arm-kernel@lists.infradead.org (moderated list:ARM/STM32 ARCHITECTURE), linux-kernel@vger.kernel.org, Maxime Coquelin Subject: [PATCH 7/7] dmaengine: stm32-dma: properly mask irq bits Date: Mon, 8 Oct 2018 22:47:52 -0700 Message-Id: <20181009054752.145978-8-joel@joelfernandes.org> X-Mailer: git-send-email 2.19.0.605.g01d371f741-goog In-Reply-To: <20181009054752.145978-1-joel@joelfernandes.org> References: <20181009054752.145978-1-joel@joelfernandes.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Pierre Yves MORDRET A single register of the controller holds the information for four dma channels. The functions stm32_dma_irq_status() don't mask the relevant bits after the shift, thus adjacent channel's status is also reported in the returned value. Fixed by masking the value before returning it. Similarly, the function stm32_dma_irq_clear() don't mask the input value before shifting it, thus an incorrect input value could disable the interrupts of adjacent channels. Fixed by masking the input value before using it. Signed-off-by: Pierre-Yves MORDRET Signed-off-by: Antonio Borneo Signed-off-by: Vinod Koul --- drivers/dma/stm32-dma.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/dma/stm32-dma.c b/drivers/dma/stm32-dma.c index 05a2974cd2c0..8c5807362a25 100644 --- a/drivers/dma/stm32-dma.c +++ b/drivers/dma/stm32-dma.c @@ -38,6 +38,10 @@ #define STM32_DMA_TEI BIT(3) /* Transfer Error Interrupt */ #define STM32_DMA_DMEI BIT(2) /* Direct Mode Error Interrupt */ #define STM32_DMA_FEI BIT(0) /* FIFO Error Interrupt */ +#define STM32_DMA_MASKI (STM32_DMA_TCI \ + | STM32_DMA_TEI \ + | STM32_DMA_DMEI \ + | STM32_DMA_FEI) /* DMA Stream x Configuration Register */ #define STM32_DMA_SCR(x) (0x0010 + 0x18 * (x)) /* x = 0..7 */ @@ -405,7 +409,7 @@ static u32 stm32_dma_irq_status(struct stm32_dma_chan *chan) flags = dma_isr >> (((chan->id & 2) << 3) | ((chan->id & 1) * 6)); - return flags; + return flags & STM32_DMA_MASKI; } static void stm32_dma_irq_clear(struct stm32_dma_chan *chan, u32 flags) @@ -420,6 +424,7 @@ static void stm32_dma_irq_clear(struct stm32_dma_chan *chan, u32 flags) * If (ch % 4) is 2 or 3, left shift the mask by 16 bits. * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits. */ + flags &= STM32_DMA_MASKI; dma_ifcr = flags << (((chan->id & 2) << 3) | ((chan->id & 1) * 6)); if (chan->id & 4) -- 2.19.0.605.g01d371f741-goog From mboxrd@z Thu Jan 1 00:00:00 1970 From: joel@joelfernandes.org (Joel Fernandes (Google)) Date: Mon, 8 Oct 2018 22:47:52 -0700 Subject: [PATCH 7/7] dmaengine: stm32-dma: properly mask irq bits In-Reply-To: <20181009054752.145978-1-joel@joelfernandes.org> References: <20181009054752.145978-1-joel@joelfernandes.org> Message-ID: <20181009054752.145978-8-joel@joelfernandes.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org From: Pierre Yves MORDRET A single register of the controller holds the information for four dma channels. The functions stm32_dma_irq_status() don't mask the relevant bits after the shift, thus adjacent channel's status is also reported in the returned value. Fixed by masking the value before returning it. Similarly, the function stm32_dma_irq_clear() don't mask the input value before shifting it, thus an incorrect input value could disable the interrupts of adjacent channels. Fixed by masking the input value before using it. Signed-off-by: Pierre-Yves MORDRET Signed-off-by: Antonio Borneo Signed-off-by: Vinod Koul --- drivers/dma/stm32-dma.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/dma/stm32-dma.c b/drivers/dma/stm32-dma.c index 05a2974cd2c0..8c5807362a25 100644 --- a/drivers/dma/stm32-dma.c +++ b/drivers/dma/stm32-dma.c @@ -38,6 +38,10 @@ #define STM32_DMA_TEI BIT(3) /* Transfer Error Interrupt */ #define STM32_DMA_DMEI BIT(2) /* Direct Mode Error Interrupt */ #define STM32_DMA_FEI BIT(0) /* FIFO Error Interrupt */ +#define STM32_DMA_MASKI (STM32_DMA_TCI \ + | STM32_DMA_TEI \ + | STM32_DMA_DMEI \ + | STM32_DMA_FEI) /* DMA Stream x Configuration Register */ #define STM32_DMA_SCR(x) (0x0010 + 0x18 * (x)) /* x = 0..7 */ @@ -405,7 +409,7 @@ static u32 stm32_dma_irq_status(struct stm32_dma_chan *chan) flags = dma_isr >> (((chan->id & 2) << 3) | ((chan->id & 1) * 6)); - return flags; + return flags & STM32_DMA_MASKI; } static void stm32_dma_irq_clear(struct stm32_dma_chan *chan, u32 flags) @@ -420,6 +424,7 @@ static void stm32_dma_irq_clear(struct stm32_dma_chan *chan, u32 flags) * If (ch % 4) is 2 or 3, left shift the mask by 16 bits. * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits. */ + flags &= STM32_DMA_MASKI; dma_ifcr = flags << (((chan->id & 2) << 3) | ((chan->id & 1) * 6)); if (chan->id & 4) -- 2.19.0.605.g01d371f741-goog