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[60.240.121.136]) by smtp.gmail.com with ESMTPSA id x69-v6sm26733261pff.175.2018.10.08.22.31.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 08 Oct 2018 22:31:03 -0700 (PDT) Date: Tue, 9 Oct 2018 15:30:58 +1000 From: Nicholas Piggin To: Christophe LEROY Subject: Re: [PATCH v2 3/3] powerpc: machine check interrupt is a non-maskable interrupt Message-ID: <20181009153058.2564e7a1@roar.ozlabs.ibm.com> In-Reply-To: References: <20170719065912.19183-1-npiggin@gmail.com> <20170719065912.19183-4-npiggin@gmail.com> <30487984-752a-960d-6aae-6571c55c7ba5@c-s.fr> <20181009143241.026f3e7f@roar.ozlabs.ibm.com> X-Mailer: Claws Mail 3.17.0 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mahesh Jagannath Salgaonkar , linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Tue, 9 Oct 2018 06:46:30 +0200 Christophe LEROY wrote: > Le 09/10/2018 =C3=A0 06:32, Nicholas Piggin a =C3=A9crit=C2=A0: > > On Mon, 8 Oct 2018 17:39:11 +0200 > > Christophe LEROY wrote: > > =20 > >> Hi Nick, > >> > >> Le 19/07/2017 =C3=A0 08:59, Nicholas Piggin a =C3=A9crit=C2=A0: =20 > >>> Use nmi_enter similarly to system reset interrupts. This uses NMI > >>> printk NMI buffers and turns off various debugging facilities that > >>> helps avoid tripping on ourselves or other CPUs. > >>> > >>> Signed-off-by: Nicholas Piggin > >>> --- > >>> arch/powerpc/kernel/traps.c | 9 ++++++--- > >>> 1 file changed, 6 insertions(+), 3 deletions(-) > >>> > >>> diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c > >>> index 2849c4f50324..6d31f9d7c333 100644 > >>> --- a/arch/powerpc/kernel/traps.c > >>> +++ b/arch/powerpc/kernel/traps.c > >>> @@ -789,8 +789,10 @@ int machine_check_generic(struct pt_regs *regs) > >>> =20 > >>> void machine_check_exception(struct pt_regs *regs) > >>> { > >>> - enum ctx_state prev_state =3D exception_enter(); > >>> int recover =3D 0; > >>> + bool nested =3D in_nmi(); > >>> + if (!nested) > >>> + nmi_enter(); =20 > >> > >> This alters preempt_count, then when die() is called > >> in_interrupt() returns true allthough the trap didn't happen in > >> interrupt, so oops_end() panics for "fatal exception in interrupt" > >> instead of gently sending SIGBUS the faulting app. =20 > >=20 > > Thanks for tracking that down. > > =20 > >> Any idea on how to fix this ? =20 > >=20 > > I would say we have to deliver the sigbus by hand. > >=20 > > if ((user_mode(regs))) > > _exception(SIGBUS, regs, BUS_MCEERR_AR, regs->nip); > > else > > die("Machine check", regs, SIGBUS); > > =20 >=20 > And what about all the other things done by 'die()' ? >=20 > And what if it is a kernel thread ? >=20 > In one of my boards, I have a kernel thread regularly checking the HW,=20 > and if it gets a machine check I expect it to gently stop and the die=20 > notification to be delivered to all registered notifiers. >=20 > Until before this patch, it was working well. I guess the alternative is we could check regs->trap for machine check in the die test. Complication is having to account for MCE in an interrupt handler. if (in_interrupt()) { if (!IS_MCHECK_EXC(regs) || (irq_count() - (NMI_OFFSET + HA= RDIRQ_OFFSET))) panic("Fatal exception in interrupt"); } Something like that might work for you? We needs a ppc64 macro for the MCE, and can probably add something like in_nmi_from_interrupt() for the second part of the test. Thanks, Nick