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[60.240.121.136]) by smtp.gmail.com with ESMTPSA id q2-v6sm69654360pfc.17.2018.10.09.05.14.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 09 Oct 2018 05:14:53 -0700 (PDT) Date: Tue, 9 Oct 2018 22:14:46 +1000 From: Nicholas Piggin To: Christophe LEROY Subject: Re: [PATCH v2 3/3] powerpc: machine check interrupt is a non-maskable interrupt Message-ID: <20181009221446.33b926e3@roar.ozlabs.ibm.com> In-Reply-To: References: <20170719065912.19183-1-npiggin@gmail.com> <20170719065912.19183-4-npiggin@gmail.com> <30487984-752a-960d-6aae-6571c55c7ba5@c-s.fr> <20181009143241.026f3e7f@roar.ozlabs.ibm.com> <20181009153058.2564e7a1@roar.ozlabs.ibm.com> <0539727f-8420-3176-30b5-f4a6a1ccd4a4@c-s.fr> <20181009211650.042d428c@roar.ozlabs.ibm.com> X-Mailer: Claws Mail 3.17.0 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mahesh Jagannath Salgaonkar , linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Tue, 9 Oct 2018 14:01:37 +0200 Christophe LEROY wrote: > Le 09/10/2018 =C3=A0 13:16, Nicholas Piggin a =C3=A9crit=C2=A0: > > On Tue, 9 Oct 2018 09:36:18 +0000 > > Christophe Leroy wrote: > > =20 > >> On 10/09/2018 05:30 AM, Nicholas Piggin wrote: =20 > >>> On Tue, 9 Oct 2018 06:46:30 +0200 > >>> Christophe LEROY wrote: > >>> =20 > >>>> Le 09/10/2018 =C3=A0 06:32, Nicholas Piggin a =C3=A9crit=C2=A0: =20 > >>>>> On Mon, 8 Oct 2018 17:39:11 +0200 > >>>>> Christophe LEROY wrote: > >>>>> =20 > >>>>>> Hi Nick, > >>>>>> > >>>>>> Le 19/07/2017 =C3=A0 08:59, Nicholas Piggin a =C3=A9crit=C2=A0: =20 > >>>>>>> Use nmi_enter similarly to system reset interrupts. This uses NMI > >>>>>>> printk NMI buffers and turns off various debugging facilities that > >>>>>>> helps avoid tripping on ourselves or other CPUs. > >>>>>>> > >>>>>>> Signed-off-by: Nicholas Piggin > >>>>>>> --- > >>>>>>> arch/powerpc/kernel/traps.c | 9 ++++++--- > >>>>>>> 1 file changed, 6 insertions(+), 3 deletions(-) > >>>>>>> > >>>>>>> diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/tr= aps.c > >>>>>>> index 2849c4f50324..6d31f9d7c333 100644 > >>>>>>> --- a/arch/powerpc/kernel/traps.c > >>>>>>> +++ b/arch/powerpc/kernel/traps.c > >>>>>>> @@ -789,8 +789,10 @@ int machine_check_generic(struct pt_regs *re= gs) > >>>>>>> =20 > >>>>>>> void machine_check_exception(struct pt_regs *regs) > >>>>>>> { > >>>>>>> - enum ctx_state prev_state =3D exception_enter(); > >>>>>>> int recover =3D 0; > >>>>>>> + bool nested =3D in_nmi(); > >>>>>>> + if (!nested) > >>>>>>> + nmi_enter(); =20 > >>>>>> > >>>>>> This alters preempt_count, then when die() is called > >>>>>> in_interrupt() returns true allthough the trap didn't happen in > >>>>>> interrupt, so oops_end() panics for "fatal exception in interrupt" > >>>>>> instead of gently sending SIGBUS the faulting app. =20 > >>>>> > >>>>> Thanks for tracking that down. > >>>>> =20 > >>>>>> Any idea on how to fix this ? =20 > >>>>> > >>>>> I would say we have to deliver the sigbus by hand. > >>>>> > >>>>> if ((user_mode(regs))) > >>>>> _exception(SIGBUS, regs, BUS_MCEERR_AR, regs->nip); > >>>>> else > >>>>> die("Machine check", regs, SIGBUS); > >>>>> =20 > >>>> > >>>> And what about all the other things done by 'die()' ? > >>>> > >>>> And what if it is a kernel thread ? > >>>> > >>>> In one of my boards, I have a kernel thread regularly checking the H= W, > >>>> and if it gets a machine check I expect it to gently stop and the die > >>>> notification to be delivered to all registered notifiers. > >>>> > >>>> Until before this patch, it was working well. =20 > >>> > >>> I guess the alternative is we could check regs->trap for machine > >>> check in the die test. Complication is having to account for MCE > >>> in an interrupt handler. > >>> > >>> if (in_interrupt()) { > >>> if (!IS_MCHECK_EXC(regs) || (irq_count() - (NMI_OFF= SET + HARDIRQ_OFFSET))) > >>> panic("Fatal exception in interrupt"); > >>> } > >>> > >>> Something like that might work for you? We needs a ppc64 macro for the > >>> MCE, and can probably add something like in_nmi_from_interrupt() for > >>> the second part of the test. =20 > >> > >> Don't know, I'm away from home on business trip so I won't be able to > >> test anything before next week. However it looks more or less like a > >> hack, doesn't it ? =20 > >=20 > > I thought it seemed okay (with the right functions added). Actually it > > could be a bit nicer to do this, then it works generally : > >=20 > > if (in_interrupt()) { > > if (!in_nmi() || in_nmi_from_interrupt()) > > panic("Fatal exception in interrupt"); > > } =20 >=20 >=20 > Yes looks nice, but: > 1/ what is in_nmi_from_interrupt() ? Is it (in_nmi() && (in_irq() ||=20 > in_softirq()) ? return (irq_count() - (NMI_OFFSET + HARDIRQ_OFFSET))) !=3D 0; (basically just in_interrupt() with the nmi_enter undone) > 2/ what about in_nmi_from_nmi(), how do we detect that ? Oh good point, I'm not sure. I guess we could irq_enter() in the nested case, I think that would make in_nmi_from_interrupt() return true. Thanks, Nick