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Date: Mon, 15 Oct 2018 17:36:10 +0200
From: Fredrik Noring <noring@nocrew.org>
Message-ID: <20181015153610.GA2364@sx9>
References: <20181014142928.2784-1-f4bug@amsat.org> <20181014164140.GB2319@sx9>
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Subject: Re: [Qemu-devel] [PATCH] target/mips: Support Toshiba specific
 three-operand MADD and MADDU
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To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= <f4bug@amsat.org>
Cc: Richard Henderson <richard.henderson@linaro.org>, Aleksandar Markovic <amarkovic@wavecomp.com>, "Maciej W. Rozycki" <macro@linux-mips.org>, Aurelien Jarno <aurelien@aurel32.net>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, =?utf-8?Q?J=C3=BCrgen?= Urban <JuergenUrban@gmx.de>

Hi Philippe,

> That's true it is not reachable, it lacks the INSN_R3900 definition,
> used by the R3900 mips_def_t.
> 
> I'll stop bothering with this until the code is reachable (my branch posted).

I would be happy if your patch could be merged soon. Adding the following
five lines to it would make both MADD and MADDU immediately reachable and
testable, at least for the R5900 to begin with:

--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -22768,6 +22768,11 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
     switch (op1) {
     case OPC_MADD: /* Multiply and add/sub */
     case OPC_MADDU:
+        if (ctx->insn_flags & INSN_R5900) {
+            gen_mul_txx9(ctx, op1, 0, rd, rs, rt);
+            break;
+        }
+        /* Fallthrough */
     case OPC_MSUB:
     case OPC_MSUBU:
         check_insn(ctx, ISA_MIPS32);

> To be able to use the 64-bit result we need to use tcg_gen_mul_i64().

tcg_gen_muls2_i32 produces a 64-bit result in two 32-bit registers, and
tcg_gen_add2_i32 seems to correspond to adding such registers. And then
tcg_gen_ext_i32_tl could be used to extend the results to 64 bits. Look
at the cases for MULT and MULTU, since they are very similar.

Fredrik