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Wed, 17 Oct 2018 15:07:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1539788876; bh=aIDjsHgp29qxLYl8k2zdVmwWr1qd6bytssBEyFK+7JI=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=D6T+lnGLmZGetw1PqUwJOfJS6Y/PXrEgP7WMTCMQr8SDSToBbSpJsMnT3Iq96JoL8 T57/xqAjnZaMTUG481FPbsmZwHwpv74CxUNXSpy8d2bvk1Fp5OEfku/9t6XjR7nKq6 MGn7ubI5K3Phh3iFguA41XEtUFGT+DgzwklhRc3w= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 51E4C605A4 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org Date: Wed, 17 Oct 2018 09:07:52 -0600 From: Jordan Crouse To: Jean-Philippe Brucker Cc: iommu@lists.linux-foundation.org, joro@8bytes.org, linux-pci@vger.kernel.org, alex.williamson@redhat.com, Jonathan.Cameron@huawei.com, jacob.jun.pan@linux.intel.com, christian.koenig@amd.com, eric.auger@redhat.com, kevin.tian@intel.com, yi.l.liu@intel.com, andrew.murray@arm.com, will.deacon@arm.com, robin.murphy@arm.com, ashok.raj@intel.com, baolu.lu@linux.intel.com, xuzaibo@huawei.com, liguozhu@hisilicon.com, okaya@codeaurora.org, bharatku@xilinx.com, ilias.apalodimas@linaro.org, shunyong.yang@hxt-semitech.com Subject: Re: [RFC PATCH v3 10/10] iommu/sva: Add support for private PASIDs Message-ID: <20181017150751.GF4751@jcrouse-lnx.qualcomm.com> Mail-Followup-To: Jean-Philippe Brucker , iommu@lists.linux-foundation.org, joro@8bytes.org, linux-pci@vger.kernel.org, alex.williamson@redhat.com, Jonathan.Cameron@huawei.com, jacob.jun.pan@linux.intel.com, christian.koenig@amd.com, eric.auger@redhat.com, kevin.tian@intel.com, yi.l.liu@intel.com, andrew.murray@arm.com, will.deacon@arm.com, robin.murphy@arm.com, ashok.raj@intel.com, baolu.lu@linux.intel.com, xuzaibo@huawei.com, liguozhu@hisilicon.com, okaya@codeaurora.org, bharatku@xilinx.com, ilias.apalodimas@linaro.org, shunyong.yang@hxt-semitech.com References: <20180920170046.20154-1-jean-philippe.brucker@arm.com> <20180920170046.20154-11-jean-philippe.brucker@arm.com> <20181012143229.GI9977@jcrouse-lnx.qualcomm.com> <3e1b58bb-eb16-5855-2922-2b15b37ba971@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <3e1b58bb-eb16-5855-2922-2b15b37ba971@arm.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Wed, Oct 17, 2018 at 03:21:43PM +0100, Jean-Philippe Brucker wrote: > Hi Jordan, > > On 12/10/2018 15:32, Jordan Crouse wrote: > > On Thu, Sep 20, 2018 at 06:00:46PM +0100, Jean-Philippe Brucker wrote: > >> Provide an API for allocating PASIDs and populating them manually. To ease > >> cleanup and factor allocation code, reuse the io_mm structure for private > >> PASID. Private io_mm has a NULL mm_struct pointer, and cannot be bound to > >> multiple devices. The mm_alloc() IOMMU op must now check if the mm > >> argument is NULL, in which case it should allocate io_pgtables instead of > >> binding to an mm. > >> > >> Signed-off-by: Jordan Crouse > >> Signed-off-by: Jean-Philippe Brucker > >> --- > >> Sadly this probably won't be the final thing. The API in this patch is > >> used like this: > >> > >> iommu_sva_alloc_pasid(dev, &io_mm) -> PASID > >> iommu_sva_map(io_mm, ...) > >> iommu_sva_unmap(io_mm, ...) > >> iommu_sva_free_pasid(dev, io_mm) > >> > >> The proposed API for auxiliary domains is in an early stage but might > >> replace this patch and could be used like this: > >> > >> iommu_enable_aux_domain(dev) > >> d = iommu_domain_alloc() > >> iommu_attach_aux(dev, d) > >> iommu_aux_id(d) -> PASID > >> iommu_map(d, ...) > >> iommu_unmap(d, ...) > >> iommu_detach_aux(dev, d) > >> iommu_domain_free(d) > >> > >> The advantage being that the driver doesn't have to use a special > >> version of map/unmap/etc. > > > > Hi Jean-Phillippe - > > > > Have you thought about this any more? I want to send out a > > refresh for the per-context pagetables for arm-smmu so if we want to change > > the underlying assumptions this would be a great time. > > > > For my part I'm okay with either model. In fact the second one is closer > > to the original implementation that I sent out so I have a clear development > > path in mind for either option depending on what the community decides. > > We'll probably go with the second model. I'm trying to make the latest > version work with SMMUv3 > (https://lwn.net/ml/linux-kernel/20181012051632.26064-1-baolu.lu@linux.intel.com/) > and I'd like to send an RFC soon Okay. When you do, I'll try to add the v2 code and make it work with the Adreno GPU. Jordan -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jordan Crouse Subject: Re: [RFC PATCH v3 10/10] iommu/sva: Add support for private PASIDs Date: Wed, 17 Oct 2018 09:07:52 -0600 Message-ID: <20181017150751.GF4751@jcrouse-lnx.qualcomm.com> References: <20180920170046.20154-1-jean-philippe.brucker@arm.com> <20180920170046.20154-11-jean-philippe.brucker@arm.com> <20181012143229.GI9977@jcrouse-lnx.qualcomm.com> <3e1b58bb-eb16-5855-2922-2b15b37ba971@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <3e1b58bb-eb16-5855-2922-2b15b37ba971-5wv7dgnIgG8@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Jean-Philippe Brucker Cc: kevin.tian-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, ashok.raj-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, ilias.apalodimas-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, will.deacon-5wv7dgnIgG8@public.gmane.org, alex.williamson-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, okaya-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, liguozhu-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org, robin.murphy-5wv7dgnIgG8@public.gmane.org, christian.koenig-5C7GfCeVMHo@public.gmane.org List-Id: iommu@lists.linux-foundation.org On Wed, Oct 17, 2018 at 03:21:43PM +0100, Jean-Philippe Brucker wrote: > Hi Jordan, > > On 12/10/2018 15:32, Jordan Crouse wrote: > > On Thu, Sep 20, 2018 at 06:00:46PM +0100, Jean-Philippe Brucker wrote: > >> Provide an API for allocating PASIDs and populating them manually. To ease > >> cleanup and factor allocation code, reuse the io_mm structure for private > >> PASID. Private io_mm has a NULL mm_struct pointer, and cannot be bound to > >> multiple devices. The mm_alloc() IOMMU op must now check if the mm > >> argument is NULL, in which case it should allocate io_pgtables instead of > >> binding to an mm. > >> > >> Signed-off-by: Jordan Crouse > >> Signed-off-by: Jean-Philippe Brucker > >> --- > >> Sadly this probably won't be the final thing. The API in this patch is > >> used like this: > >> > >> iommu_sva_alloc_pasid(dev, &io_mm) -> PASID > >> iommu_sva_map(io_mm, ...) > >> iommu_sva_unmap(io_mm, ...) > >> iommu_sva_free_pasid(dev, io_mm) > >> > >> The proposed API for auxiliary domains is in an early stage but might > >> replace this patch and could be used like this: > >> > >> iommu_enable_aux_domain(dev) > >> d = iommu_domain_alloc() > >> iommu_attach_aux(dev, d) > >> iommu_aux_id(d) -> PASID > >> iommu_map(d, ...) > >> iommu_unmap(d, ...) > >> iommu_detach_aux(dev, d) > >> iommu_domain_free(d) > >> > >> The advantage being that the driver doesn't have to use a special > >> version of map/unmap/etc. > > > > Hi Jean-Phillippe - > > > > Have you thought about this any more? I want to send out a > > refresh for the per-context pagetables for arm-smmu so if we want to change > > the underlying assumptions this would be a great time. > > > > For my part I'm okay with either model. In fact the second one is closer > > to the original implementation that I sent out so I have a clear development > > path in mind for either option depending on what the community decides. > > We'll probably go with the second model. I'm trying to make the latest > version work with SMMUv3 > (https://lwn.net/ml/linux-kernel/20181012051632.26064-1-baolu.lu-VuQAYsv1563Yd54FQh9/CA@public.gmane.org/) > and I'd like to send an RFC soon Okay. When you do, I'll try to add the v2 code and make it work with the Adreno GPU. Jordan -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project