From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59412) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gDJFw-000507-V6 for qemu-devel@nongnu.org; Thu, 18 Oct 2018 21:07:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gDJFl-0003OT-DB for qemu-devel@nongnu.org; Thu, 18 Oct 2018 21:07:09 -0400 Received: from out5-smtp.messagingengine.com ([66.111.4.29]:40869) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gDJFk-00036H-KJ for qemu-devel@nongnu.org; Thu, 18 Oct 2018 21:07:01 -0400 From: "Emilio G. Cota" Date: Thu, 18 Oct 2018 21:06:20 -0400 Message-Id: <20181019010625.25294-52-cota@braap.org> In-Reply-To: <20181019010625.25294-1-cota@braap.org> References: <20181019010625.25294-1-cota@braap.org> Subject: [Qemu-devel] [RFC v3 51/56] riscv: acquire the BQL in cpu_has_work List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Michael Clark , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Soon we will call cpu_has_work without the BQL. Cc: Michael Clark Cc: Palmer Dabbelt Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Emilio G. Cota --- target/riscv/cpu.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d630e8fd6c..b10995c807 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -18,6 +18,7 @@ */ #include "qemu/osdep.h" +#include "qemu/main-loop.h" #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" @@ -244,11 +245,14 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) env->pc = tb->pc; } -static bool riscv_cpu_has_work(CPUState *cs) +static bool riscv_cpu_has_work_locked(CPUState *cs) { #ifndef CONFIG_USER_ONLY RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; + + g_assert(qemu_mutex_iothread_locked()); + /* * Definition of the WFI instruction requires it to ignore the privilege * mode and delegation registers, but respect individual enables @@ -259,6 +263,21 @@ static bool riscv_cpu_has_work(CPUState *cs) #endif } +static bool riscv_cpu_has_work(CPUState *cs) +{ + if (!qemu_mutex_iothread_locked()) { + bool ret; + + cpu_mutex_unlock(cs); + qemu_mutex_lock_iothread(); + cpu_mutex_lock(cs); + ret = riscv_cpu_has_work_locked(cs); + qemu_mutex_unlock_iothread(); + return ret; + } + return riscv_cpu_has_work_locked(cs); +} + void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, target_ulong *data) { -- 2.17.1