[PATCH 1/3] firmware: xilinx: Add fpga API's

[PATCH 1/3] firmware: xilinx: Add fpga API's

[Nava kishore Manne]

This Patch Adds fpga API's to support the Bitstream loading
by using firmware interface.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
---
Changes for v1:
		-None.

Changes for RFC-V2:
                -New Patch.

 drivers/firmware/xilinx/zynqmp.c     | 46 ++++++++++++++++++++++++++++
 include/linux/firmware/xlnx-zynqmp.h |  4 +++
 2 files changed, 50 insertions(+)

diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 84b3fd2eca8b..38a1ab1be03b 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -428,6 +428,50 @@ static int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)
 	return ret;
 }
 
+/**
+ * zynqmp_pm_fpga_load - Perform the fpga load
+ * @address:	Address to write to
+ * @size:	pl bitstream size
+ * @flags:
+ *	BIT(0) - Bit-stream type.
+ *		 0 - Full Bit-stream.
+ *		 1 - Partial Bit-stream.
+ *
+ * This function provides access to pmufw. To transfer
+ * the required bitstream into PL.
+ *
+ * Return: Returns status, either success or error+reason
+ */
+static int zynqmp_pm_fpga_load(const u64 address, const u32 size,
+			       const u32 flags)
+{
+	return zynqmp_pm_invoke_fn(PM_FPGA_LOAD, lower_32_bits(address),
+				   upper_32_bits(address), size, flags, NULL);
+}
+
+/**
+ * zynqmp_pm_fpga_get_status - Read value from PCAP status register
+ * @value: Value to read
+ *
+ * This function provides access to the xilfpga library to get
+ * the PCAP status
+ *
+ * Return: Returns status, either success or error+reason
+ */
+static int zynqmp_pm_fpga_get_status(u32 *value)
+{
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+	int ret;
+
+	if (!value)
+		return -EINVAL;
+
+	ret = zynqmp_pm_invoke_fn(PM_FPGA_GET_STATUS, 0, 0, 0, 0, ret_payload);
+	*value = ret_payload[1];
+
+	return ret;
+}
+
 static const struct zynqmp_eemi_ops eemi_ops = {
 	.get_api_version = zynqmp_pm_get_api_version,
 	.query_data = zynqmp_pm_query_data,
@@ -440,6 +484,8 @@ static const struct zynqmp_eemi_ops eemi_ops = {
 	.clock_getrate = zynqmp_pm_clock_getrate,
 	.clock_setparent = zynqmp_pm_clock_setparent,
 	.clock_getparent = zynqmp_pm_clock_getparent,
+	.fpga_load = zynqmp_pm_fpga_load,
+	.fpga_get_status = zynqmp_pm_fpga_get_status,
 };
 
 /**
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index 015e130431e6..b24400ee630a 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -34,6 +34,8 @@
 
 enum pm_api_id {
 	PM_GET_API_VERSION = 1,
+	PM_FPGA_LOAD = 22,
+	PM_FPGA_GET_STATUS,
 	PM_QUERY_DATA = 35,
 	PM_CLOCK_ENABLE,
 	PM_CLOCK_DISABLE,
@@ -89,6 +91,8 @@ struct zynqmp_pm_query_data {
 
 struct zynqmp_eemi_ops {
 	int (*get_api_version)(u32 *version);
+	int (*fpga_load)(const u64 address, const u32 size, const u32 flags);
+	int (*fpga_get_status)(u32 *value);
 	int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out);
 	int (*clock_enable)(u32 clock_id);
 	int (*clock_disable)(u32 clock_id);
-- 
2.18.0

[PATCH 0/3] Add Bitstream configuration support for ZynqMP

[Nava kishore Manne]

This series of patches are created On top of the
below repo.
//git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git
BRANCH: next/drivers.  

Nava kishore Manne (3):
  firmware: xilinx: Add fpga API's
  dt-bindings: fpga: Add bindings for ZynqMP fpga driver
  fpga manager: Adding FPGA Manager support for Xilinx zynqmp

 .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt   |  17 ++
 drivers/firmware/xilinx/zynqmp.c              |  46 +++++
 drivers/fpga/Kconfig                          |   9 +
 drivers/fpga/Makefile                         |   1 +
 drivers/fpga/zynqmp-fpga.c                    | 159 ++++++++++++++++++
 include/linux/firmware/xlnx-zynqmp.h          |   4 +
 6 files changed, 236 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
 create mode 100644 drivers/fpga/zynqmp-fpga.c

-- 
2.18.0

[PATCH 2/3] dt-bindings: fpga: Add bindings for ZynqMP fpga driver

[Nava kishore Manne]

Add documentation to describe Xilinx ZynqMP fpga driver
bindings.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
---
Changes for v1:
                Created a Seperate(New) DT binding file as
                suggested by Rob.

Changes for RFC-V2:
                -Moved pcap node as a child to firwmare
                 node as suggested by Rob.

 .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt     | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt

diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
new file mode 100644
index 000000000000..248ff0ee60a8
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
@@ -0,0 +1,17 @@
+--------------------------------------------------------------------------
+Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC controlled
+using ZynqMP SoC firmware interface
+--------------------------------------------------------------------------
+For Bitstream configuration on ZynqMp Soc uses processor configuration
+port(PCAP) to configure the programmable logic(PL) through PS by using
+FW interface.
+
+Required properties:
+- compatible: should contain "xlnx,zynqmp-pcap-fpga"
+
+-------
+Example
+-------
+	zynqmp_pcap: pcap {
+		compatible = "xlnx,zynqmp-pcap-fpga";
+	};
-- 
2.18.0

[PATCH 3/3] fpga manager: Adding FPGA Manager support for Xilinx zynqmp

[Nava kishore Manne]

This patch adds FPGA Manager support for the Xilinx
ZynqMp chip.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
---
Changes for v1:
		-None.

Changes for RFC-V2:
                -Updated the Fpga Mgr registrations call's
                 to 4.18

 drivers/fpga/Kconfig       |   9 +++
 drivers/fpga/Makefile      |   1 +
 drivers/fpga/zynqmp-fpga.c | 159 +++++++++++++++++++++++++++++++++++++
 3 files changed, 169 insertions(+)
 create mode 100644 drivers/fpga/zynqmp-fpga.c

diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 1ebcef4bab5b..26ebbcf3d3a3 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -56,6 +56,15 @@ config FPGA_MGR_ZYNQ_FPGA
 	help
 	  FPGA manager driver support for Xilinx Zynq FPGAs.
 
+config FPGA_MGR_ZYNQMP_FPGA
+	tristate "Xilinx Zynqmp FPGA"
+	depends on ARCH_ZYNQMP || COMPILE_TEST
+	help
+	  FPGA manager driver support for Xilinx ZynqMP FPGAs.
+	  This driver uses processor configuration port(PCAP)
+	  to configure the programmable logic(PL) through PS
+	  on ZynqMP SoC.
+
 config FPGA_MGR_XILINX_SPI
 	tristate "Xilinx Configuration over Slave Serial (SPI)"
 	depends on SPI
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 7a2d73ba7122..3488ebbaee46 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)	+= socfpga-a10.o
 obj-$(CONFIG_FPGA_MGR_TS73XX)		+= ts73xx-fpga.o
 obj-$(CONFIG_FPGA_MGR_XILINX_SPI)	+= xilinx-spi.o
 obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)	+= zynq-fpga.o
+obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA)	+= zynqmp-fpga.o
 obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
 obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)    += altera-pr-ip-core-plat.o
 
diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c
new file mode 100644
index 000000000000..2760d7e3872a
--- /dev/null
+++ b/drivers/fpga/zynqmp-fpga.c
@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/fpga/fpga-mgr.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/string.h>
+#include <linux/firmware/xlnx-zynqmp.h>
+
+/* Constant Definitions */
+#define IXR_FPGA_DONE_MASK	0X00000008U
+
+/**
+ * struct zynqmp_fpga_priv - Private data structure
+ * @dev:	Device data structure
+ * @flags:	flags which is used to identify the bitfile type
+ */
+struct zynqmp_fpga_priv {
+	struct device *dev;
+	u32 flags;
+};
+
+static int zynqmp_fpga_ops_write_init(struct fpga_manager *mgr,
+				      struct fpga_image_info *info,
+				      const char *buf, size_t size)
+{
+	struct zynqmp_fpga_priv *priv;
+
+	priv = mgr->priv;
+	priv->flags = info->flags;
+
+	return 0;
+}
+
+static int zynqmp_fpga_ops_write(struct fpga_manager *mgr,
+				 const char *buf, size_t size)
+{
+	struct zynqmp_fpga_priv *priv;
+	char *kbuf;
+	dma_addr_t dma_addr;
+	int ret;
+	const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
+
+	if (!eemi_ops || !eemi_ops->fpga_load)
+		return -ENXIO;
+
+	priv = mgr->priv;
+
+	kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL);
+	if (!kbuf)
+		return -ENOMEM;
+
+	memcpy(kbuf, buf, size);
+
+	wmb(); /* ensure all writes are done before initiate FW call */
+
+	ret = eemi_ops->fpga_load(dma_addr, size, priv->flags);
+
+	dma_free_coherent(priv->dev, size, kbuf, dma_addr);
+
+	return ret;
+}
+
+static int zynqmp_fpga_ops_write_complete(struct fpga_manager *mgr,
+					  struct fpga_image_info *info)
+{
+	return 0;
+}
+
+static enum fpga_mgr_states zynqmp_fpga_ops_state(struct fpga_manager *mgr)
+{
+	u32 status;
+	const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
+
+	if (!eemi_ops || !eemi_ops->fpga_get_status)
+		return FPGA_MGR_STATE_UNKNOWN;
+
+	eemi_ops->fpga_get_status(&status);
+	if (status & IXR_FPGA_DONE_MASK)
+		return FPGA_MGR_STATE_OPERATING;
+
+	return FPGA_MGR_STATE_UNKNOWN;
+}
+
+static const struct fpga_manager_ops zynqmp_fpga_ops = {
+	.state = zynqmp_fpga_ops_state,
+	.write_init = zynqmp_fpga_ops_write_init,
+	.write = zynqmp_fpga_ops_write,
+	.write_complete = zynqmp_fpga_ops_write_complete,
+};
+
+static int zynqmp_fpga_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct zynqmp_fpga_priv *priv;
+	struct fpga_manager *mgr;
+	int err, ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->dev = dev;
+	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
+	if (ret < 0)
+		dev_err(dev, "no usable DMA configuration");
+
+	mgr = fpga_mgr_create(dev, "Xilinx ZynqMP FPGA Manager",
+			      &zynqmp_fpga_ops, priv);
+	if (!mgr)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, mgr);
+
+	err = fpga_mgr_register(mgr);
+	if (err) {
+		dev_err(dev, "unable to register FPGA manager");
+		fpga_mgr_free(mgr);
+		return err;
+	}
+
+	return 0;
+}
+
+static int zynqmp_fpga_remove(struct platform_device *pdev)
+{
+	struct fpga_manager *mgr = platform_get_drvdata(pdev);
+
+	fpga_mgr_unregister(mgr);
+
+	return 0;
+}
+
+static const struct of_device_id zynqmp_fpga_of_match[] = {
+	{ .compatible = "xlnx,zynqmp-pcap-fpga", },
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, zynqmp_fpga_of_match);
+
+static struct platform_driver zynqmp_fpga_driver = {
+	.probe = zynqmp_fpga_probe,
+	.remove = zynqmp_fpga_remove,
+	.driver = {
+		.name = "zynqmp_fpga_manager",
+		.of_match_table = of_match_ptr(zynqmp_fpga_of_match),
+	},
+};
+
+module_platform_driver(zynqmp_fpga_driver);
+
+MODULE_AUTHOR("Nava kishore Manne <navam@xilinx.com>");
+MODULE_DESCRIPTION("Xilinx ZynqMp FPGA Manager");
+MODULE_LICENSE("GPL");
-- 
2.18.0

Re: [PATCH 3/3] fpga manager: Adding FPGA Manager support for Xilinx zynqmp

[Moritz Fischer]

Hi Nava,

Looks good to me, a couple of nits inline below.

On Fri, Oct 19, 2018 at 1:50 AM Nava kishore Manne
<nava.manne@xilinx.com> wrote:
>
> This patch adds FPGA Manager support for the Xilinx
> ZynqMp chip.

Isn't it ZynqMP ?
>
> Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> ---
> Changes for v1:
>                 -None.
>
> Changes for RFC-V2:
>                 -Updated the Fpga Mgr registrations call's
>                  to 4.18
>
>  drivers/fpga/Kconfig       |   9 +++
>  drivers/fpga/Makefile      |   1 +
>  drivers/fpga/zynqmp-fpga.c | 159 +++++++++++++++++++++++++++++++++++++
>  3 files changed, 169 insertions(+)
>  create mode 100644 drivers/fpga/zynqmp-fpga.c
>
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index 1ebcef4bab5b..26ebbcf3d3a3 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -56,6 +56,15 @@ config FPGA_MGR_ZYNQ_FPGA
>         help
>           FPGA manager driver support for Xilinx Zynq FPGAs.
>
> +config FPGA_MGR_ZYNQMP_FPGA
> +       tristate "Xilinx Zynqmp FPGA"
> +       depends on ARCH_ZYNQMP || COMPILE_TEST
> +       help
> +         FPGA manager driver support for Xilinx ZynqMP FPGAs.
> +         This driver uses processor configuration port(PCAP)
This driver uses *the* processor configuration port.

> +         to configure the programmable logic(PL) through PS
> +         on ZynqMP SoC.
> +
>  config FPGA_MGR_XILINX_SPI
>         tristate "Xilinx Configuration over Slave Serial (SPI)"
>         depends on SPI
> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> index 7a2d73ba7122..3488ebbaee46 100644
> --- a/drivers/fpga/Makefile
> +++ b/drivers/fpga/Makefile
> @@ -16,6 +16,7 @@ obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)    += socfpga-a10.o
>  obj-$(CONFIG_FPGA_MGR_TS73XX)          += ts73xx-fpga.o
>  obj-$(CONFIG_FPGA_MGR_XILINX_SPI)      += xilinx-spi.o
>  obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)       += zynq-fpga.o
> +obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA)     += zynqmp-fpga.o
>  obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
>  obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)    += altera-pr-ip-core-plat.o
>
> diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c
> new file mode 100644
> index 000000000000..2760d7e3872a
> --- /dev/null
> +++ b/drivers/fpga/zynqmp-fpga.c
> @@ -0,0 +1,159 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2018 Xilinx, Inc.
> + */
> +
> +#include <linux/dma-mapping.h>
> +#include <linux/fpga/fpga-mgr.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/string.h>
> +#include <linux/firmware/xlnx-zynqmp.h>
> +
> +/* Constant Definitions */
> +#define IXR_FPGA_DONE_MASK     0X00000008U
> +
> +/**
> + * struct zynqmp_fpga_priv - Private data structure
> + * @dev:       Device data structure
> + * @flags:     flags which is used to identify the bitfile type
> + */
> +struct zynqmp_fpga_priv {
> +       struct device *dev;
> +       u32 flags;
> +};
> +
> +static int zynqmp_fpga_ops_write_init(struct fpga_manager *mgr,
> +                                     struct fpga_image_info *info,
> +                                     const char *buf, size_t size)
> +{
> +       struct zynqmp_fpga_priv *priv;
> +
> +       priv = mgr->priv;
> +       priv->flags = info->flags;
> +
> +       return 0;
> +}
> +
> +static int zynqmp_fpga_ops_write(struct fpga_manager *mgr,
> +                                const char *buf, size_t size)
> +{
> +       struct zynqmp_fpga_priv *priv;
> +       char *kbuf;
> +       dma_addr_t dma_addr;
> +       int ret;
> +       const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();

Reverse xmas-tree please, i.e. long lines first.

> +
> +       if (!eemi_ops || !eemi_ops->fpga_load)
> +               return -ENXIO;
> +
> +       priv = mgr->priv;
> +
> +       kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL);
> +       if (!kbuf)
> +               return -ENOMEM;
> +
> +       memcpy(kbuf, buf, size);
> +
> +       wmb(); /* ensure all writes are done before initiate FW call */
> +
> +       ret = eemi_ops->fpga_load(dma_addr, size, priv->flags);
> +
> +       dma_free_coherent(priv->dev, size, kbuf, dma_addr);
> +
> +       return ret;
> +}
> +
> +static int zynqmp_fpga_ops_write_complete(struct fpga_manager *mgr,
> +                                         struct fpga_image_info *info)
> +{
> +       return 0;
> +}
> +
> +static enum fpga_mgr_states zynqmp_fpga_ops_state(struct fpga_manager *mgr)
> +{
> +       u32 status;
> +       const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();

Same here, split it up if necessary.
> +
> +       if (!eemi_ops || !eemi_ops->fpga_get_status)
> +               return FPGA_MGR_STATE_UNKNOWN;
> +
> +       eemi_ops->fpga_get_status(&status);
> +       if (status & IXR_FPGA_DONE_MASK)
> +               return FPGA_MGR_STATE_OPERATING;
> +
> +       return FPGA_MGR_STATE_UNKNOWN;
> +}
> +
> +static const struct fpga_manager_ops zynqmp_fpga_ops = {
> +       .state = zynqmp_fpga_ops_state,
> +       .write_init = zynqmp_fpga_ops_write_init,
> +       .write = zynqmp_fpga_ops_write,
> +       .write_complete = zynqmp_fpga_ops_write_complete,
> +};
> +
> +static int zynqmp_fpga_probe(struct platform_device *pdev)
> +{
> +       struct device *dev = &pdev->dev;
> +       struct zynqmp_fpga_priv *priv;
> +       struct fpga_manager *mgr;
> +       int err, ret;
> +
> +       priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> +       if (!priv)
> +               return -ENOMEM;
> +
> +       priv->dev = dev;
> +       ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
> +       if (ret < 0)
> +               dev_err(dev, "no usable DMA configuration");

Do you wanna do something about this error if it happens? Return 'ret' maybe?
> +
> +       mgr = fpga_mgr_create(dev, "Xilinx ZynqMP FPGA Manager",
> +                             &zynqmp_fpga_ops, priv);
> +       if (!mgr)
> +               return -ENOMEM;
> +
> +       platform_set_drvdata(pdev, mgr);
> +
> +       err = fpga_mgr_register(mgr);
> +       if (err) {
> +               dev_err(dev, "unable to register FPGA manager");
> +               fpga_mgr_free(mgr);
> +               return err;
> +       }
> +
> +       return 0;
> +}
> +
> +static int zynqmp_fpga_remove(struct platform_device *pdev)
> +{
> +       struct fpga_manager *mgr = platform_get_drvdata(pdev);
> +
> +       fpga_mgr_unregister(mgr);
> +
> +       return 0;
> +}
> +
> +static const struct of_device_id zynqmp_fpga_of_match[] = {
> +       { .compatible = "xlnx,zynqmp-pcap-fpga", },
> +       {},
> +};
> +
> +MODULE_DEVICE_TABLE(of, zynqmp_fpga_of_match);
> +
> +static struct platform_driver zynqmp_fpga_driver = {
> +       .probe = zynqmp_fpga_probe,
> +       .remove = zynqmp_fpga_remove,
> +       .driver = {
> +               .name = "zynqmp_fpga_manager",
> +               .of_match_table = of_match_ptr(zynqmp_fpga_of_match),
> +       },
> +};
> +
> +module_platform_driver(zynqmp_fpga_driver);
> +
> +MODULE_AUTHOR("Nava kishore Manne <navam@xilinx.com>");
> +MODULE_DESCRIPTION("Xilinx ZynqMp FPGA Manager");
> +MODULE_LICENSE("GPL");
> --
> 2.18.0
>

Thanks,

Moritz

[PATCH 3/3] fpga manager: Adding FPGA Manager support for Xilinx zynqmp

[Moritz Fischer]

Hi Nava,

Looks good to me, a couple of nits inline below.

On Fri, Oct 19, 2018 at 1:50 AM Nava kishore Manne
<nava.manne@xilinx.com> wrote:
>
> This patch adds FPGA Manager support for the Xilinx
> ZynqMp chip.

Isn't it ZynqMP ?
>
> Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> ---
> Changes for v1:
>                 -None.
>
> Changes for RFC-V2:
>                 -Updated the Fpga Mgr registrations call's
>                  to 4.18
>
>  drivers/fpga/Kconfig       |   9 +++
>  drivers/fpga/Makefile      |   1 +
>  drivers/fpga/zynqmp-fpga.c | 159 +++++++++++++++++++++++++++++++++++++
>  3 files changed, 169 insertions(+)
>  create mode 100644 drivers/fpga/zynqmp-fpga.c
>
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index 1ebcef4bab5b..26ebbcf3d3a3 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -56,6 +56,15 @@ config FPGA_MGR_ZYNQ_FPGA
>         help
>           FPGA manager driver support for Xilinx Zynq FPGAs.
>
> +config FPGA_MGR_ZYNQMP_FPGA
> +       tristate "Xilinx Zynqmp FPGA"
> +       depends on ARCH_ZYNQMP || COMPILE_TEST
> +       help
> +         FPGA manager driver support for Xilinx ZynqMP FPGAs.
> +         This driver uses processor configuration port(PCAP)
This driver uses *the* processor configuration port.

> +         to configure the programmable logic(PL) through PS
> +         on ZynqMP SoC.
> +
>  config FPGA_MGR_XILINX_SPI
>         tristate "Xilinx Configuration over Slave Serial (SPI)"
>         depends on SPI
> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> index 7a2d73ba7122..3488ebbaee46 100644
> --- a/drivers/fpga/Makefile
> +++ b/drivers/fpga/Makefile
> @@ -16,6 +16,7 @@ obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)    += socfpga-a10.o
>  obj-$(CONFIG_FPGA_MGR_TS73XX)          += ts73xx-fpga.o
>  obj-$(CONFIG_FPGA_MGR_XILINX_SPI)      += xilinx-spi.o
>  obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)       += zynq-fpga.o
> +obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA)     += zynqmp-fpga.o
>  obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
>  obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)    += altera-pr-ip-core-plat.o
>
> diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c
> new file mode 100644
> index 000000000000..2760d7e3872a
> --- /dev/null
> +++ b/drivers/fpga/zynqmp-fpga.c
> @@ -0,0 +1,159 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2018 Xilinx, Inc.
> + */
> +
> +#include <linux/dma-mapping.h>
> +#include <linux/fpga/fpga-mgr.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/string.h>
> +#include <linux/firmware/xlnx-zynqmp.h>
> +
> +/* Constant Definitions */
> +#define IXR_FPGA_DONE_MASK     0X00000008U
> +
> +/**
> + * struct zynqmp_fpga_priv - Private data structure
> + * @dev:       Device data structure
> + * @flags:     flags which is used to identify the bitfile type
> + */
> +struct zynqmp_fpga_priv {
> +       struct device *dev;
> +       u32 flags;
> +};
> +
> +static int zynqmp_fpga_ops_write_init(struct fpga_manager *mgr,
> +                                     struct fpga_image_info *info,
> +                                     const char *buf, size_t size)
> +{
> +       struct zynqmp_fpga_priv *priv;
> +
> +       priv = mgr->priv;
> +       priv->flags = info->flags;
> +
> +       return 0;
> +}
> +
> +static int zynqmp_fpga_ops_write(struct fpga_manager *mgr,
> +                                const char *buf, size_t size)
> +{
> +       struct zynqmp_fpga_priv *priv;
> +       char *kbuf;
> +       dma_addr_t dma_addr;
> +       int ret;
> +       const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();

Reverse xmas-tree please, i.e. long lines first.

> +
> +       if (!eemi_ops || !eemi_ops->fpga_load)
> +               return -ENXIO;
> +
> +       priv = mgr->priv;
> +
> +       kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL);
> +       if (!kbuf)
> +               return -ENOMEM;
> +
> +       memcpy(kbuf, buf, size);
> +
> +       wmb(); /* ensure all writes are done before initiate FW call */
> +
> +       ret = eemi_ops->fpga_load(dma_addr, size, priv->flags);
> +
> +       dma_free_coherent(priv->dev, size, kbuf, dma_addr);
> +
> +       return ret;
> +}
> +
> +static int zynqmp_fpga_ops_write_complete(struct fpga_manager *mgr,
> +                                         struct fpga_image_info *info)
> +{
> +       return 0;
> +}
> +
> +static enum fpga_mgr_states zynqmp_fpga_ops_state(struct fpga_manager *mgr)
> +{
> +       u32 status;
> +       const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();

Same here, split it up if necessary.
> +
> +       if (!eemi_ops || !eemi_ops->fpga_get_status)
> +               return FPGA_MGR_STATE_UNKNOWN;
> +
> +       eemi_ops->fpga_get_status(&status);
> +       if (status & IXR_FPGA_DONE_MASK)
> +               return FPGA_MGR_STATE_OPERATING;
> +
> +       return FPGA_MGR_STATE_UNKNOWN;
> +}
> +
> +static const struct fpga_manager_ops zynqmp_fpga_ops = {
> +       .state = zynqmp_fpga_ops_state,
> +       .write_init = zynqmp_fpga_ops_write_init,
> +       .write = zynqmp_fpga_ops_write,
> +       .write_complete = zynqmp_fpga_ops_write_complete,
> +};
> +
> +static int zynqmp_fpga_probe(struct platform_device *pdev)
> +{
> +       struct device *dev = &pdev->dev;
> +       struct zynqmp_fpga_priv *priv;
> +       struct fpga_manager *mgr;
> +       int err, ret;
> +
> +       priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> +       if (!priv)
> +               return -ENOMEM;
> +
> +       priv->dev = dev;
> +       ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
> +       if (ret < 0)
> +               dev_err(dev, "no usable DMA configuration");

Do you wanna do something about this error if it happens? Return 'ret' maybe?
> +
> +       mgr = fpga_mgr_create(dev, "Xilinx ZynqMP FPGA Manager",
> +                             &zynqmp_fpga_ops, priv);
> +       if (!mgr)
> +               return -ENOMEM;
> +
> +       platform_set_drvdata(pdev, mgr);
> +
> +       err = fpga_mgr_register(mgr);
> +       if (err) {
> +               dev_err(dev, "unable to register FPGA manager");
> +               fpga_mgr_free(mgr);
> +               return err;
> +       }
> +
> +       return 0;
> +}
> +
> +static int zynqmp_fpga_remove(struct platform_device *pdev)
> +{
> +       struct fpga_manager *mgr = platform_get_drvdata(pdev);
> +
> +       fpga_mgr_unregister(mgr);
> +
> +       return 0;
> +}
> +
> +static const struct of_device_id zynqmp_fpga_of_match[] = {
> +       { .compatible = "xlnx,zynqmp-pcap-fpga", },
> +       {},
> +};
> +
> +MODULE_DEVICE_TABLE(of, zynqmp_fpga_of_match);
> +
> +static struct platform_driver zynqmp_fpga_driver = {
> +       .probe = zynqmp_fpga_probe,
> +       .remove = zynqmp_fpga_remove,
> +       .driver = {
> +               .name = "zynqmp_fpga_manager",
> +               .of_match_table = of_match_ptr(zynqmp_fpga_of_match),
> +       },
> +};
> +
> +module_platform_driver(zynqmp_fpga_driver);
> +
> +MODULE_AUTHOR("Nava kishore Manne <navam@xilinx.com>");
> +MODULE_DESCRIPTION("Xilinx ZynqMp FPGA Manager");
> +MODULE_LICENSE("GPL");
> --
> 2.18.0
>

Thanks,

Moritz

Re: [PATCH 3/3] fpga manager: Adding FPGA Manager support for Xilinx zynqmp

[Moritz Fischer]

On Fri, Oct 19, 2018 at 2:33 PM Moritz Fischer
<moritz.fischer.private@gmail.com> wrote:
>
> Hi Nava,
>
> Looks good to me, a couple of nits inline below.
>
> On Fri, Oct 19, 2018 at 1:50 AM Nava kishore Manne
> <nava.manne@xilinx.com> wrote:
> >
> > This patch adds FPGA Manager support for the Xilinx
> > ZynqMp chip.
>
> Isn't it ZynqMP ?
> >
> > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> > ---
> > Changes for v1:
> >                 -None.
> >
> > Changes for RFC-V2:
> >                 -Updated the Fpga Mgr registrations call's
> >                  to 4.18
> >
> >  drivers/fpga/Kconfig       |   9 +++
> >  drivers/fpga/Makefile      |   1 +
> >  drivers/fpga/zynqmp-fpga.c | 159 +++++++++++++++++++++++++++++++++++++
> >  3 files changed, 169 insertions(+)
> >  create mode 100644 drivers/fpga/zynqmp-fpga.c
> >
> > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> > index 1ebcef4bab5b..26ebbcf3d3a3 100644
> > --- a/drivers/fpga/Kconfig
> > +++ b/drivers/fpga/Kconfig
> > @@ -56,6 +56,15 @@ config FPGA_MGR_ZYNQ_FPGA
> >         help
> >           FPGA manager driver support for Xilinx Zynq FPGAs.
> >
> > +config FPGA_MGR_ZYNQMP_FPGA
> > +       tristate "Xilinx Zynqmp FPGA"
> > +       depends on ARCH_ZYNQMP || COMPILE_TEST
> > +       help
> > +         FPGA manager driver support for Xilinx ZynqMP FPGAs.
> > +         This driver uses processor configuration port(PCAP)
> This driver uses *the* processor configuration port.
>
> > +         to configure the programmable logic(PL) through PS
> > +         on ZynqMP SoC.
> > +
> >  config FPGA_MGR_XILINX_SPI
> >         tristate "Xilinx Configuration over Slave Serial (SPI)"
> >         depends on SPI
> > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> > index 7a2d73ba7122..3488ebbaee46 100644
> > --- a/drivers/fpga/Makefile
> > +++ b/drivers/fpga/Makefile
> > @@ -16,6 +16,7 @@ obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)    += socfpga-a10.o
> >  obj-$(CONFIG_FPGA_MGR_TS73XX)          += ts73xx-fpga.o
> >  obj-$(CONFIG_FPGA_MGR_XILINX_SPI)      += xilinx-spi.o
> >  obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)       += zynq-fpga.o
> > +obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA)     += zynqmp-fpga.o
> >  obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
> >  obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)    += altera-pr-ip-core-plat.o
> >
> > diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c
> > new file mode 100644
> > index 000000000000..2760d7e3872a
> > --- /dev/null
> > +++ b/drivers/fpga/zynqmp-fpga.c
> > @@ -0,0 +1,159 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2018 Xilinx, Inc.
> > + */
> > +
> > +#include <linux/dma-mapping.h>
> > +#include <linux/fpga/fpga-mgr.h>
> > +#include <linux/io.h>
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/of_address.h>
> > +#include <linux/string.h>
> > +#include <linux/firmware/xlnx-zynqmp.h>
> > +
> > +/* Constant Definitions */
> > +#define IXR_FPGA_DONE_MASK     0X00000008U
> > +
> > +/**
> > + * struct zynqmp_fpga_priv - Private data structure
> > + * @dev:       Device data structure
> > + * @flags:     flags which is used to identify the bitfile type
> > + */
> > +struct zynqmp_fpga_priv {
> > +       struct device *dev;
> > +       u32 flags;
> > +};
> > +
> > +static int zynqmp_fpga_ops_write_init(struct fpga_manager *mgr,
> > +                                     struct fpga_image_info *info,
> > +                                     const char *buf, size_t size)
> > +{
> > +       struct zynqmp_fpga_priv *priv;
> > +
> > +       priv = mgr->priv;
> > +       priv->flags = info->flags;
> > +
> > +       return 0;
> > +}
> > +
> > +static int zynqmp_fpga_ops_write(struct fpga_manager *mgr,
> > +                                const char *buf, size_t size)
> > +{
> > +       struct zynqmp_fpga_priv *priv;
> > +       char *kbuf;
> > +       dma_addr_t dma_addr;
> > +       int ret;
> > +       const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
>
> Reverse xmas-tree please, i.e. long lines first.
>
> > +
> > +       if (!eemi_ops || !eemi_ops->fpga_load)
> > +               return -ENXIO;
> > +
> > +       priv = mgr->priv;
> > +
> > +       kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL);
> > +       if (!kbuf)
> > +               return -ENOMEM;
> > +
> > +       memcpy(kbuf, buf, size);
> > +
> > +       wmb(); /* ensure all writes are done before initiate FW call */
> > +
> > +       ret = eemi_ops->fpga_load(dma_addr, size, priv->flags);

Don't you have to do anything with the flags? Is it really just a
pass-through of
FPGA manager flags to eemi calls?

Don't you want to make partial bitstreams e.g. use a flags value that
you export in your
firmware header (xlnx-zynqmp.h) and set those based on what flags get passed in,
i.e. explicitely translate FPGA Manager flags to your firmware flags?

Thanks,

Moritz

[PATCH 3/3] fpga manager: Adding FPGA Manager support for Xilinx zynqmp

[Moritz Fischer]

On Fri, Oct 19, 2018 at 2:33 PM Moritz Fischer
<moritz.fischer.private@gmail.com> wrote:
>
> Hi Nava,
>
> Looks good to me, a couple of nits inline below.
>
> On Fri, Oct 19, 2018 at 1:50 AM Nava kishore Manne
> <nava.manne@xilinx.com> wrote:
> >
> > This patch adds FPGA Manager support for the Xilinx
> > ZynqMp chip.
>
> Isn't it ZynqMP ?
> >
> > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> > ---
> > Changes for v1:
> >                 -None.
> >
> > Changes for RFC-V2:
> >                 -Updated the Fpga Mgr registrations call's
> >                  to 4.18
> >
> >  drivers/fpga/Kconfig       |   9 +++
> >  drivers/fpga/Makefile      |   1 +
> >  drivers/fpga/zynqmp-fpga.c | 159 +++++++++++++++++++++++++++++++++++++
> >  3 files changed, 169 insertions(+)
> >  create mode 100644 drivers/fpga/zynqmp-fpga.c
> >
> > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> > index 1ebcef4bab5b..26ebbcf3d3a3 100644
> > --- a/drivers/fpga/Kconfig
> > +++ b/drivers/fpga/Kconfig
> > @@ -56,6 +56,15 @@ config FPGA_MGR_ZYNQ_FPGA
> >         help
> >           FPGA manager driver support for Xilinx Zynq FPGAs.
> >
> > +config FPGA_MGR_ZYNQMP_FPGA
> > +       tristate "Xilinx Zynqmp FPGA"
> > +       depends on ARCH_ZYNQMP || COMPILE_TEST
> > +       help
> > +         FPGA manager driver support for Xilinx ZynqMP FPGAs.
> > +         This driver uses processor configuration port(PCAP)
> This driver uses *the* processor configuration port.
>
> > +         to configure the programmable logic(PL) through PS
> > +         on ZynqMP SoC.
> > +
> >  config FPGA_MGR_XILINX_SPI
> >         tristate "Xilinx Configuration over Slave Serial (SPI)"
> >         depends on SPI
> > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> > index 7a2d73ba7122..3488ebbaee46 100644
> > --- a/drivers/fpga/Makefile
> > +++ b/drivers/fpga/Makefile
> > @@ -16,6 +16,7 @@ obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)    += socfpga-a10.o
> >  obj-$(CONFIG_FPGA_MGR_TS73XX)          += ts73xx-fpga.o
> >  obj-$(CONFIG_FPGA_MGR_XILINX_SPI)      += xilinx-spi.o
> >  obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)       += zynq-fpga.o
> > +obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA)     += zynqmp-fpga.o
> >  obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
> >  obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)    += altera-pr-ip-core-plat.o
> >
> > diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c
> > new file mode 100644
> > index 000000000000..2760d7e3872a
> > --- /dev/null
> > +++ b/drivers/fpga/zynqmp-fpga.c
> > @@ -0,0 +1,159 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2018 Xilinx, Inc.
> > + */
> > +
> > +#include <linux/dma-mapping.h>
> > +#include <linux/fpga/fpga-mgr.h>
> > +#include <linux/io.h>
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/of_address.h>
> > +#include <linux/string.h>
> > +#include <linux/firmware/xlnx-zynqmp.h>
> > +
> > +/* Constant Definitions */
> > +#define IXR_FPGA_DONE_MASK     0X00000008U
> > +
> > +/**
> > + * struct zynqmp_fpga_priv - Private data structure
> > + * @dev:       Device data structure
> > + * @flags:     flags which is used to identify the bitfile type
> > + */
> > +struct zynqmp_fpga_priv {
> > +       struct device *dev;
> > +       u32 flags;
> > +};
> > +
> > +static int zynqmp_fpga_ops_write_init(struct fpga_manager *mgr,
> > +                                     struct fpga_image_info *info,
> > +                                     const char *buf, size_t size)
> > +{
> > +       struct zynqmp_fpga_priv *priv;
> > +
> > +       priv = mgr->priv;
> > +       priv->flags = info->flags;
> > +
> > +       return 0;
> > +}
> > +
> > +static int zynqmp_fpga_ops_write(struct fpga_manager *mgr,
> > +                                const char *buf, size_t size)
> > +{
> > +       struct zynqmp_fpga_priv *priv;
> > +       char *kbuf;
> > +       dma_addr_t dma_addr;
> > +       int ret;
> > +       const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
>
> Reverse xmas-tree please, i.e. long lines first.
>
> > +
> > +       if (!eemi_ops || !eemi_ops->fpga_load)
> > +               return -ENXIO;
> > +
> > +       priv = mgr->priv;
> > +
> > +       kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL);
> > +       if (!kbuf)
> > +               return -ENOMEM;
> > +
> > +       memcpy(kbuf, buf, size);
> > +
> > +       wmb(); /* ensure all writes are done before initiate FW call */
> > +
> > +       ret = eemi_ops->fpga_load(dma_addr, size, priv->flags);

Don't you have to do anything with the flags? Is it really just a
pass-through of
FPGA manager flags to eemi calls?

Don't you want to make partial bitstreams e.g. use a flags value that
you export in your
firmware header (xlnx-zynqmp.h) and set those based on what flags get passed in,
i.e. explicitely translate FPGA Manager flags to your firmware flags?

Thanks,

Moritz

[PATCH 0/3] Add Bitstream configuration support for ZynqMP

[Nava kishore Manne]

This series of patches are created On top of the
below repo.
//git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git
BRANCH: next/drivers.  

Nava kishore Manne (3):
  firmware: xilinx: Add fpga API's
  dt-bindings: fpga: Add bindings for ZynqMP fpga driver
  fpga manager: Adding FPGA Manager support for Xilinx zynqmp

 .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt   |  17 ++
 drivers/firmware/xilinx/zynqmp.c              |  46 +++++
 drivers/fpga/Kconfig                          |   9 +
 drivers/fpga/Makefile                         |   1 +
 drivers/fpga/zynqmp-fpga.c                    | 159 ++++++++++++++++++
 include/linux/firmware/xlnx-zynqmp.h          |   4 +
 6 files changed, 236 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
 create mode 100644 drivers/fpga/zynqmp-fpga.c

-- 
2.18.0

[PATCH 0/3] Add Bitstream configuration support for ZynqMP

[Nava kishore Manne]

This series of patches are created On top of the
below repo.
//git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git
BRANCH: next/drivers.  

Nava kishore Manne (3):
  firmware: xilinx: Add fpga API's
  dt-bindings: fpga: Add bindings for ZynqMP fpga driver
  fpga manager: Adding FPGA Manager support for Xilinx zynqmp

 .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt   |  17 ++
 drivers/firmware/xilinx/zynqmp.c              |  46 +++++
 drivers/fpga/Kconfig                          |   9 +
 drivers/fpga/Makefile                         |   1 +
 drivers/fpga/zynqmp-fpga.c                    | 159 ++++++++++++++++++
 include/linux/firmware/xlnx-zynqmp.h          |   4 +
 6 files changed, 236 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
 create mode 100644 drivers/fpga/zynqmp-fpga.c

-- 
2.18.0

[PATCH 0/3] Add Bitstream configuration support for ZynqMP

[Nava kishore Manne]

This series of patches are created On top of the
below repo.
//git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git
BRANCH: next/drivers.  

Nava kishore Manne (3):
  firmware: xilinx: Add fpga API's
  dt-bindings: fpga: Add bindings for ZynqMP fpga driver
  fpga manager: Adding FPGA Manager support for Xilinx zynqmp

 .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt   |  17 ++
 drivers/firmware/xilinx/zynqmp.c              |  46 +++++
 drivers/fpga/Kconfig                          |   9 +
 drivers/fpga/Makefile                         |   1 +
 drivers/fpga/zynqmp-fpga.c                    | 159 ++++++++++++++++++
 include/linux/firmware/xlnx-zynqmp.h          |   4 +
 6 files changed, 236 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
 create mode 100644 drivers/fpga/zynqmp-fpga.c

-- 
2.18.0

[PATCH 1/3] firmware: xilinx: Add fpga API's

[Nava kishore Manne]

This Patch Adds fpga API's to support the Bitstream loading
by using firmware interface.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
---
Changes for v1:
		-None.

Changes for RFC-V2:
                -New Patch.

 drivers/firmware/xilinx/zynqmp.c     | 46 ++++++++++++++++++++++++++++
 include/linux/firmware/xlnx-zynqmp.h |  4 +++
 2 files changed, 50 insertions(+)

diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 84b3fd2eca8b..38a1ab1be03b 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -428,6 +428,50 @@ static int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)
 	return ret;
 }
 
+/**
+ * zynqmp_pm_fpga_load - Perform the fpga load
+ * @address:	Address to write to
+ * @size:	pl bitstream size
+ * @flags:
+ *	BIT(0) - Bit-stream type.
+ *		 0 - Full Bit-stream.
+ *		 1 - Partial Bit-stream.
+ *
+ * This function provides access to pmufw. To transfer
+ * the required bitstream into PL.
+ *
+ * Return: Returns status, either success or error+reason
+ */
+static int zynqmp_pm_fpga_load(const u64 address, const u32 size,
+			       const u32 flags)
+{
+	return zynqmp_pm_invoke_fn(PM_FPGA_LOAD, lower_32_bits(address),
+				   upper_32_bits(address), size, flags, NULL);
+}
+
+/**
+ * zynqmp_pm_fpga_get_status - Read value from PCAP status register
+ * @value: Value to read
+ *
+ * This function provides access to the xilfpga library to get
+ * the PCAP status
+ *
+ * Return: Returns status, either success or error+reason
+ */
+static int zynqmp_pm_fpga_get_status(u32 *value)
+{
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+	int ret;
+
+	if (!value)
+		return -EINVAL;
+
+	ret = zynqmp_pm_invoke_fn(PM_FPGA_GET_STATUS, 0, 0, 0, 0, ret_payload);
+	*value = ret_payload[1];
+
+	return ret;
+}
+
 static const struct zynqmp_eemi_ops eemi_ops = {
 	.get_api_version = zynqmp_pm_get_api_version,
 	.query_data = zynqmp_pm_query_data,
@@ -440,6 +484,8 @@ static const struct zynqmp_eemi_ops eemi_ops = {
 	.clock_getrate = zynqmp_pm_clock_getrate,
 	.clock_setparent = zynqmp_pm_clock_setparent,
 	.clock_getparent = zynqmp_pm_clock_getparent,
+	.fpga_load = zynqmp_pm_fpga_load,
+	.fpga_get_status = zynqmp_pm_fpga_get_status,
 };
 
 /**
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index 015e130431e6..b24400ee630a 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -34,6 +34,8 @@
 
 enum pm_api_id {
 	PM_GET_API_VERSION = 1,
+	PM_FPGA_LOAD = 22,
+	PM_FPGA_GET_STATUS,
 	PM_QUERY_DATA = 35,
 	PM_CLOCK_ENABLE,
 	PM_CLOCK_DISABLE,
@@ -89,6 +91,8 @@ struct zynqmp_pm_query_data {
 
 struct zynqmp_eemi_ops {
 	int (*get_api_version)(u32 *version);
+	int (*fpga_load)(const u64 address, const u32 size, const u32 flags);
+	int (*fpga_get_status)(u32 *value);
 	int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out);
 	int (*clock_enable)(u32 clock_id);
 	int (*clock_disable)(u32 clock_id);
-- 
2.18.0

[PATCH 1/3] firmware: xilinx: Add fpga API's

[Nava kishore Manne]

This Patch Adds fpga API's to support the Bitstream loading
by using firmware interface.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
---
Changes for v1:
		-None.

Changes for RFC-V2:
                -New Patch.

 drivers/firmware/xilinx/zynqmp.c     | 46 ++++++++++++++++++++++++++++
 include/linux/firmware/xlnx-zynqmp.h |  4 +++
 2 files changed, 50 insertions(+)

diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 84b3fd2eca8b..38a1ab1be03b 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -428,6 +428,50 @@ static int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)
 	return ret;
 }
 
+/**
+ * zynqmp_pm_fpga_load - Perform the fpga load
+ * @address:	Address to write to
+ * @size:	pl bitstream size
+ * @flags:
+ *	BIT(0) - Bit-stream type.
+ *		 0 - Full Bit-stream.
+ *		 1 - Partial Bit-stream.
+ *
+ * This function provides access to pmufw. To transfer
+ * the required bitstream into PL.
+ *
+ * Return: Returns status, either success or error+reason
+ */
+static int zynqmp_pm_fpga_load(const u64 address, const u32 size,
+			       const u32 flags)
+{
+	return zynqmp_pm_invoke_fn(PM_FPGA_LOAD, lower_32_bits(address),
+				   upper_32_bits(address), size, flags, NULL);
+}
+
+/**
+ * zynqmp_pm_fpga_get_status - Read value from PCAP status register
+ * @value: Value to read
+ *
+ * This function provides access to the xilfpga library to get
+ * the PCAP status
+ *
+ * Return: Returns status, either success or error+reason
+ */
+static int zynqmp_pm_fpga_get_status(u32 *value)
+{
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+	int ret;
+
+	if (!value)
+		return -EINVAL;
+
+	ret = zynqmp_pm_invoke_fn(PM_FPGA_GET_STATUS, 0, 0, 0, 0, ret_payload);
+	*value = ret_payload[1];
+
+	return ret;
+}
+
 static const struct zynqmp_eemi_ops eemi_ops = {
 	.get_api_version = zynqmp_pm_get_api_version,
 	.query_data = zynqmp_pm_query_data,
@@ -440,6 +484,8 @@ static const struct zynqmp_eemi_ops eemi_ops = {
 	.clock_getrate = zynqmp_pm_clock_getrate,
 	.clock_setparent = zynqmp_pm_clock_setparent,
 	.clock_getparent = zynqmp_pm_clock_getparent,
+	.fpga_load = zynqmp_pm_fpga_load,
+	.fpga_get_status = zynqmp_pm_fpga_get_status,
 };
 
 /**
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index 015e130431e6..b24400ee630a 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -34,6 +34,8 @@
 
 enum pm_api_id {
 	PM_GET_API_VERSION = 1,
+	PM_FPGA_LOAD = 22,
+	PM_FPGA_GET_STATUS,
 	PM_QUERY_DATA = 35,
 	PM_CLOCK_ENABLE,
 	PM_CLOCK_DISABLE,
@@ -89,6 +91,8 @@ struct zynqmp_pm_query_data {
 
 struct zynqmp_eemi_ops {
 	int (*get_api_version)(u32 *version);
+	int (*fpga_load)(const u64 address, const u32 size, const u32 flags);
+	int (*fpga_get_status)(u32 *value);
 	int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out);
 	int (*clock_enable)(u32 clock_id);
 	int (*clock_disable)(u32 clock_id);
-- 
2.18.0

[PATCH 1/3] firmware: xilinx: Add fpga API's

[Nava kishore Manne]

This Patch Adds fpga API's to support the Bitstream loading
by using firmware interface.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
---
Changes for v1:
		-None.

Changes for RFC-V2:
                -New Patch.

 drivers/firmware/xilinx/zynqmp.c     | 46 ++++++++++++++++++++++++++++
 include/linux/firmware/xlnx-zynqmp.h |  4 +++
 2 files changed, 50 insertions(+)

diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 84b3fd2eca8b..38a1ab1be03b 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -428,6 +428,50 @@ static int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)
 	return ret;
 }
 
+/**
+ * zynqmp_pm_fpga_load - Perform the fpga load
+ * @address:	Address to write to
+ * @size:	pl bitstream size
+ * @flags:
+ *	BIT(0) - Bit-stream type.
+ *		 0 - Full Bit-stream.
+ *		 1 - Partial Bit-stream.
+ *
+ * This function provides access to pmufw. To transfer
+ * the required bitstream into PL.
+ *
+ * Return: Returns status, either success or error+reason
+ */
+static int zynqmp_pm_fpga_load(const u64 address, const u32 size,
+			       const u32 flags)
+{
+	return zynqmp_pm_invoke_fn(PM_FPGA_LOAD, lower_32_bits(address),
+				   upper_32_bits(address), size, flags, NULL);
+}
+
+/**
+ * zynqmp_pm_fpga_get_status - Read value from PCAP status register
+ * @value: Value to read
+ *
+ * This function provides access to the xilfpga library to get
+ * the PCAP status
+ *
+ * Return: Returns status, either success or error+reason
+ */
+static int zynqmp_pm_fpga_get_status(u32 *value)
+{
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+	int ret;
+
+	if (!value)
+		return -EINVAL;
+
+	ret = zynqmp_pm_invoke_fn(PM_FPGA_GET_STATUS, 0, 0, 0, 0, ret_payload);
+	*value = ret_payload[1];
+
+	return ret;
+}
+
 static const struct zynqmp_eemi_ops eemi_ops = {
 	.get_api_version = zynqmp_pm_get_api_version,
 	.query_data = zynqmp_pm_query_data,
@@ -440,6 +484,8 @@ static const struct zynqmp_eemi_ops eemi_ops = {
 	.clock_getrate = zynqmp_pm_clock_getrate,
 	.clock_setparent = zynqmp_pm_clock_setparent,
 	.clock_getparent = zynqmp_pm_clock_getparent,
+	.fpga_load = zynqmp_pm_fpga_load,
+	.fpga_get_status = zynqmp_pm_fpga_get_status,
 };
 
 /**
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index 015e130431e6..b24400ee630a 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -34,6 +34,8 @@
 
 enum pm_api_id {
 	PM_GET_API_VERSION = 1,
+	PM_FPGA_LOAD = 22,
+	PM_FPGA_GET_STATUS,
 	PM_QUERY_DATA = 35,
 	PM_CLOCK_ENABLE,
 	PM_CLOCK_DISABLE,
@@ -89,6 +91,8 @@ struct zynqmp_pm_query_data {
 
 struct zynqmp_eemi_ops {
 	int (*get_api_version)(u32 *version);
+	int (*fpga_load)(const u64 address, const u32 size, const u32 flags);
+	int (*fpga_get_status)(u32 *value);
 	int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out);
 	int (*clock_enable)(u32 clock_id);
 	int (*clock_disable)(u32 clock_id);
-- 
2.18.0

[PATCH 2/3] dt-bindings: fpga: Add bindings for ZynqMP fpga driver

[Nava kishore Manne]

Add documentation to describe Xilinx ZynqMP fpga driver
bindings.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
---
Changes for v1:
                Created a Seperate(New) DT binding file as
                suggested by Rob.

Changes for RFC-V2:
                -Moved pcap node as a child to firwmare
                 node as suggested by Rob.

 .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt     | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt

diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
new file mode 100644
index 000000000000..248ff0ee60a8
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
@@ -0,0 +1,17 @@
+--------------------------------------------------------------------------
+Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC controlled
+using ZynqMP SoC firmware interface
+--------------------------------------------------------------------------
+For Bitstream configuration on ZynqMp Soc uses processor configuration
+port(PCAP) to configure the programmable logic(PL) through PS by using
+FW interface.
+
+Required properties:
+- compatible: should contain "xlnx,zynqmp-pcap-fpga"
+
+-------
+Example
+-------
+	zynqmp_pcap: pcap {
+		compatible = "xlnx,zynqmp-pcap-fpga";
+	};
-- 
2.18.0

[PATCH 2/3] dt-bindings: fpga: Add bindings for ZynqMP fpga driver

[Nava kishore Manne]

Add documentation to describe Xilinx ZynqMP fpga driver
bindings.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
---
Changes for v1:
                Created a Seperate(New) DT binding file as
                suggested by Rob.

Changes for RFC-V2:
                -Moved pcap node as a child to firwmare
                 node as suggested by Rob.

 .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt     | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt

diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
new file mode 100644
index 000000000000..248ff0ee60a8
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
@@ -0,0 +1,17 @@
+--------------------------------------------------------------------------
+Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC controlled
+using ZynqMP SoC firmware interface
+--------------------------------------------------------------------------
+For Bitstream configuration on ZynqMp Soc uses processor configuration
+port(PCAP) to configure the programmable logic(PL) through PS by using
+FW interface.
+
+Required properties:
+- compatible: should contain "xlnx,zynqmp-pcap-fpga"
+
+-------
+Example
+-------
+	zynqmp_pcap: pcap {
+		compatible = "xlnx,zynqmp-pcap-fpga";
+	};
-- 
2.18.0

[PATCH 2/3] dt-bindings: fpga: Add bindings for ZynqMP fpga driver

[Nava kishore Manne]

Add documentation to describe Xilinx ZynqMP fpga driver
bindings.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
---
Changes for v1:
                Created a Seperate(New) DT binding file as
                suggested by Rob.

Changes for RFC-V2:
                -Moved pcap node as a child to firwmare
                 node as suggested by Rob.

 .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt     | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt

diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
new file mode 100644
index 000000000000..248ff0ee60a8
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
@@ -0,0 +1,17 @@
+--------------------------------------------------------------------------
+Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC controlled
+using ZynqMP SoC firmware interface
+--------------------------------------------------------------------------
+For Bitstream configuration on ZynqMp Soc uses processor configuration
+port(PCAP) to configure the programmable logic(PL) through PS by using
+FW interface.
+
+Required properties:
+- compatible: should contain "xlnx,zynqmp-pcap-fpga"
+
+-------
+Example
+-------
+	zynqmp_pcap: pcap {
+		compatible = "xlnx,zynqmp-pcap-fpga";
+	};
-- 
2.18.0

[PATCH 3/3] fpga manager: Adding FPGA Manager support for Xilinx zynqmp

[Nava kishore Manne]

This patch adds FPGA Manager support for the Xilinx
ZynqMp chip.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
---
Changes for v1:
		-None.

Changes for RFC-V2:
                -Updated the Fpga Mgr registrations call's
                 to 4.18

 drivers/fpga/Kconfig       |   9 +++
 drivers/fpga/Makefile      |   1 +
 drivers/fpga/zynqmp-fpga.c | 159 +++++++++++++++++++++++++++++++++++++
 3 files changed, 169 insertions(+)
 create mode 100644 drivers/fpga/zynqmp-fpga.c

diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 1ebcef4bab5b..26ebbcf3d3a3 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -56,6 +56,15 @@ config FPGA_MGR_ZYNQ_FPGA
 	help
 	  FPGA manager driver support for Xilinx Zynq FPGAs.
 
+config FPGA_MGR_ZYNQMP_FPGA
+	tristate "Xilinx Zynqmp FPGA"
+	depends on ARCH_ZYNQMP || COMPILE_TEST
+	help
+	  FPGA manager driver support for Xilinx ZynqMP FPGAs.
+	  This driver uses processor configuration port(PCAP)
+	  to configure the programmable logic(PL) through PS
+	  on ZynqMP SoC.
+
 config FPGA_MGR_XILINX_SPI
 	tristate "Xilinx Configuration over Slave Serial (SPI)"
 	depends on SPI
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 7a2d73ba7122..3488ebbaee46 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)	+= socfpga-a10.o
 obj-$(CONFIG_FPGA_MGR_TS73XX)		+= ts73xx-fpga.o
 obj-$(CONFIG_FPGA_MGR_XILINX_SPI)	+= xilinx-spi.o
 obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)	+= zynq-fpga.o
+obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA)	+= zynqmp-fpga.o
 obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
 obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)    += altera-pr-ip-core-plat.o
 
diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c
new file mode 100644
index 000000000000..2760d7e3872a
--- /dev/null
+++ b/drivers/fpga/zynqmp-fpga.c
@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/fpga/fpga-mgr.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/string.h>
+#include <linux/firmware/xlnx-zynqmp.h>
+
+/* Constant Definitions */
+#define IXR_FPGA_DONE_MASK	0X00000008U
+
+/**
+ * struct zynqmp_fpga_priv - Private data structure
+ * @dev:	Device data structure
+ * @flags:	flags which is used to identify the bitfile type
+ */
+struct zynqmp_fpga_priv {
+	struct device *dev;
+	u32 flags;
+};
+
+static int zynqmp_fpga_ops_write_init(struct fpga_manager *mgr,
+				      struct fpga_image_info *info,
+				      const char *buf, size_t size)
+{
+	struct zynqmp_fpga_priv *priv;
+
+	priv = mgr->priv;
+	priv->flags = info->flags;
+
+	return 0;
+}
+
+static int zynqmp_fpga_ops_write(struct fpga_manager *mgr,
+				 const char *buf, size_t size)
+{
+	struct zynqmp_fpga_priv *priv;
+	char *kbuf;
+	dma_addr_t dma_addr;
+	int ret;
+	const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
+
+	if (!eemi_ops || !eemi_ops->fpga_load)
+		return -ENXIO;
+
+	priv = mgr->priv;
+
+	kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL);
+	if (!kbuf)
+		return -ENOMEM;
+
+	memcpy(kbuf, buf, size);
+
+	wmb(); /* ensure all writes are done before initiate FW call */
+
+	ret = eemi_ops->fpga_load(dma_addr, size, priv->flags);
+
+	dma_free_coherent(priv->dev, size, kbuf, dma_addr);
+
+	return ret;
+}
+
+static int zynqmp_fpga_ops_write_complete(struct fpga_manager *mgr,
+					  struct fpga_image_info *info)
+{
+	return 0;
+}
+
+static enum fpga_mgr_states zynqmp_fpga_ops_state(struct fpga_manager *mgr)
+{
+	u32 status;
+	const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
+
+	if (!eemi_ops || !eemi_ops->fpga_get_status)
+		return FPGA_MGR_STATE_UNKNOWN;
+
+	eemi_ops->fpga_get_status(&status);
+	if (status & IXR_FPGA_DONE_MASK)
+		return FPGA_MGR_STATE_OPERATING;
+
+	return FPGA_MGR_STATE_UNKNOWN;
+}
+
+static const struct fpga_manager_ops zynqmp_fpga_ops = {
+	.state = zynqmp_fpga_ops_state,
+	.write_init = zynqmp_fpga_ops_write_init,
+	.write = zynqmp_fpga_ops_write,
+	.write_complete = zynqmp_fpga_ops_write_complete,
+};
+
+static int zynqmp_fpga_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct zynqmp_fpga_priv *priv;
+	struct fpga_manager *mgr;
+	int err, ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->dev = dev;
+	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
+	if (ret < 0)
+		dev_err(dev, "no usable DMA configuration");
+
+	mgr = fpga_mgr_create(dev, "Xilinx ZynqMP FPGA Manager",
+			      &zynqmp_fpga_ops, priv);
+	if (!mgr)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, mgr);
+
+	err = fpga_mgr_register(mgr);
+	if (err) {
+		dev_err(dev, "unable to register FPGA manager");
+		fpga_mgr_free(mgr);
+		return err;
+	}
+
+	return 0;
+}
+
+static int zynqmp_fpga_remove(struct platform_device *pdev)
+{
+	struct fpga_manager *mgr = platform_get_drvdata(pdev);
+
+	fpga_mgr_unregister(mgr);
+
+	return 0;
+}
+
+static const struct of_device_id zynqmp_fpga_of_match[] = {
+	{ .compatible = "xlnx,zynqmp-pcap-fpga", },
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, zynqmp_fpga_of_match);
+
+static struct platform_driver zynqmp_fpga_driver = {
+	.probe = zynqmp_fpga_probe,
+	.remove = zynqmp_fpga_remove,
+	.driver = {
+		.name = "zynqmp_fpga_manager",
+		.of_match_table = of_match_ptr(zynqmp_fpga_of_match),
+	},
+};
+
+module_platform_driver(zynqmp_fpga_driver);
+
+MODULE_AUTHOR("Nava kishore Manne <navam@xilinx.com>");
+MODULE_DESCRIPTION("Xilinx ZynqMp FPGA Manager");
+MODULE_LICENSE("GPL");
-- 
2.18.0

[PATCH 3/3] fpga manager: Adding FPGA Manager support for Xilinx zynqmp

[Nava kishore Manne]

This patch adds FPGA Manager support for the Xilinx
ZynqMp chip.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
---
Changes for v1:
		-None.

Changes for RFC-V2:
                -Updated the Fpga Mgr registrations call's
                 to 4.18

 drivers/fpga/Kconfig       |   9 +++
 drivers/fpga/Makefile      |   1 +
 drivers/fpga/zynqmp-fpga.c | 159 +++++++++++++++++++++++++++++++++++++
 3 files changed, 169 insertions(+)
 create mode 100644 drivers/fpga/zynqmp-fpga.c

diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 1ebcef4bab5b..26ebbcf3d3a3 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -56,6 +56,15 @@ config FPGA_MGR_ZYNQ_FPGA
 	help
 	  FPGA manager driver support for Xilinx Zynq FPGAs.
 
+config FPGA_MGR_ZYNQMP_FPGA
+	tristate "Xilinx Zynqmp FPGA"
+	depends on ARCH_ZYNQMP || COMPILE_TEST
+	help
+	  FPGA manager driver support for Xilinx ZynqMP FPGAs.
+	  This driver uses processor configuration port(PCAP)
+	  to configure the programmable logic(PL) through PS
+	  on ZynqMP SoC.
+
 config FPGA_MGR_XILINX_SPI
 	tristate "Xilinx Configuration over Slave Serial (SPI)"
 	depends on SPI
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 7a2d73ba7122..3488ebbaee46 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)	+= socfpga-a10.o
 obj-$(CONFIG_FPGA_MGR_TS73XX)		+= ts73xx-fpga.o
 obj-$(CONFIG_FPGA_MGR_XILINX_SPI)	+= xilinx-spi.o
 obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)	+= zynq-fpga.o
+obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA)	+= zynqmp-fpga.o
 obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
 obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)    += altera-pr-ip-core-plat.o
 
diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c
new file mode 100644
index 000000000000..2760d7e3872a
--- /dev/null
+++ b/drivers/fpga/zynqmp-fpga.c
@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/fpga/fpga-mgr.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/string.h>
+#include <linux/firmware/xlnx-zynqmp.h>
+
+/* Constant Definitions */
+#define IXR_FPGA_DONE_MASK	0X00000008U
+
+/**
+ * struct zynqmp_fpga_priv - Private data structure
+ * @dev:	Device data structure
+ * @flags:	flags which is used to identify the bitfile type
+ */
+struct zynqmp_fpga_priv {
+	struct device *dev;
+	u32 flags;
+};
+
+static int zynqmp_fpga_ops_write_init(struct fpga_manager *mgr,
+				      struct fpga_image_info *info,
+				      const char *buf, size_t size)
+{
+	struct zynqmp_fpga_priv *priv;
+
+	priv = mgr->priv;
+	priv->flags = info->flags;
+
+	return 0;
+}
+
+static int zynqmp_fpga_ops_write(struct fpga_manager *mgr,
+				 const char *buf, size_t size)
+{
+	struct zynqmp_fpga_priv *priv;
+	char *kbuf;
+	dma_addr_t dma_addr;
+	int ret;
+	const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
+
+	if (!eemi_ops || !eemi_ops->fpga_load)
+		return -ENXIO;
+
+	priv = mgr->priv;
+
+	kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL);
+	if (!kbuf)
+		return -ENOMEM;
+
+	memcpy(kbuf, buf, size);
+
+	wmb(); /* ensure all writes are done before initiate FW call */
+
+	ret = eemi_ops->fpga_load(dma_addr, size, priv->flags);
+
+	dma_free_coherent(priv->dev, size, kbuf, dma_addr);
+
+	return ret;
+}
+
+static int zynqmp_fpga_ops_write_complete(struct fpga_manager *mgr,
+					  struct fpga_image_info *info)
+{
+	return 0;
+}
+
+static enum fpga_mgr_states zynqmp_fpga_ops_state(struct fpga_manager *mgr)
+{
+	u32 status;
+	const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
+
+	if (!eemi_ops || !eemi_ops->fpga_get_status)
+		return FPGA_MGR_STATE_UNKNOWN;
+
+	eemi_ops->fpga_get_status(&status);
+	if (status & IXR_FPGA_DONE_MASK)
+		return FPGA_MGR_STATE_OPERATING;
+
+	return FPGA_MGR_STATE_UNKNOWN;
+}
+
+static const struct fpga_manager_ops zynqmp_fpga_ops = {
+	.state = zynqmp_fpga_ops_state,
+	.write_init = zynqmp_fpga_ops_write_init,
+	.write = zynqmp_fpga_ops_write,
+	.write_complete = zynqmp_fpga_ops_write_complete,
+};
+
+static int zynqmp_fpga_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct zynqmp_fpga_priv *priv;
+	struct fpga_manager *mgr;
+	int err, ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->dev = dev;
+	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
+	if (ret < 0)
+		dev_err(dev, "no usable DMA configuration");
+
+	mgr = fpga_mgr_create(dev, "Xilinx ZynqMP FPGA Manager",
+			      &zynqmp_fpga_ops, priv);
+	if (!mgr)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, mgr);
+
+	err = fpga_mgr_register(mgr);
+	if (err) {
+		dev_err(dev, "unable to register FPGA manager");
+		fpga_mgr_free(mgr);
+		return err;
+	}
+
+	return 0;
+}
+
+static int zynqmp_fpga_remove(struct platform_device *pdev)
+{
+	struct fpga_manager *mgr = platform_get_drvdata(pdev);
+
+	fpga_mgr_unregister(mgr);
+
+	return 0;
+}
+
+static const struct of_device_id zynqmp_fpga_of_match[] = {
+	{ .compatible = "xlnx,zynqmp-pcap-fpga", },
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, zynqmp_fpga_of_match);
+
+static struct platform_driver zynqmp_fpga_driver = {
+	.probe = zynqmp_fpga_probe,
+	.remove = zynqmp_fpga_remove,
+	.driver = {
+		.name = "zynqmp_fpga_manager",
+		.of_match_table = of_match_ptr(zynqmp_fpga_of_match),
+	},
+};
+
+module_platform_driver(zynqmp_fpga_driver);
+
+MODULE_AUTHOR("Nava kishore Manne <navam@xilinx.com>");
+MODULE_DESCRIPTION("Xilinx ZynqMp FPGA Manager");
+MODULE_LICENSE("GPL");
-- 
2.18.0

[PATCH 3/3] fpga manager: Adding FPGA Manager support for Xilinx zynqmp

[Nava kishore Manne]

This patch adds FPGA Manager support for the Xilinx
ZynqMp chip.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
---
Changes for v1:
		-None.

Changes for RFC-V2:
                -Updated the Fpga Mgr registrations call's
                 to 4.18

 drivers/fpga/Kconfig       |   9 +++
 drivers/fpga/Makefile      |   1 +
 drivers/fpga/zynqmp-fpga.c | 159 +++++++++++++++++++++++++++++++++++++
 3 files changed, 169 insertions(+)
 create mode 100644 drivers/fpga/zynqmp-fpga.c

diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 1ebcef4bab5b..26ebbcf3d3a3 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -56,6 +56,15 @@ config FPGA_MGR_ZYNQ_FPGA
 	help
 	  FPGA manager driver support for Xilinx Zynq FPGAs.
 
+config FPGA_MGR_ZYNQMP_FPGA
+	tristate "Xilinx Zynqmp FPGA"
+	depends on ARCH_ZYNQMP || COMPILE_TEST
+	help
+	  FPGA manager driver support for Xilinx ZynqMP FPGAs.
+	  This driver uses processor configuration port(PCAP)
+	  to configure the programmable logic(PL) through PS
+	  on ZynqMP SoC.
+
 config FPGA_MGR_XILINX_SPI
 	tristate "Xilinx Configuration over Slave Serial (SPI)"
 	depends on SPI
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 7a2d73ba7122..3488ebbaee46 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)	+= socfpga-a10.o
 obj-$(CONFIG_FPGA_MGR_TS73XX)		+= ts73xx-fpga.o
 obj-$(CONFIG_FPGA_MGR_XILINX_SPI)	+= xilinx-spi.o
 obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)	+= zynq-fpga.o
+obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA)	+= zynqmp-fpga.o
 obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
 obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)    += altera-pr-ip-core-plat.o
 
diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c
new file mode 100644
index 000000000000..2760d7e3872a
--- /dev/null
+++ b/drivers/fpga/zynqmp-fpga.c
@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/fpga/fpga-mgr.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/string.h>
+#include <linux/firmware/xlnx-zynqmp.h>
+
+/* Constant Definitions */
+#define IXR_FPGA_DONE_MASK	0X00000008U
+
+/**
+ * struct zynqmp_fpga_priv - Private data structure
+ * @dev:	Device data structure
+ * @flags:	flags which is used to identify the bitfile type
+ */
+struct zynqmp_fpga_priv {
+	struct device *dev;
+	u32 flags;
+};
+
+static int zynqmp_fpga_ops_write_init(struct fpga_manager *mgr,
+				      struct fpga_image_info *info,
+				      const char *buf, size_t size)
+{
+	struct zynqmp_fpga_priv *priv;
+
+	priv = mgr->priv;
+	priv->flags = info->flags;
+
+	return 0;
+}
+
+static int zynqmp_fpga_ops_write(struct fpga_manager *mgr,
+				 const char *buf, size_t size)
+{
+	struct zynqmp_fpga_priv *priv;
+	char *kbuf;
+	dma_addr_t dma_addr;
+	int ret;
+	const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
+
+	if (!eemi_ops || !eemi_ops->fpga_load)
+		return -ENXIO;
+
+	priv = mgr->priv;
+
+	kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL);
+	if (!kbuf)
+		return -ENOMEM;
+
+	memcpy(kbuf, buf, size);
+
+	wmb(); /* ensure all writes are done before initiate FW call */
+
+	ret = eemi_ops->fpga_load(dma_addr, size, priv->flags);
+
+	dma_free_coherent(priv->dev, size, kbuf, dma_addr);
+
+	return ret;
+}
+
+static int zynqmp_fpga_ops_write_complete(struct fpga_manager *mgr,
+					  struct fpga_image_info *info)
+{
+	return 0;
+}
+
+static enum fpga_mgr_states zynqmp_fpga_ops_state(struct fpga_manager *mgr)
+{
+	u32 status;
+	const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
+
+	if (!eemi_ops || !eemi_ops->fpga_get_status)
+		return FPGA_MGR_STATE_UNKNOWN;
+
+	eemi_ops->fpga_get_status(&status);
+	if (status & IXR_FPGA_DONE_MASK)
+		return FPGA_MGR_STATE_OPERATING;
+
+	return FPGA_MGR_STATE_UNKNOWN;
+}
+
+static const struct fpga_manager_ops zynqmp_fpga_ops = {
+	.state = zynqmp_fpga_ops_state,
+	.write_init = zynqmp_fpga_ops_write_init,
+	.write = zynqmp_fpga_ops_write,
+	.write_complete = zynqmp_fpga_ops_write_complete,
+};
+
+static int zynqmp_fpga_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct zynqmp_fpga_priv *priv;
+	struct fpga_manager *mgr;
+	int err, ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->dev = dev;
+	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
+	if (ret < 0)
+		dev_err(dev, "no usable DMA configuration");
+
+	mgr = fpga_mgr_create(dev, "Xilinx ZynqMP FPGA Manager",
+			      &zynqmp_fpga_ops, priv);
+	if (!mgr)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, mgr);
+
+	err = fpga_mgr_register(mgr);
+	if (err) {
+		dev_err(dev, "unable to register FPGA manager");
+		fpga_mgr_free(mgr);
+		return err;
+	}
+
+	return 0;
+}
+
+static int zynqmp_fpga_remove(struct platform_device *pdev)
+{
+	struct fpga_manager *mgr = platform_get_drvdata(pdev);
+
+	fpga_mgr_unregister(mgr);
+
+	return 0;
+}
+
+static const struct of_device_id zynqmp_fpga_of_match[] = {
+	{ .compatible = "xlnx,zynqmp-pcap-fpga", },
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, zynqmp_fpga_of_match);
+
+static struct platform_driver zynqmp_fpga_driver = {
+	.probe = zynqmp_fpga_probe,
+	.remove = zynqmp_fpga_remove,
+	.driver = {
+		.name = "zynqmp_fpga_manager",
+		.of_match_table = of_match_ptr(zynqmp_fpga_of_match),
+	},
+};
+
+module_platform_driver(zynqmp_fpga_driver);
+
+MODULE_AUTHOR("Nava kishore Manne <navam@xilinx.com>");
+MODULE_DESCRIPTION("Xilinx ZynqMp FPGA Manager");
+MODULE_LICENSE("GPL");
-- 
2.18.0

RE: [PATCH 3/3] fpga manager: Adding FPGA Manager support for Xilinx zynqmp

[Nava kishore Manne]

Hi Moritz,

	Thanks for the quick response...
Please find my response inline...

> -----Original Message-----
> From: Moritz Fischer [mailto:moritz.fischer.private@gmail.com]
> Sent: Saturday, October 20, 2018 2:54 AM
> To: Nava kishore Manne <navam@xilinx.com>
> Cc: Alan Tull <atull@kernel.org>; Rob Herring <robh+dt@kernel.org>; Mark
> Rutland <mark.rutland@arm.com>; Michal Simek <michals@xilinx.com>; Rajan
> Vaja <RAJANV@xilinx.com>; Jolly Shah <JOLLYS@xilinx.com>; linux-
> fpga@vger.kernel.org; Devicetree List <devicetree@vger.kernel.org>; linux-
> arm-kernel <linux-arm-kernel@lists.infradead.org>; Linux Kernel Mailing List
> <linux-kernel@vger.kernel.org>; chinnikishore369@gmail.com
> Subject: Re: [PATCH 3/3] fpga manager: Adding FPGA Manager support for
> Xilinx zynqmp
> 
> Hi Nava,
> 
> Looks good to me, a couple of nits inline below.
> 
> On Fri, Oct 19, 2018 at 1:50 AM Nava kishore Manne
> <nava.manne@xilinx.com> wrote:
> >
> > This patch adds FPGA Manager support for the Xilinx ZynqMp chip.
> 
> Isn't it ZynqMP ?

Will fix in the next version.

> >
> > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> > ---
> > Changes for v1:
> >                 -None.
> >
> > Changes for RFC-V2:
> >                 -Updated the Fpga Mgr registrations call's
> >                  to 4.18
> >
> >  drivers/fpga/Kconfig       |   9 +++
> >  drivers/fpga/Makefile      |   1 +
> >  drivers/fpga/zynqmp-fpga.c | 159
> > +++++++++++++++++++++++++++++++++++++
> >  3 files changed, 169 insertions(+)
> >  create mode 100644 drivers/fpga/zynqmp-fpga.c
> >
> > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index
> > 1ebcef4bab5b..26ebbcf3d3a3 100644
> > --- a/drivers/fpga/Kconfig
> > +++ b/drivers/fpga/Kconfig
> > @@ -56,6 +56,15 @@ config FPGA_MGR_ZYNQ_FPGA
> >         help
> >           FPGA manager driver support for Xilinx Zynq FPGAs.
> >
> > +config FPGA_MGR_ZYNQMP_FPGA
> > +       tristate "Xilinx Zynqmp FPGA"
> > +       depends on ARCH_ZYNQMP || COMPILE_TEST
> > +       help
> > +         FPGA manager driver support for Xilinx ZynqMP FPGAs.
> > +         This driver uses processor configuration port(PCAP)
> This driver uses *the* processor configuration port.
>

Will fix in the next version.
 
> > +         to configure the programmable logic(PL) through PS
> > +         on ZynqMP SoC.
> > +
> >  config FPGA_MGR_XILINX_SPI
> >         tristate "Xilinx Configuration over Slave Serial (SPI)"
> >         depends on SPI
> > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index
> > 7a2d73ba7122..3488ebbaee46 100644
> > --- a/drivers/fpga/Makefile
> > +++ b/drivers/fpga/Makefile
> > @@ -16,6 +16,7 @@ obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)    +=
> socfpga-a10.o
> >  obj-$(CONFIG_FPGA_MGR_TS73XX)          += ts73xx-fpga.o
> >  obj-$(CONFIG_FPGA_MGR_XILINX_SPI)      += xilinx-spi.o
> >  obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)       += zynq-fpga.o
> > +obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA)     += zynqmp-fpga.o
> >  obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
> >  obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)    += altera-pr-ip-core-plat.o
> >
> > diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c
> > new file mode 100644 index 000000000000..2760d7e3872a
> > --- /dev/null
> > +++ b/drivers/fpga/zynqmp-fpga.c
> > @@ -0,0 +1,159 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2018 Xilinx, Inc.
> > + */
> > +
> > +#include <linux/dma-mapping.h>
> > +#include <linux/fpga/fpga-mgr.h>
> > +#include <linux/io.h>
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/of_address.h>
> > +#include <linux/string.h>
> > +#include <linux/firmware/xlnx-zynqmp.h>
> > +
> > +/* Constant Definitions */
> > +#define IXR_FPGA_DONE_MASK     0X00000008U
> > +
> > +/**
> > + * struct zynqmp_fpga_priv - Private data structure
> > + * @dev:       Device data structure
> > + * @flags:     flags which is used to identify the bitfile type
> > + */
> > +struct zynqmp_fpga_priv {
> > +       struct device *dev;
> > +       u32 flags;
> > +};
> > +
> > +static int zynqmp_fpga_ops_write_init(struct fpga_manager *mgr,
> > +                                     struct fpga_image_info *info,
> > +                                     const char *buf, size_t size) {
> > +       struct zynqmp_fpga_priv *priv;
> > +
> > +       priv = mgr->priv;
> > +       priv->flags = info->flags;
> > +
> > +       return 0;
> > +}
> > +
> > +static int zynqmp_fpga_ops_write(struct fpga_manager *mgr,
> > +                                const char *buf, size_t size) {
> > +       struct zynqmp_fpga_priv *priv;
> > +       char *kbuf;
> > +       dma_addr_t dma_addr;
> > +       int ret;
> > +       const struct zynqmp_eemi_ops *eemi_ops =
> > +zynqmp_pm_get_eemi_ops();
> 
> Reverse xmas-tree please, i.e. long lines first.
> 
Will fix in the next version.

> > +
> > +       if (!eemi_ops || !eemi_ops->fpga_load)
> > +               return -ENXIO;
> > +
> > +       priv = mgr->priv;
> > +
> > +       kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL);
> > +       if (!kbuf)
> > +               return -ENOMEM;
> > +
> > +       memcpy(kbuf, buf, size);
> > +
> > +       wmb(); /* ensure all writes are done before initiate FW call
> > + */
> > +
> > +       ret = eemi_ops->fpga_load(dma_addr, size, priv->flags);
> > +
> > +       dma_free_coherent(priv->dev, size, kbuf, dma_addr);
> > +
> > +       return ret;
> > +}
> > +
> > +static int zynqmp_fpga_ops_write_complete(struct fpga_manager *mgr,
> > +                                         struct fpga_image_info
> > +*info) {
> > +       return 0;
> > +}
> > +
> > +static enum fpga_mgr_states zynqmp_fpga_ops_state(struct fpga_manager
> > +*mgr) {
> > +       u32 status;
> > +       const struct zynqmp_eemi_ops *eemi_ops =
> > +zynqmp_pm_get_eemi_ops();
> 
> Same here, split it up if necessary.

Will fix in the next version

> > +
> > +       if (!eemi_ops || !eemi_ops->fpga_get_status)
> > +               return FPGA_MGR_STATE_UNKNOWN;
> > +
> > +       eemi_ops->fpga_get_status(&status);
> > +       if (status & IXR_FPGA_DONE_MASK)
> > +               return FPGA_MGR_STATE_OPERATING;
> > +
> > +       return FPGA_MGR_STATE_UNKNOWN; }
> > +
> > +static const struct fpga_manager_ops zynqmp_fpga_ops = {
> > +       .state = zynqmp_fpga_ops_state,
> > +       .write_init = zynqmp_fpga_ops_write_init,
> > +       .write = zynqmp_fpga_ops_write,
> > +       .write_complete = zynqmp_fpga_ops_write_complete, };
> > +
> > +static int zynqmp_fpga_probe(struct platform_device *pdev) {
> > +       struct device *dev = &pdev->dev;
> > +       struct zynqmp_fpga_priv *priv;
> > +       struct fpga_manager *mgr;
> > +       int err, ret;
> > +
> > +       priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > +       if (!priv)
> > +               return -ENOMEM;
> > +
> > +       priv->dev = dev;
> > +       ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
> > +       if (ret < 0)
> > +               dev_err(dev, "no usable DMA configuration");
> 
> Do you wanna do something about this error if it happens? Return 'ret' maybe?

Will fix in the next version.

> > +
> > +       mgr = fpga_mgr_create(dev, "Xilinx ZynqMP FPGA Manager",
> > +                             &zynqmp_fpga_ops, priv);
> > +       if (!mgr)
> > +               return -ENOMEM;
> > +
> > +       platform_set_drvdata(pdev, mgr);
> > +
> > +       err = fpga_mgr_register(mgr);
> > +       if (err) {
> > +               dev_err(dev, "unable to register FPGA manager");
> > +               fpga_mgr_free(mgr);
> > +               return err;
> > +       }
> > +
> > +       return 0;
> > +}
> > +
> > +static int zynqmp_fpga_remove(struct platform_device *pdev) {
> > +       struct fpga_manager *mgr = platform_get_drvdata(pdev);
> > +
> > +       fpga_mgr_unregister(mgr);
> > +
> > +       return 0;
> > +}
> > +
> > +static const struct of_device_id zynqmp_fpga_of_match[] = {
> > +       { .compatible = "xlnx,zynqmp-pcap-fpga", },
> > +       {},
> > +};
> > +
> > +MODULE_DEVICE_TABLE(of, zynqmp_fpga_of_match);
> > +
> > +static struct platform_driver zynqmp_fpga_driver = {
> > +       .probe = zynqmp_fpga_probe,
> > +       .remove = zynqmp_fpga_remove,
> > +       .driver = {
> > +               .name = "zynqmp_fpga_manager",
> > +               .of_match_table = of_match_ptr(zynqmp_fpga_of_match),
> > +       },
> > +};
> > +
> > +module_platform_driver(zynqmp_fpga_driver);
> > +
> > +MODULE_AUTHOR("Nava kishore Manne <navam@xilinx.com>");
> > +MODULE_DESCRIPTION("Xilinx ZynqMp FPGA Manager");
> > +MODULE_LICENSE("GPL");
> > --
> > 2.18.0
> >
> 
> Thanks,
> 
> Moritz

[PATCH 3/3] fpga manager: Adding FPGA Manager support for Xilinx zynqmp

[Nava kishore Manne]

Hi Moritz,

	Thanks for the quick response...
Please find my response inline...

> -----Original Message-----
> From: Moritz Fischer [mailto:moritz.fischer.private at gmail.com]
> Sent: Saturday, October 20, 2018 2:54 AM
> To: Nava kishore Manne <navam@xilinx.com>
> Cc: Alan Tull <atull@kernel.org>; Rob Herring <robh+dt@kernel.org>; Mark
> Rutland <mark.rutland@arm.com>; Michal Simek <michals@xilinx.com>; Rajan
> Vaja <RAJANV@xilinx.com>; Jolly Shah <JOLLYS@xilinx.com>; linux-
> fpga at vger.kernel.org; Devicetree List <devicetree@vger.kernel.org>; linux-
> arm-kernel <linux-arm-kernel@lists.infradead.org>; Linux Kernel Mailing List
> <linux-kernel@vger.kernel.org>; chinnikishore369 at gmail.com
> Subject: Re: [PATCH 3/3] fpga manager: Adding FPGA Manager support for
> Xilinx zynqmp
> 
> Hi Nava,
> 
> Looks good to me, a couple of nits inline below.
> 
> On Fri, Oct 19, 2018 at 1:50 AM Nava kishore Manne
> <nava.manne@xilinx.com> wrote:
> >
> > This patch adds FPGA Manager support for the Xilinx ZynqMp chip.
> 
> Isn't it ZynqMP ?

Will fix in the next version.

> >
> > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> > ---
> > Changes for v1:
> >                 -None.
> >
> > Changes for RFC-V2:
> >                 -Updated the Fpga Mgr registrations call's
> >                  to 4.18
> >
> >  drivers/fpga/Kconfig       |   9 +++
> >  drivers/fpga/Makefile      |   1 +
> >  drivers/fpga/zynqmp-fpga.c | 159
> > +++++++++++++++++++++++++++++++++++++
> >  3 files changed, 169 insertions(+)
> >  create mode 100644 drivers/fpga/zynqmp-fpga.c
> >
> > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index
> > 1ebcef4bab5b..26ebbcf3d3a3 100644
> > --- a/drivers/fpga/Kconfig
> > +++ b/drivers/fpga/Kconfig
> > @@ -56,6 +56,15 @@ config FPGA_MGR_ZYNQ_FPGA
> >         help
> >           FPGA manager driver support for Xilinx Zynq FPGAs.
> >
> > +config FPGA_MGR_ZYNQMP_FPGA
> > +       tristate "Xilinx Zynqmp FPGA"
> > +       depends on ARCH_ZYNQMP || COMPILE_TEST
> > +       help
> > +         FPGA manager driver support for Xilinx ZynqMP FPGAs.
> > +         This driver uses processor configuration port(PCAP)
> This driver uses *the* processor configuration port.
>

Will fix in the next version.
 
> > +         to configure the programmable logic(PL) through PS
> > +         on ZynqMP SoC.
> > +
> >  config FPGA_MGR_XILINX_SPI
> >         tristate "Xilinx Configuration over Slave Serial (SPI)"
> >         depends on SPI
> > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index
> > 7a2d73ba7122..3488ebbaee46 100644
> > --- a/drivers/fpga/Makefile
> > +++ b/drivers/fpga/Makefile
> > @@ -16,6 +16,7 @@ obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)    +=
> socfpga-a10.o
> >  obj-$(CONFIG_FPGA_MGR_TS73XX)          += ts73xx-fpga.o
> >  obj-$(CONFIG_FPGA_MGR_XILINX_SPI)      += xilinx-spi.o
> >  obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)       += zynq-fpga.o
> > +obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA)     += zynqmp-fpga.o
> >  obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
> >  obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)    += altera-pr-ip-core-plat.o
> >
> > diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c
> > new file mode 100644 index 000000000000..2760d7e3872a
> > --- /dev/null
> > +++ b/drivers/fpga/zynqmp-fpga.c
> > @@ -0,0 +1,159 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2018 Xilinx, Inc.
> > + */
> > +
> > +#include <linux/dma-mapping.h>
> > +#include <linux/fpga/fpga-mgr.h>
> > +#include <linux/io.h>
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/of_address.h>
> > +#include <linux/string.h>
> > +#include <linux/firmware/xlnx-zynqmp.h>
> > +
> > +/* Constant Definitions */
> > +#define IXR_FPGA_DONE_MASK     0X00000008U
> > +
> > +/**
> > + * struct zynqmp_fpga_priv - Private data structure
> > + * @dev:       Device data structure
> > + * @flags:     flags which is used to identify the bitfile type
> > + */
> > +struct zynqmp_fpga_priv {
> > +       struct device *dev;
> > +       u32 flags;
> > +};
> > +
> > +static int zynqmp_fpga_ops_write_init(struct fpga_manager *mgr,
> > +                                     struct fpga_image_info *info,
> > +                                     const char *buf, size_t size) {
> > +       struct zynqmp_fpga_priv *priv;
> > +
> > +       priv = mgr->priv;
> > +       priv->flags = info->flags;
> > +
> > +       return 0;
> > +}
> > +
> > +static int zynqmp_fpga_ops_write(struct fpga_manager *mgr,
> > +                                const char *buf, size_t size) {
> > +       struct zynqmp_fpga_priv *priv;
> > +       char *kbuf;
> > +       dma_addr_t dma_addr;
> > +       int ret;
> > +       const struct zynqmp_eemi_ops *eemi_ops =
> > +zynqmp_pm_get_eemi_ops();
> 
> Reverse xmas-tree please, i.e. long lines first.
> 
Will fix in the next version.

> > +
> > +       if (!eemi_ops || !eemi_ops->fpga_load)
> > +               return -ENXIO;
> > +
> > +       priv = mgr->priv;
> > +
> > +       kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL);
> > +       if (!kbuf)
> > +               return -ENOMEM;
> > +
> > +       memcpy(kbuf, buf, size);
> > +
> > +       wmb(); /* ensure all writes are done before initiate FW call
> > + */
> > +
> > +       ret = eemi_ops->fpga_load(dma_addr, size, priv->flags);
> > +
> > +       dma_free_coherent(priv->dev, size, kbuf, dma_addr);
> > +
> > +       return ret;
> > +}
> > +
> > +static int zynqmp_fpga_ops_write_complete(struct fpga_manager *mgr,
> > +                                         struct fpga_image_info
> > +*info) {
> > +       return 0;
> > +}
> > +
> > +static enum fpga_mgr_states zynqmp_fpga_ops_state(struct fpga_manager
> > +*mgr) {
> > +       u32 status;
> > +       const struct zynqmp_eemi_ops *eemi_ops =
> > +zynqmp_pm_get_eemi_ops();
> 
> Same here, split it up if necessary.

Will fix in the next version

> > +
> > +       if (!eemi_ops || !eemi_ops->fpga_get_status)
> > +               return FPGA_MGR_STATE_UNKNOWN;
> > +
> > +       eemi_ops->fpga_get_status(&status);
> > +       if (status & IXR_FPGA_DONE_MASK)
> > +               return FPGA_MGR_STATE_OPERATING;
> > +
> > +       return FPGA_MGR_STATE_UNKNOWN; }
> > +
> > +static const struct fpga_manager_ops zynqmp_fpga_ops = {
> > +       .state = zynqmp_fpga_ops_state,
> > +       .write_init = zynqmp_fpga_ops_write_init,
> > +       .write = zynqmp_fpga_ops_write,
> > +       .write_complete = zynqmp_fpga_ops_write_complete, };
> > +
> > +static int zynqmp_fpga_probe(struct platform_device *pdev) {
> > +       struct device *dev = &pdev->dev;
> > +       struct zynqmp_fpga_priv *priv;
> > +       struct fpga_manager *mgr;
> > +       int err, ret;
> > +
> > +       priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > +       if (!priv)
> > +               return -ENOMEM;
> > +
> > +       priv->dev = dev;
> > +       ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
> > +       if (ret < 0)
> > +               dev_err(dev, "no usable DMA configuration");
> 
> Do you wanna do something about this error if it happens? Return 'ret' maybe?

Will fix in the next version.

> > +
> > +       mgr = fpga_mgr_create(dev, "Xilinx ZynqMP FPGA Manager",
> > +                             &zynqmp_fpga_ops, priv);
> > +       if (!mgr)
> > +               return -ENOMEM;
> > +
> > +       platform_set_drvdata(pdev, mgr);
> > +
> > +       err = fpga_mgr_register(mgr);
> > +       if (err) {
> > +               dev_err(dev, "unable to register FPGA manager");
> > +               fpga_mgr_free(mgr);
> > +               return err;
> > +       }
> > +
> > +       return 0;
> > +}
> > +
> > +static int zynqmp_fpga_remove(struct platform_device *pdev) {
> > +       struct fpga_manager *mgr = platform_get_drvdata(pdev);
> > +
> > +       fpga_mgr_unregister(mgr);
> > +
> > +       return 0;
> > +}
> > +
> > +static const struct of_device_id zynqmp_fpga_of_match[] = {
> > +       { .compatible = "xlnx,zynqmp-pcap-fpga", },
> > +       {},
> > +};
> > +
> > +MODULE_DEVICE_TABLE(of, zynqmp_fpga_of_match);
> > +
> > +static struct platform_driver zynqmp_fpga_driver = {
> > +       .probe = zynqmp_fpga_probe,
> > +       .remove = zynqmp_fpga_remove,
> > +       .driver = {
> > +               .name = "zynqmp_fpga_manager",
> > +               .of_match_table = of_match_ptr(zynqmp_fpga_of_match),
> > +       },
> > +};
> > +
> > +module_platform_driver(zynqmp_fpga_driver);
> > +
> > +MODULE_AUTHOR("Nava kishore Manne <navam@xilinx.com>");
> > +MODULE_DESCRIPTION("Xilinx ZynqMp FPGA Manager");
> > +MODULE_LICENSE("GPL");
> > --
> > 2.18.0
> >
> 
> Thanks,
> 
> Moritz

RE: [PATCH 3/3] fpga manager: Adding FPGA Manager support for Xilinx zynqmp

[Nava kishore Manne]

Hi Mortiz,

Thanks for the quick response....
Please find my response inline.

> -----Original Message-----
> From: Moritz Fischer [mailto:moritz.fischer@ettus.com]
> Sent: Saturday, October 20, 2018 7:02 AM
> To: Moritz Fischer <moritz.fischer.private@gmail.com>
> Cc: Nava kishore Manne <navam@xilinx.com>; Alan Tull <atull@kernel.org>;
> Rob Herring <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>;
> Michal Simek <michals@xilinx.com>; Rajan Vaja <RAJANV@xilinx.com>; Jolly
> Shah <JOLLYS@xilinx.com>; linux-fpga@vger.kernel.org; Devicetree List
> <devicetree@vger.kernel.org>; linux-arm-kernel <linux-arm-
> kernel@lists.infradead.org>; Linux Kernel Mailing List <linux-
> kernel@vger.kernel.org>; chinnikishore369@gmail.com
> Subject: Re: [PATCH 3/3] fpga manager: Adding FPGA Manager support for
> Xilinx zynqmp
> 
> On Fri, Oct 19, 2018 at 2:33 PM Moritz Fischer
> <moritz.fischer.private@gmail.com> wrote:
> >
> > Hi Nava,
> >
> > Looks good to me, a couple of nits inline below.
> >
> > On Fri, Oct 19, 2018 at 1:50 AM Nava kishore Manne
> > <nava.manne@xilinx.com> wrote:
> > >
> > > This patch adds FPGA Manager support for the Xilinx ZynqMp chip.
> >
> > Isn't it ZynqMP ?
> > >
> > > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> > > ---
> > > Changes for v1:
> > >                 -None.
> > >
> > > Changes for RFC-V2:
> > >                 -Updated the Fpga Mgr registrations call's
> > >                  to 4.18
> > >
> > >  drivers/fpga/Kconfig       |   9 +++
> > >  drivers/fpga/Makefile      |   1 +
> > >  drivers/fpga/zynqmp-fpga.c | 159
> > > +++++++++++++++++++++++++++++++++++++
> > >  3 files changed, 169 insertions(+)
> > >  create mode 100644 drivers/fpga/zynqmp-fpga.c
> > >
> > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index
> > > 1ebcef4bab5b..26ebbcf3d3a3 100644
> > > --- a/drivers/fpga/Kconfig
> > > +++ b/drivers/fpga/Kconfig
> > > @@ -56,6 +56,15 @@ config FPGA_MGR_ZYNQ_FPGA
> > >         help
> > >           FPGA manager driver support for Xilinx Zynq FPGAs.
> > >
> > > +config FPGA_MGR_ZYNQMP_FPGA
> > > +       tristate "Xilinx Zynqmp FPGA"
> > > +       depends on ARCH_ZYNQMP || COMPILE_TEST
> > > +       help
> > > +         FPGA manager driver support for Xilinx ZynqMP FPGAs.
> > > +         This driver uses processor configuration port(PCAP)
> > This driver uses *the* processor configuration port.
> >
> > > +         to configure the programmable logic(PL) through PS
> > > +         on ZynqMP SoC.
> > > +
> > >  config FPGA_MGR_XILINX_SPI
> > >         tristate "Xilinx Configuration over Slave Serial (SPI)"
> > >         depends on SPI
> > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index
> > > 7a2d73ba7122..3488ebbaee46 100644
> > > --- a/drivers/fpga/Makefile
> > > +++ b/drivers/fpga/Makefile
> > > @@ -16,6 +16,7 @@ obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)    +=
> socfpga-a10.o
> > >  obj-$(CONFIG_FPGA_MGR_TS73XX)          += ts73xx-fpga.o
> > >  obj-$(CONFIG_FPGA_MGR_XILINX_SPI)      += xilinx-spi.o
> > >  obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)       += zynq-fpga.o
> > > +obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA)     += zynqmp-fpga.o
> > >  obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
> > >  obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)    += altera-pr-ip-core-plat.o
> > >
> > > diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c
> > > new file mode 100644 index 000000000000..2760d7e3872a
> > > --- /dev/null
> > > +++ b/drivers/fpga/zynqmp-fpga.c
> > > @@ -0,0 +1,159 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * Copyright (C) 2018 Xilinx, Inc.
> > > + */
> > > +
> > > +#include <linux/dma-mapping.h>
> > > +#include <linux/fpga/fpga-mgr.h>
> > > +#include <linux/io.h>
> > > +#include <linux/kernel.h>
> > > +#include <linux/module.h>
> > > +#include <linux/of_address.h>
> > > +#include <linux/string.h>
> > > +#include <linux/firmware/xlnx-zynqmp.h>
> > > +
> > > +/* Constant Definitions */
> > > +#define IXR_FPGA_DONE_MASK     0X00000008U
> > > +
> > > +/**
> > > + * struct zynqmp_fpga_priv - Private data structure
> > > + * @dev:       Device data structure
> > > + * @flags:     flags which is used to identify the bitfile type
> > > + */
> > > +struct zynqmp_fpga_priv {
> > > +       struct device *dev;
> > > +       u32 flags;
> > > +};
> > > +
> > > +static int zynqmp_fpga_ops_write_init(struct fpga_manager *mgr,
> > > +                                     struct fpga_image_info *info,
> > > +                                     const char *buf, size_t size)
> > > +{
> > > +       struct zynqmp_fpga_priv *priv;
> > > +
> > > +       priv = mgr->priv;
> > > +       priv->flags = info->flags;
> > > +
> > > +       return 0;
> > > +}
> > > +
> > > +static int zynqmp_fpga_ops_write(struct fpga_manager *mgr,
> > > +                                const char *buf, size_t size) {
> > > +       struct zynqmp_fpga_priv *priv;
> > > +       char *kbuf;
> > > +       dma_addr_t dma_addr;
> > > +       int ret;
> > > +       const struct zynqmp_eemi_ops *eemi_ops =
> > > +zynqmp_pm_get_eemi_ops();
> >
> > Reverse xmas-tree please, i.e. long lines first.
> >
> > > +
> > > +       if (!eemi_ops || !eemi_ops->fpga_load)
> > > +               return -ENXIO;
> > > +
> > > +       priv = mgr->priv;
> > > +
> > > +       kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr,
> GFP_KERNEL);
> > > +       if (!kbuf)
> > > +               return -ENOMEM;
> > > +
> > > +       memcpy(kbuf, buf, size);
> > > +
> > > +       wmb(); /* ensure all writes are done before initiate FW call
> > > + */
> > > +
> > > +       ret = eemi_ops->fpga_load(dma_addr, size, priv->flags);
> 
> Don't you have to do anything with the flags? Is it really just a pass-through of
> FPGA manager flags to eemi calls?
> 
> Don't you want to make partial bitstreams e.g. use a flags value that you export
> in your firmware header (xlnx-zynqmp.h) and set those based on what flags get
> passed in, i.e. explicitely translate FPGA Manager flags to your firmware flags?

At this point of time the firmware use Flag 0 for full Bitstream and 1 for partial bitstream loading.
So I have not doing any explicit translate FPGA Manager flags inside the driver.
Will document the flags info in xlnx-zynqmp.h

Regards,
Navakishore.

[PATCH 3/3] fpga manager: Adding FPGA Manager support for Xilinx zynqmp

[Nava kishore Manne]

Hi Mortiz,

Thanks for the quick response....
Please find my response inline.

> -----Original Message-----
> From: Moritz Fischer [mailto:moritz.fischer at ettus.com]
> Sent: Saturday, October 20, 2018 7:02 AM
> To: Moritz Fischer <moritz.fischer.private@gmail.com>
> Cc: Nava kishore Manne <navam@xilinx.com>; Alan Tull <atull@kernel.org>;
> Rob Herring <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>;
> Michal Simek <michals@xilinx.com>; Rajan Vaja <RAJANV@xilinx.com>; Jolly
> Shah <JOLLYS@xilinx.com>; linux-fpga at vger.kernel.org; Devicetree List
> <devicetree@vger.kernel.org>; linux-arm-kernel <linux-arm-
> kernel at lists.infradead.org>; Linux Kernel Mailing List <linux-
> kernel at vger.kernel.org>; chinnikishore369 at gmail.com
> Subject: Re: [PATCH 3/3] fpga manager: Adding FPGA Manager support for
> Xilinx zynqmp
> 
> On Fri, Oct 19, 2018 at 2:33 PM Moritz Fischer
> <moritz.fischer.private@gmail.com> wrote:
> >
> > Hi Nava,
> >
> > Looks good to me, a couple of nits inline below.
> >
> > On Fri, Oct 19, 2018 at 1:50 AM Nava kishore Manne
> > <nava.manne@xilinx.com> wrote:
> > >
> > > This patch adds FPGA Manager support for the Xilinx ZynqMp chip.
> >
> > Isn't it ZynqMP ?
> > >
> > > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> > > ---
> > > Changes for v1:
> > >                 -None.
> > >
> > > Changes for RFC-V2:
> > >                 -Updated the Fpga Mgr registrations call's
> > >                  to 4.18
> > >
> > >  drivers/fpga/Kconfig       |   9 +++
> > >  drivers/fpga/Makefile      |   1 +
> > >  drivers/fpga/zynqmp-fpga.c | 159
> > > +++++++++++++++++++++++++++++++++++++
> > >  3 files changed, 169 insertions(+)
> > >  create mode 100644 drivers/fpga/zynqmp-fpga.c
> > >
> > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index
> > > 1ebcef4bab5b..26ebbcf3d3a3 100644
> > > --- a/drivers/fpga/Kconfig
> > > +++ b/drivers/fpga/Kconfig
> > > @@ -56,6 +56,15 @@ config FPGA_MGR_ZYNQ_FPGA
> > >         help
> > >           FPGA manager driver support for Xilinx Zynq FPGAs.
> > >
> > > +config FPGA_MGR_ZYNQMP_FPGA
> > > +       tristate "Xilinx Zynqmp FPGA"
> > > +       depends on ARCH_ZYNQMP || COMPILE_TEST
> > > +       help
> > > +         FPGA manager driver support for Xilinx ZynqMP FPGAs.
> > > +         This driver uses processor configuration port(PCAP)
> > This driver uses *the* processor configuration port.
> >
> > > +         to configure the programmable logic(PL) through PS
> > > +         on ZynqMP SoC.
> > > +
> > >  config FPGA_MGR_XILINX_SPI
> > >         tristate "Xilinx Configuration over Slave Serial (SPI)"
> > >         depends on SPI
> > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index
> > > 7a2d73ba7122..3488ebbaee46 100644
> > > --- a/drivers/fpga/Makefile
> > > +++ b/drivers/fpga/Makefile
> > > @@ -16,6 +16,7 @@ obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)    +=
> socfpga-a10.o
> > >  obj-$(CONFIG_FPGA_MGR_TS73XX)          += ts73xx-fpga.o
> > >  obj-$(CONFIG_FPGA_MGR_XILINX_SPI)      += xilinx-spi.o
> > >  obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)       += zynq-fpga.o
> > > +obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA)     += zynqmp-fpga.o
> > >  obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
> > >  obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)    += altera-pr-ip-core-plat.o
> > >
> > > diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c
> > > new file mode 100644 index 000000000000..2760d7e3872a
> > > --- /dev/null
> > > +++ b/drivers/fpga/zynqmp-fpga.c
> > > @@ -0,0 +1,159 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * Copyright (C) 2018 Xilinx, Inc.
> > > + */
> > > +
> > > +#include <linux/dma-mapping.h>
> > > +#include <linux/fpga/fpga-mgr.h>
> > > +#include <linux/io.h>
> > > +#include <linux/kernel.h>
> > > +#include <linux/module.h>
> > > +#include <linux/of_address.h>
> > > +#include <linux/string.h>
> > > +#include <linux/firmware/xlnx-zynqmp.h>
> > > +
> > > +/* Constant Definitions */
> > > +#define IXR_FPGA_DONE_MASK     0X00000008U
> > > +
> > > +/**
> > > + * struct zynqmp_fpga_priv - Private data structure
> > > + * @dev:       Device data structure
> > > + * @flags:     flags which is used to identify the bitfile type
> > > + */
> > > +struct zynqmp_fpga_priv {
> > > +       struct device *dev;
> > > +       u32 flags;
> > > +};
> > > +
> > > +static int zynqmp_fpga_ops_write_init(struct fpga_manager *mgr,
> > > +                                     struct fpga_image_info *info,
> > > +                                     const char *buf, size_t size)
> > > +{
> > > +       struct zynqmp_fpga_priv *priv;
> > > +
> > > +       priv = mgr->priv;
> > > +       priv->flags = info->flags;
> > > +
> > > +       return 0;
> > > +}
> > > +
> > > +static int zynqmp_fpga_ops_write(struct fpga_manager *mgr,
> > > +                                const char *buf, size_t size) {
> > > +       struct zynqmp_fpga_priv *priv;
> > > +       char *kbuf;
> > > +       dma_addr_t dma_addr;
> > > +       int ret;
> > > +       const struct zynqmp_eemi_ops *eemi_ops =
> > > +zynqmp_pm_get_eemi_ops();
> >
> > Reverse xmas-tree please, i.e. long lines first.
> >
> > > +
> > > +       if (!eemi_ops || !eemi_ops->fpga_load)
> > > +               return -ENXIO;
> > > +
> > > +       priv = mgr->priv;
> > > +
> > > +       kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr,
> GFP_KERNEL);
> > > +       if (!kbuf)
> > > +               return -ENOMEM;
> > > +
> > > +       memcpy(kbuf, buf, size);
> > > +
> > > +       wmb(); /* ensure all writes are done before initiate FW call
> > > + */
> > > +
> > > +       ret = eemi_ops->fpga_load(dma_addr, size, priv->flags);
> 
> Don't you have to do anything with the flags? Is it really just a pass-through of
> FPGA manager flags to eemi calls?
> 
> Don't you want to make partial bitstreams e.g. use a flags value that you export
> in your firmware header (xlnx-zynqmp.h) and set those based on what flags get
> passed in, i.e. explicitely translate FPGA Manager flags to your firmware flags?

At this point of time the firmware use Flag 0 for full Bitstream and 1 for partial bitstream loading.
So I have not doing any explicit translate FPGA Manager flags inside the driver.
Will document the flags info in xlnx-zynqmp.h

Regards,
Navakishore.

Re: [PATCH 3/3] fpga manager: Adding FPGA Manager support for Xilinx zynqmp

[Moritz Fischer]

On Mon, Oct 22, 2018 at 10:03:55AM +0000, Nava kishore Manne wrote:
> Hi Mortiz,
> 
> Thanks for the quick response....
> Please find my response inline.
> 
> > -----Original Message-----
> > From: Moritz Fischer [mailto:moritz.fischer@ettus.com]
> > Sent: Saturday, October 20, 2018 7:02 AM
> > To: Moritz Fischer <moritz.fischer.private@gmail.com>
> > Cc: Nava kishore Manne <navam@xilinx.com>; Alan Tull <atull@kernel.org>;
> > Rob Herring <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>;
> > Michal Simek <michals@xilinx.com>; Rajan Vaja <RAJANV@xilinx.com>; Jolly
> > Shah <JOLLYS@xilinx.com>; linux-fpga@vger.kernel.org; Devicetree List
> > <devicetree@vger.kernel.org>; linux-arm-kernel <linux-arm-
> > kernel@lists.infradead.org>; Linux Kernel Mailing List <linux-
> > kernel@vger.kernel.org>; chinnikishore369@gmail.com
> > Subject: Re: [PATCH 3/3] fpga manager: Adding FPGA Manager support for
> > Xilinx zynqmp
> > 
> > On Fri, Oct 19, 2018 at 2:33 PM Moritz Fischer
> > <moritz.fischer.private@gmail.com> wrote:
> > >
> > > Hi Nava,
> > >
> > > Looks good to me, a couple of nits inline below.
> > >
> > > On Fri, Oct 19, 2018 at 1:50 AM Nava kishore Manne
> > > <nava.manne@xilinx.com> wrote:
> > > >
> > > > This patch adds FPGA Manager support for the Xilinx ZynqMp chip.
> > >
> > > Isn't it ZynqMP ?
> > > >
> > > > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> > > > ---
> > > > Changes for v1:
> > > >                 -None.
> > > >
> > > > Changes for RFC-V2:
> > > >                 -Updated the Fpga Mgr registrations call's
> > > >                  to 4.18
> > > >
> > > >  drivers/fpga/Kconfig       |   9 +++
> > > >  drivers/fpga/Makefile      |   1 +
> > > >  drivers/fpga/zynqmp-fpga.c | 159
> > > > +++++++++++++++++++++++++++++++++++++
> > > >  3 files changed, 169 insertions(+)
> > > >  create mode 100644 drivers/fpga/zynqmp-fpga.c
> > > >
> > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index
> > > > 1ebcef4bab5b..26ebbcf3d3a3 100644
> > > > --- a/drivers/fpga/Kconfig
> > > > +++ b/drivers/fpga/Kconfig
> > > > @@ -56,6 +56,15 @@ config FPGA_MGR_ZYNQ_FPGA
> > > >         help
> > > >           FPGA manager driver support for Xilinx Zynq FPGAs.
> > > >
> > > > +config FPGA_MGR_ZYNQMP_FPGA
> > > > +       tristate "Xilinx Zynqmp FPGA"
> > > > +       depends on ARCH_ZYNQMP || COMPILE_TEST
> > > > +       help
> > > > +         FPGA manager driver support for Xilinx ZynqMP FPGAs.
> > > > +         This driver uses processor configuration port(PCAP)
> > > This driver uses *the* processor configuration port.
> > >
> > > > +         to configure the programmable logic(PL) through PS
> > > > +         on ZynqMP SoC.
> > > > +
> > > >  config FPGA_MGR_XILINX_SPI
> > > >         tristate "Xilinx Configuration over Slave Serial (SPI)"
> > > >         depends on SPI
> > > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index
> > > > 7a2d73ba7122..3488ebbaee46 100644
> > > > --- a/drivers/fpga/Makefile
> > > > +++ b/drivers/fpga/Makefile
> > > > @@ -16,6 +16,7 @@ obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)    +=
> > socfpga-a10.o
> > > >  obj-$(CONFIG_FPGA_MGR_TS73XX)          += ts73xx-fpga.o
> > > >  obj-$(CONFIG_FPGA_MGR_XILINX_SPI)      += xilinx-spi.o
> > > >  obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)       += zynq-fpga.o
> > > > +obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA)     += zynqmp-fpga.o
> > > >  obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
> > > >  obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)    += altera-pr-ip-core-plat.o
> > > >
> > > > diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c
> > > > new file mode 100644 index 000000000000..2760d7e3872a
> > > > --- /dev/null
> > > > +++ b/drivers/fpga/zynqmp-fpga.c
> > > > @@ -0,0 +1,159 @@
> > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > +/*
> > > > + * Copyright (C) 2018 Xilinx, Inc.
> > > > + */
> > > > +
> > > > +#include <linux/dma-mapping.h>
> > > > +#include <linux/fpga/fpga-mgr.h>
> > > > +#include <linux/io.h>
> > > > +#include <linux/kernel.h>
> > > > +#include <linux/module.h>
> > > > +#include <linux/of_address.h>
> > > > +#include <linux/string.h>
> > > > +#include <linux/firmware/xlnx-zynqmp.h>
> > > > +
> > > > +/* Constant Definitions */
> > > > +#define IXR_FPGA_DONE_MASK     0X00000008U
> > > > +
> > > > +/**
> > > > + * struct zynqmp_fpga_priv - Private data structure
> > > > + * @dev:       Device data structure
> > > > + * @flags:     flags which is used to identify the bitfile type
> > > > + */
> > > > +struct zynqmp_fpga_priv {
> > > > +       struct device *dev;
> > > > +       u32 flags;
> > > > +};
> > > > +
> > > > +static int zynqmp_fpga_ops_write_init(struct fpga_manager *mgr,
> > > > +                                     struct fpga_image_info *info,
> > > > +                                     const char *buf, size_t size)
> > > > +{
> > > > +       struct zynqmp_fpga_priv *priv;
> > > > +
> > > > +       priv = mgr->priv;
> > > > +       priv->flags = info->flags;
> > > > +
> > > > +       return 0;
> > > > +}
> > > > +
> > > > +static int zynqmp_fpga_ops_write(struct fpga_manager *mgr,
> > > > +                                const char *buf, size_t size) {
> > > > +       struct zynqmp_fpga_priv *priv;
> > > > +       char *kbuf;
> > > > +       dma_addr_t dma_addr;
> > > > +       int ret;
> > > > +       const struct zynqmp_eemi_ops *eemi_ops =
> > > > +zynqmp_pm_get_eemi_ops();
> > >
> > > Reverse xmas-tree please, i.e. long lines first.
> > >
> > > > +
> > > > +       if (!eemi_ops || !eemi_ops->fpga_load)
> > > > +               return -ENXIO;
> > > > +
> > > > +       priv = mgr->priv;
> > > > +
> > > > +       kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr,
> > GFP_KERNEL);
> > > > +       if (!kbuf)
> > > > +               return -ENOMEM;
> > > > +
> > > > +       memcpy(kbuf, buf, size);
> > > > +
> > > > +       wmb(); /* ensure all writes are done before initiate FW call
> > > > + */
> > > > +
> > > > +       ret = eemi_ops->fpga_load(dma_addr, size, priv->flags);
> > 
> > Don't you have to do anything with the flags? Is it really just a pass-through of
> > FPGA manager flags to eemi calls?
> > 
> > Don't you want to make partial bitstreams e.g. use a flags value that you export
> > in your firmware header (xlnx-zynqmp.h) and set those based on what flags get
> > passed in, i.e. explicitely translate FPGA Manager flags to your firmware flags?
> 
> At this point of time the firmware use Flag 0 for full Bitstream and 1 for partial bitstream loading.
> So I have not doing any explicit translate FPGA Manager flags inside the driver.
> Will document the flags info in xlnx-zynqmp.h

I think you should explicitely translate them, the fact that they happen
to line up in the current implementation is somewhat of coincidence, and
in future might break (since it's not really easy to to spot the
dependency when refactoring).

Why don't you do something like:

#include <linux/firmware/xilinx-zynqmp.h>

[...]

eemi_flags = 0;

if (flags & FPGA_MGR_PARTIAL_RECONFIG)
	eemi_flags |= XILINX_ZYNQMP_PM_FPGA_PARTIAL;

eemi_ops->fpga_load(...., eemi_flags);

Thanks,

Moritz

[PATCH 3/3] fpga manager: Adding FPGA Manager support for Xilinx zynqmp

[Moritz Fischer]

On Mon, Oct 22, 2018 at 10:03:55AM +0000, Nava kishore Manne wrote:
> Hi Mortiz,
> 
> Thanks for the quick response....
> Please find my response inline.
> 
> > -----Original Message-----
> > From: Moritz Fischer [mailto:moritz.fischer at ettus.com]
> > Sent: Saturday, October 20, 2018 7:02 AM
> > To: Moritz Fischer <moritz.fischer.private@gmail.com>
> > Cc: Nava kishore Manne <navam@xilinx.com>; Alan Tull <atull@kernel.org>;
> > Rob Herring <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>;
> > Michal Simek <michals@xilinx.com>; Rajan Vaja <RAJANV@xilinx.com>; Jolly
> > Shah <JOLLYS@xilinx.com>; linux-fpga at vger.kernel.org; Devicetree List
> > <devicetree@vger.kernel.org>; linux-arm-kernel <linux-arm-
> > kernel at lists.infradead.org>; Linux Kernel Mailing List <linux-
> > kernel at vger.kernel.org>; chinnikishore369 at gmail.com
> > Subject: Re: [PATCH 3/3] fpga manager: Adding FPGA Manager support for
> > Xilinx zynqmp
> > 
> > On Fri, Oct 19, 2018 at 2:33 PM Moritz Fischer
> > <moritz.fischer.private@gmail.com> wrote:
> > >
> > > Hi Nava,
> > >
> > > Looks good to me, a couple of nits inline below.
> > >
> > > On Fri, Oct 19, 2018 at 1:50 AM Nava kishore Manne
> > > <nava.manne@xilinx.com> wrote:
> > > >
> > > > This patch adds FPGA Manager support for the Xilinx ZynqMp chip.
> > >
> > > Isn't it ZynqMP ?
> > > >
> > > > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> > > > ---
> > > > Changes for v1:
> > > >                 -None.
> > > >
> > > > Changes for RFC-V2:
> > > >                 -Updated the Fpga Mgr registrations call's
> > > >                  to 4.18
> > > >
> > > >  drivers/fpga/Kconfig       |   9 +++
> > > >  drivers/fpga/Makefile      |   1 +
> > > >  drivers/fpga/zynqmp-fpga.c | 159
> > > > +++++++++++++++++++++++++++++++++++++
> > > >  3 files changed, 169 insertions(+)
> > > >  create mode 100644 drivers/fpga/zynqmp-fpga.c
> > > >
> > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index
> > > > 1ebcef4bab5b..26ebbcf3d3a3 100644
> > > > --- a/drivers/fpga/Kconfig
> > > > +++ b/drivers/fpga/Kconfig
> > > > @@ -56,6 +56,15 @@ config FPGA_MGR_ZYNQ_FPGA
> > > >         help
> > > >           FPGA manager driver support for Xilinx Zynq FPGAs.
> > > >
> > > > +config FPGA_MGR_ZYNQMP_FPGA
> > > > +       tristate "Xilinx Zynqmp FPGA"
> > > > +       depends on ARCH_ZYNQMP || COMPILE_TEST
> > > > +       help
> > > > +         FPGA manager driver support for Xilinx ZynqMP FPGAs.
> > > > +         This driver uses processor configuration port(PCAP)
> > > This driver uses *the* processor configuration port.
> > >
> > > > +         to configure the programmable logic(PL) through PS
> > > > +         on ZynqMP SoC.
> > > > +
> > > >  config FPGA_MGR_XILINX_SPI
> > > >         tristate "Xilinx Configuration over Slave Serial (SPI)"
> > > >         depends on SPI
> > > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index
> > > > 7a2d73ba7122..3488ebbaee46 100644
> > > > --- a/drivers/fpga/Makefile
> > > > +++ b/drivers/fpga/Makefile
> > > > @@ -16,6 +16,7 @@ obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)    +=
> > socfpga-a10.o
> > > >  obj-$(CONFIG_FPGA_MGR_TS73XX)          += ts73xx-fpga.o
> > > >  obj-$(CONFIG_FPGA_MGR_XILINX_SPI)      += xilinx-spi.o
> > > >  obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)       += zynq-fpga.o
> > > > +obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA)     += zynqmp-fpga.o
> > > >  obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
> > > >  obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)    += altera-pr-ip-core-plat.o
> > > >
> > > > diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c
> > > > new file mode 100644 index 000000000000..2760d7e3872a
> > > > --- /dev/null
> > > > +++ b/drivers/fpga/zynqmp-fpga.c
> > > > @@ -0,0 +1,159 @@
> > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > +/*
> > > > + * Copyright (C) 2018 Xilinx, Inc.
> > > > + */
> > > > +
> > > > +#include <linux/dma-mapping.h>
> > > > +#include <linux/fpga/fpga-mgr.h>
> > > > +#include <linux/io.h>
> > > > +#include <linux/kernel.h>
> > > > +#include <linux/module.h>
> > > > +#include <linux/of_address.h>
> > > > +#include <linux/string.h>
> > > > +#include <linux/firmware/xlnx-zynqmp.h>
> > > > +
> > > > +/* Constant Definitions */
> > > > +#define IXR_FPGA_DONE_MASK     0X00000008U
> > > > +
> > > > +/**
> > > > + * struct zynqmp_fpga_priv - Private data structure
> > > > + * @dev:       Device data structure
> > > > + * @flags:     flags which is used to identify the bitfile type
> > > > + */
> > > > +struct zynqmp_fpga_priv {
> > > > +       struct device *dev;
> > > > +       u32 flags;
> > > > +};
> > > > +
> > > > +static int zynqmp_fpga_ops_write_init(struct fpga_manager *mgr,
> > > > +                                     struct fpga_image_info *info,
> > > > +                                     const char *buf, size_t size)
> > > > +{
> > > > +       struct zynqmp_fpga_priv *priv;
> > > > +
> > > > +       priv = mgr->priv;
> > > > +       priv->flags = info->flags;
> > > > +
> > > > +       return 0;
> > > > +}
> > > > +
> > > > +static int zynqmp_fpga_ops_write(struct fpga_manager *mgr,
> > > > +                                const char *buf, size_t size) {
> > > > +       struct zynqmp_fpga_priv *priv;
> > > > +       char *kbuf;
> > > > +       dma_addr_t dma_addr;
> > > > +       int ret;
> > > > +       const struct zynqmp_eemi_ops *eemi_ops =
> > > > +zynqmp_pm_get_eemi_ops();
> > >
> > > Reverse xmas-tree please, i.e. long lines first.
> > >
> > > > +
> > > > +       if (!eemi_ops || !eemi_ops->fpga_load)
> > > > +               return -ENXIO;
> > > > +
> > > > +       priv = mgr->priv;
> > > > +
> > > > +       kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr,
> > GFP_KERNEL);
> > > > +       if (!kbuf)
> > > > +               return -ENOMEM;
> > > > +
> > > > +       memcpy(kbuf, buf, size);
> > > > +
> > > > +       wmb(); /* ensure all writes are done before initiate FW call
> > > > + */
> > > > +
> > > > +       ret = eemi_ops->fpga_load(dma_addr, size, priv->flags);
> > 
> > Don't you have to do anything with the flags? Is it really just a pass-through of
> > FPGA manager flags to eemi calls?
> > 
> > Don't you want to make partial bitstreams e.g. use a flags value that you export
> > in your firmware header (xlnx-zynqmp.h) and set those based on what flags get
> > passed in, i.e. explicitely translate FPGA Manager flags to your firmware flags?
> 
> At this point of time the firmware use Flag 0 for full Bitstream and 1 for partial bitstream loading.
> So I have not doing any explicit translate FPGA Manager flags inside the driver.
> Will document the flags info in xlnx-zynqmp.h

I think you should explicitely translate them, the fact that they happen
to line up in the current implementation is somewhat of coincidence, and
in future might break (since it's not really easy to to spot the
dependency when refactoring).

Why don't you do something like:

#include <linux/firmware/xilinx-zynqmp.h>

[...]

eemi_flags = 0;

if (flags & FPGA_MGR_PARTIAL_RECONFIG)
	eemi_flags |= XILINX_ZYNQMP_PM_FPGA_PARTIAL;

eemi_ops->fpga_load(...., eemi_flags);

Thanks,

Moritz

RE: [PATCH 3/3] fpga manager: Adding FPGA Manager support for Xilinx zynqmp

[Nava kishore Manne]

Hi Moritz,

Thanks for the quick response..
Please find my response inline.

> -----Original Message-----
> From: Moritz Fischer [mailto:mdf@kernel.org]
> Sent: Monday, October 22, 2018 3:53 PM
> To: Nava kishore Manne <navam@xilinx.com>
> Cc: Moritz Fischer <moritz.fischer@ettus.com>; Moritz Fischer
> <moritz.fischer.private@gmail.com>; Alan Tull <atull@kernel.org>; Rob Herring
> <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>; Michal Simek
> <michals@xilinx.com>; Rajan Vaja <RAJANV@xilinx.com>; Jolly Shah
> <JOLLYS@xilinx.com>; linux-fpga@vger.kernel.org; Devicetree List
> <devicetree@vger.kernel.org>; linux-arm-kernel <linux-arm-
> kernel@lists.infradead.org>; Linux Kernel Mailing List <linux-
> kernel@vger.kernel.org>; chinnikishore369@gmail.com
> Subject: Re: [PATCH 3/3] fpga manager: Adding FPGA Manager support for
> Xilinx zynqmp
> 
> On Mon, Oct 22, 2018 at 10:03:55AM +0000, Nava kishore Manne wrote:
> > Hi Mortiz,
> >
> > Thanks for the quick response....
> > Please find my response inline.
> >
> > > -----Original Message-----
> > > From: Moritz Fischer [mailto:moritz.fischer@ettus.com]
> > > Sent: Saturday, October 20, 2018 7:02 AM
> > > To: Moritz Fischer <moritz.fischer.private@gmail.com>
> > > Cc: Nava kishore Manne <navam@xilinx.com>; Alan Tull
> > > <atull@kernel.org>; Rob Herring <robh+dt@kernel.org>; Mark Rutland
> > > <mark.rutland@arm.com>; Michal Simek <michals@xilinx.com>; Rajan
> > > Vaja <RAJANV@xilinx.com>; Jolly Shah <JOLLYS@xilinx.com>;
> > > linux-fpga@vger.kernel.org; Devicetree List
> > > <devicetree@vger.kernel.org>; linux-arm-kernel <linux-arm-
> > > kernel@lists.infradead.org>; Linux Kernel Mailing List <linux-
> > > kernel@vger.kernel.org>; chinnikishore369@gmail.com
> > > Subject: Re: [PATCH 3/3] fpga manager: Adding FPGA Manager support
> > > for Xilinx zynqmp
> > >
> > > On Fri, Oct 19, 2018 at 2:33 PM Moritz Fischer
> > > <moritz.fischer.private@gmail.com> wrote:
> > > >
> > > > Hi Nava,
> > > >
> > > > Looks good to me, a couple of nits inline below.
> > > >
> > > > On Fri, Oct 19, 2018 at 1:50 AM Nava kishore Manne
> > > > <nava.manne@xilinx.com> wrote:
> > > > >
> > > > > This patch adds FPGA Manager support for the Xilinx ZynqMp chip.
> > > >
> > > > Isn't it ZynqMP ?
> > > > >
> > > > > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> > > > > ---
> > > > > Changes for v1:
> > > > >                 -None.
> > > > >
> > > > > Changes for RFC-V2:
> > > > >                 -Updated the Fpga Mgr registrations call's
> > > > >                  to 4.18
> > > > >
> > > > >  drivers/fpga/Kconfig       |   9 +++
> > > > >  drivers/fpga/Makefile      |   1 +
> > > > >  drivers/fpga/zynqmp-fpga.c | 159
> > > > > +++++++++++++++++++++++++++++++++++++
> > > > >  3 files changed, 169 insertions(+)  create mode 100644
> > > > > drivers/fpga/zynqmp-fpga.c
> > > > >
> > > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index
> > > > > 1ebcef4bab5b..26ebbcf3d3a3 100644
> > > > > --- a/drivers/fpga/Kconfig
> > > > > +++ b/drivers/fpga/Kconfig
> > > > > @@ -56,6 +56,15 @@ config FPGA_MGR_ZYNQ_FPGA
> > > > >         help
> > > > >           FPGA manager driver support for Xilinx Zynq FPGAs.
> > > > >
> > > > > +config FPGA_MGR_ZYNQMP_FPGA
> > > > > +       tristate "Xilinx Zynqmp FPGA"
> > > > > +       depends on ARCH_ZYNQMP || COMPILE_TEST
> > > > > +       help
> > > > > +         FPGA manager driver support for Xilinx ZynqMP FPGAs.
> > > > > +         This driver uses processor configuration port(PCAP)
> > > > This driver uses *the* processor configuration port.
> > > >
> > > > > +         to configure the programmable logic(PL) through PS
> > > > > +         on ZynqMP SoC.
> > > > > +
> > > > >  config FPGA_MGR_XILINX_SPI
> > > > >         tristate "Xilinx Configuration over Slave Serial (SPI)"
> > > > >         depends on SPI
> > > > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index
> > > > > 7a2d73ba7122..3488ebbaee46 100644
> > > > > --- a/drivers/fpga/Makefile
> > > > > +++ b/drivers/fpga/Makefile
> > > > > @@ -16,6 +16,7 @@ obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)    +=
> > > socfpga-a10.o
> > > > >  obj-$(CONFIG_FPGA_MGR_TS73XX)          += ts73xx-fpga.o
> > > > >  obj-$(CONFIG_FPGA_MGR_XILINX_SPI)      += xilinx-spi.o
> > > > >  obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)       += zynq-fpga.o
> > > > > +obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA)     += zynqmp-fpga.o
> > > > >  obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
> > > > >  obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)    += altera-pr-ip-core-plat.o
> > > > >
> > > > > diff --git a/drivers/fpga/zynqmp-fpga.c
> > > > > b/drivers/fpga/zynqmp-fpga.c new file mode 100644 index
> > > > > 000000000000..2760d7e3872a
> > > > > --- /dev/null
> > > > > +++ b/drivers/fpga/zynqmp-fpga.c
> > > > > @@ -0,0 +1,159 @@
> > > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > > +/*
> > > > > + * Copyright (C) 2018 Xilinx, Inc.
> > > > > + */
> > > > > +
> > > > > +#include <linux/dma-mapping.h>
> > > > > +#include <linux/fpga/fpga-mgr.h> #include <linux/io.h> #include
> > > > > +<linux/kernel.h> #include <linux/module.h> #include
> > > > > +<linux/of_address.h> #include <linux/string.h> #include
> > > > > +<linux/firmware/xlnx-zynqmp.h>
> > > > > +
> > > > > +/* Constant Definitions */
> > > > > +#define IXR_FPGA_DONE_MASK     0X00000008U
> > > > > +
> > > > > +/**
> > > > > + * struct zynqmp_fpga_priv - Private data structure
> > > > > + * @dev:       Device data structure
> > > > > + * @flags:     flags which is used to identify the bitfile type
> > > > > + */
> > > > > +struct zynqmp_fpga_priv {
> > > > > +       struct device *dev;
> > > > > +       u32 flags;
> > > > > +};
> > > > > +
> > > > > +static int zynqmp_fpga_ops_write_init(struct fpga_manager *mgr,
> > > > > +                                     struct fpga_image_info *info,
> > > > > +                                     const char *buf, size_t
> > > > > +size) {
> > > > > +       struct zynqmp_fpga_priv *priv;
> > > > > +
> > > > > +       priv = mgr->priv;
> > > > > +       priv->flags = info->flags;
> > > > > +
> > > > > +       return 0;
> > > > > +}
> > > > > +
> > > > > +static int zynqmp_fpga_ops_write(struct fpga_manager *mgr,
> > > > > +                                const char *buf, size_t size) {
> > > > > +       struct zynqmp_fpga_priv *priv;
> > > > > +       char *kbuf;
> > > > > +       dma_addr_t dma_addr;
> > > > > +       int ret;
> > > > > +       const struct zynqmp_eemi_ops *eemi_ops =
> > > > > +zynqmp_pm_get_eemi_ops();
> > > >
> > > > Reverse xmas-tree please, i.e. long lines first.
> > > >
> > > > > +
> > > > > +       if (!eemi_ops || !eemi_ops->fpga_load)
> > > > > +               return -ENXIO;
> > > > > +
> > > > > +       priv = mgr->priv;
> > > > > +
> > > > > +       kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr,
> > > GFP_KERNEL);
> > > > > +       if (!kbuf)
> > > > > +               return -ENOMEM;
> > > > > +
> > > > > +       memcpy(kbuf, buf, size);
> > > > > +
> > > > > +       wmb(); /* ensure all writes are done before initiate FW
> > > > > + call */
> > > > > +
> > > > > +       ret = eemi_ops->fpga_load(dma_addr, size, priv->flags);
> > >
> > > Don't you have to do anything with the flags? Is it really just a
> > > pass-through of FPGA manager flags to eemi calls?
> > >
> > > Don't you want to make partial bitstreams e.g. use a flags value
> > > that you export in your firmware header (xlnx-zynqmp.h) and set
> > > those based on what flags get passed in, i.e. explicitely translate FPGA
> Manager flags to your firmware flags?
> >
> > At this point of time the firmware use Flag 0 for full Bitstream and 1 for partial
> bitstream loading.
> > So I have not doing any explicit translate FPGA Manager flags inside the
> driver.
> > Will document the flags info in xlnx-zynqmp.h
> 
> I think you should explicitely translate them, the fact that they happen to line
> up in the current implementation is somewhat of coincidence, and in future
> might break (since it's not really easy to to spot the dependency when
> refactoring).
> 
> Why don't you do something like:
> 
> #include <linux/firmware/xilinx-zynqmp.h>
> 
> [...]
> 
> eemi_flags = 0;
> 
> if (flags & FPGA_MGR_PARTIAL_RECONFIG)
> 	eemi_flags |= XILINX_ZYNQMP_PM_FPGA_PARTIAL;
> 
> eemi_ops->fpga_load(...., eemi_flags);
> 

Yes, I agree with you and it's sound good. Will fix in the next version.

Regards,
Navakishore.

[PATCH 3/3] fpga manager: Adding FPGA Manager support for Xilinx zynqmp

[Nava kishore Manne]

Hi Moritz,

Thanks for the quick response..
Please find my response inline.

> -----Original Message-----
> From: Moritz Fischer [mailto:mdf at kernel.org]
> Sent: Monday, October 22, 2018 3:53 PM
> To: Nava kishore Manne <navam@xilinx.com>
> Cc: Moritz Fischer <moritz.fischer@ettus.com>; Moritz Fischer
> <moritz.fischer.private@gmail.com>; Alan Tull <atull@kernel.org>; Rob Herring
> <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>; Michal Simek
> <michals@xilinx.com>; Rajan Vaja <RAJANV@xilinx.com>; Jolly Shah
> <JOLLYS@xilinx.com>; linux-fpga at vger.kernel.org; Devicetree List
> <devicetree@vger.kernel.org>; linux-arm-kernel <linux-arm-
> kernel at lists.infradead.org>; Linux Kernel Mailing List <linux-
> kernel at vger.kernel.org>; chinnikishore369 at gmail.com
> Subject: Re: [PATCH 3/3] fpga manager: Adding FPGA Manager support for
> Xilinx zynqmp
> 
> On Mon, Oct 22, 2018 at 10:03:55AM +0000, Nava kishore Manne wrote:
> > Hi Mortiz,
> >
> > Thanks for the quick response....
> > Please find my response inline.
> >
> > > -----Original Message-----
> > > From: Moritz Fischer [mailto:moritz.fischer at ettus.com]
> > > Sent: Saturday, October 20, 2018 7:02 AM
> > > To: Moritz Fischer <moritz.fischer.private@gmail.com>
> > > Cc: Nava kishore Manne <navam@xilinx.com>; Alan Tull
> > > <atull@kernel.org>; Rob Herring <robh+dt@kernel.org>; Mark Rutland
> > > <mark.rutland@arm.com>; Michal Simek <michals@xilinx.com>; Rajan
> > > Vaja <RAJANV@xilinx.com>; Jolly Shah <JOLLYS@xilinx.com>;
> > > linux-fpga at vger.kernel.org; Devicetree List
> > > <devicetree@vger.kernel.org>; linux-arm-kernel <linux-arm-
> > > kernel at lists.infradead.org>; Linux Kernel Mailing List <linux-
> > > kernel at vger.kernel.org>; chinnikishore369 at gmail.com
> > > Subject: Re: [PATCH 3/3] fpga manager: Adding FPGA Manager support
> > > for Xilinx zynqmp
> > >
> > > On Fri, Oct 19, 2018 at 2:33 PM Moritz Fischer
> > > <moritz.fischer.private@gmail.com> wrote:
> > > >
> > > > Hi Nava,
> > > >
> > > > Looks good to me, a couple of nits inline below.
> > > >
> > > > On Fri, Oct 19, 2018 at 1:50 AM Nava kishore Manne
> > > > <nava.manne@xilinx.com> wrote:
> > > > >
> > > > > This patch adds FPGA Manager support for the Xilinx ZynqMp chip.
> > > >
> > > > Isn't it ZynqMP ?
> > > > >
> > > > > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> > > > > ---
> > > > > Changes for v1:
> > > > >                 -None.
> > > > >
> > > > > Changes for RFC-V2:
> > > > >                 -Updated the Fpga Mgr registrations call's
> > > > >                  to 4.18
> > > > >
> > > > >  drivers/fpga/Kconfig       |   9 +++
> > > > >  drivers/fpga/Makefile      |   1 +
> > > > >  drivers/fpga/zynqmp-fpga.c | 159
> > > > > +++++++++++++++++++++++++++++++++++++
> > > > >  3 files changed, 169 insertions(+)  create mode 100644
> > > > > drivers/fpga/zynqmp-fpga.c
> > > > >
> > > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index
> > > > > 1ebcef4bab5b..26ebbcf3d3a3 100644
> > > > > --- a/drivers/fpga/Kconfig
> > > > > +++ b/drivers/fpga/Kconfig
> > > > > @@ -56,6 +56,15 @@ config FPGA_MGR_ZYNQ_FPGA
> > > > >         help
> > > > >           FPGA manager driver support for Xilinx Zynq FPGAs.
> > > > >
> > > > > +config FPGA_MGR_ZYNQMP_FPGA
> > > > > +       tristate "Xilinx Zynqmp FPGA"
> > > > > +       depends on ARCH_ZYNQMP || COMPILE_TEST
> > > > > +       help
> > > > > +         FPGA manager driver support for Xilinx ZynqMP FPGAs.
> > > > > +         This driver uses processor configuration port(PCAP)
> > > > This driver uses *the* processor configuration port.
> > > >
> > > > > +         to configure the programmable logic(PL) through PS
> > > > > +         on ZynqMP SoC.
> > > > > +
> > > > >  config FPGA_MGR_XILINX_SPI
> > > > >         tristate "Xilinx Configuration over Slave Serial (SPI)"
> > > > >         depends on SPI
> > > > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index
> > > > > 7a2d73ba7122..3488ebbaee46 100644
> > > > > --- a/drivers/fpga/Makefile
> > > > > +++ b/drivers/fpga/Makefile
> > > > > @@ -16,6 +16,7 @@ obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)    +=
> > > socfpga-a10.o
> > > > >  obj-$(CONFIG_FPGA_MGR_TS73XX)          += ts73xx-fpga.o
> > > > >  obj-$(CONFIG_FPGA_MGR_XILINX_SPI)      += xilinx-spi.o
> > > > >  obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)       += zynq-fpga.o
> > > > > +obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA)     += zynqmp-fpga.o
> > > > >  obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
> > > > >  obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)    += altera-pr-ip-core-plat.o
> > > > >
> > > > > diff --git a/drivers/fpga/zynqmp-fpga.c
> > > > > b/drivers/fpga/zynqmp-fpga.c new file mode 100644 index
> > > > > 000000000000..2760d7e3872a
> > > > > --- /dev/null
> > > > > +++ b/drivers/fpga/zynqmp-fpga.c
> > > > > @@ -0,0 +1,159 @@
> > > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > > +/*
> > > > > + * Copyright (C) 2018 Xilinx, Inc.
> > > > > + */
> > > > > +
> > > > > +#include <linux/dma-mapping.h>
> > > > > +#include <linux/fpga/fpga-mgr.h> #include <linux/io.h> #include
> > > > > +<linux/kernel.h> #include <linux/module.h> #include
> > > > > +<linux/of_address.h> #include <linux/string.h> #include
> > > > > +<linux/firmware/xlnx-zynqmp.h>
> > > > > +
> > > > > +/* Constant Definitions */
> > > > > +#define IXR_FPGA_DONE_MASK     0X00000008U
> > > > > +
> > > > > +/**
> > > > > + * struct zynqmp_fpga_priv - Private data structure
> > > > > + * @dev:       Device data structure
> > > > > + * @flags:     flags which is used to identify the bitfile type
> > > > > + */
> > > > > +struct zynqmp_fpga_priv {
> > > > > +       struct device *dev;
> > > > > +       u32 flags;
> > > > > +};
> > > > > +
> > > > > +static int zynqmp_fpga_ops_write_init(struct fpga_manager *mgr,
> > > > > +                                     struct fpga_image_info *info,
> > > > > +                                     const char *buf, size_t
> > > > > +size) {
> > > > > +       struct zynqmp_fpga_priv *priv;
> > > > > +
> > > > > +       priv = mgr->priv;
> > > > > +       priv->flags = info->flags;
> > > > > +
> > > > > +       return 0;
> > > > > +}
> > > > > +
> > > > > +static int zynqmp_fpga_ops_write(struct fpga_manager *mgr,
> > > > > +                                const char *buf, size_t size) {
> > > > > +       struct zynqmp_fpga_priv *priv;
> > > > > +       char *kbuf;
> > > > > +       dma_addr_t dma_addr;
> > > > > +       int ret;
> > > > > +       const struct zynqmp_eemi_ops *eemi_ops =
> > > > > +zynqmp_pm_get_eemi_ops();
> > > >
> > > > Reverse xmas-tree please, i.e. long lines first.
> > > >
> > > > > +
> > > > > +       if (!eemi_ops || !eemi_ops->fpga_load)
> > > > > +               return -ENXIO;
> > > > > +
> > > > > +       priv = mgr->priv;
> > > > > +
> > > > > +       kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr,
> > > GFP_KERNEL);
> > > > > +       if (!kbuf)
> > > > > +               return -ENOMEM;
> > > > > +
> > > > > +       memcpy(kbuf, buf, size);
> > > > > +
> > > > > +       wmb(); /* ensure all writes are done before initiate FW
> > > > > + call */
> > > > > +
> > > > > +       ret = eemi_ops->fpga_load(dma_addr, size, priv->flags);
> > >
> > > Don't you have to do anything with the flags? Is it really just a
> > > pass-through of FPGA manager flags to eemi calls?
> > >
> > > Don't you want to make partial bitstreams e.g. use a flags value
> > > that you export in your firmware header (xlnx-zynqmp.h) and set
> > > those based on what flags get passed in, i.e. explicitely translate FPGA
> Manager flags to your firmware flags?
> >
> > At this point of time the firmware use Flag 0 for full Bitstream and 1 for partial
> bitstream loading.
> > So I have not doing any explicit translate FPGA Manager flags inside the
> driver.
> > Will document the flags info in xlnx-zynqmp.h
> 
> I think you should explicitely translate them, the fact that they happen to line
> up in the current implementation is somewhat of coincidence, and in future
> might break (since it's not really easy to to spot the dependency when
> refactoring).
> 
> Why don't you do something like:
> 
> #include <linux/firmware/xilinx-zynqmp.h>
> 
> [...]
> 
> eemi_flags = 0;
> 
> if (flags & FPGA_MGR_PARTIAL_RECONFIG)
> 	eemi_flags |= XILINX_ZYNQMP_PM_FPGA_PARTIAL;
> 
> eemi_ops->fpga_load(...., eemi_flags);
> 

Yes, I agree with you and it's sound good. Will fix in the next version.

Regards,
Navakishore.

Re: [PATCH 0/3] Add Bitstream configuration support for ZynqMP

[Alan Tull]

On Fri, Oct 19, 2018 at 3:49 AM Nava kishore Manne
<nava.manne@xilinx.com> wrote:

Hi Nava,

>
> This series of patches are created On top of the
> below repo.
> //git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git
> BRANCH: next/drivers.

IIUC this is dependent on some patches that aren't released yet.
Please make this explicit by specifying which patches this is
dependent on in each future submission of new versions.  It will help
so that I don't send these upstream prematurely and introduce build
breaks.  Of course, we can keep reviewing!

Thanks for submitting!
Alan

>
> Nava kishore Manne (3):
>   firmware: xilinx: Add fpga API's
>   dt-bindings: fpga: Add bindings for ZynqMP fpga driver
>   fpga manager: Adding FPGA Manager support for Xilinx zynqmp
>
>  .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt   |  17 ++
>  drivers/firmware/xilinx/zynqmp.c              |  46 +++++
>  drivers/fpga/Kconfig                          |   9 +
>  drivers/fpga/Makefile                         |   1 +
>  drivers/fpga/zynqmp-fpga.c                    | 159 ++++++++++++++++++
>  include/linux/firmware/xlnx-zynqmp.h          |   4 +
>  6 files changed, 236 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
>  create mode 100644 drivers/fpga/zynqmp-fpga.c
>
> --
> 2.18.0
>

Re: [PATCH 0/3] Add Bitstream configuration support for ZynqMP

[Alan Tull]

On Fri, Oct 19, 2018 at 3:49 AM Nava kishore Manne
<nava.manne@xilinx.com> wrote:

Hi Nava,

>
> This series of patches are created On top of the
> below repo.
> //git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git
> BRANCH: next/drivers.

IIUC this is dependent on some patches that aren't released yet.
Please make this explicit by specifying which patches this is
dependent on in each future submission of new versions.  It will help
so that I don't send these upstream prematurely and introduce build
breaks.  Of course, we can keep reviewing!

Thanks for submitting!
Alan

>
> Nava kishore Manne (3):
>   firmware: xilinx: Add fpga API's
>   dt-bindings: fpga: Add bindings for ZynqMP fpga driver
>   fpga manager: Adding FPGA Manager support for Xilinx zynqmp
>
>  .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt   |  17 ++
>  drivers/firmware/xilinx/zynqmp.c              |  46 +++++
>  drivers/fpga/Kconfig                          |   9 +
>  drivers/fpga/Makefile                         |   1 +
>  drivers/fpga/zynqmp-fpga.c                    | 159 ++++++++++++++++++
>  include/linux/firmware/xlnx-zynqmp.h          |   4 +
>  6 files changed, 236 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
>  create mode 100644 drivers/fpga/zynqmp-fpga.c
>
> --
> 2.18.0
>

[PATCH 0/3] Add Bitstream configuration support for ZynqMP

[Alan Tull]

On Fri, Oct 19, 2018 at 3:49 AM Nava kishore Manne
<nava.manne@xilinx.com> wrote:

Hi Nava,

>
> This series of patches are created On top of the
> below repo.
> //git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git
> BRANCH: next/drivers.

IIUC this is dependent on some patches that aren't released yet.
Please make this explicit by specifying which patches this is
dependent on in each future submission of new versions.  It will help
so that I don't send these upstream prematurely and introduce build
breaks.  Of course, we can keep reviewing!

Thanks for submitting!
Alan

>
> Nava kishore Manne (3):
>   firmware: xilinx: Add fpga API's
>   dt-bindings: fpga: Add bindings for ZynqMP fpga driver
>   fpga manager: Adding FPGA Manager support for Xilinx zynqmp
>
>  .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt   |  17 ++
>  drivers/firmware/xilinx/zynqmp.c              |  46 +++++
>  drivers/fpga/Kconfig                          |   9 +
>  drivers/fpga/Makefile                         |   1 +
>  drivers/fpga/zynqmp-fpga.c                    | 159 ++++++++++++++++++
>  include/linux/firmware/xlnx-zynqmp.h          |   4 +
>  6 files changed, 236 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
>  create mode 100644 drivers/fpga/zynqmp-fpga.c
>
> --
> 2.18.0
>

Re: [PATCH 2/3] dt-bindings: fpga: Add bindings for ZynqMP fpga driver

[Alan Tull]

On Fri, Oct 19, 2018 at 3:49 AM Nava kishore Manne
<nava.manne@xilinx.com> wrote:

Hi Nava,

Just some nits, below.

>
> Add documentation to describe Xilinx ZynqMP fpga driver
> bindings.
>
> Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> ---
> Changes for v1:
>                 Created a Seperate(New) DT binding file as
>                 suggested by Rob.
>
> Changes for RFC-V2:
>                 -Moved pcap node as a child to firwmare
>                  node as suggested by Rob.
>
>  .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt     | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
>
> diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> new file mode 100644
> index 000000000000..248ff0ee60a8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> @@ -0,0 +1,17 @@
> +--------------------------------------------------------------------------

Please get rid of all these '----' separators (in 4 places).

> +Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC controlled
> +using ZynqMP SoC firmware interface
> +--------------------------------------------------------------------------
> +For Bitstream configuration on ZynqMp Soc uses processor configuration
> +port(PCAP) to configure the programmable logic(PL) through PS by using
> +FW interface.
> +
> +Required properties:
> +- compatible: should contain "xlnx,zynqmp-pcap-fpga"
> +
> +-------
> +Example

Nit: please add a colon so 'Example:'
> +-------
> +       zynqmp_pcap: pcap {
> +               compatible = "xlnx,zynqmp-pcap-fpga";
> +       };
> --
> 2.18.0
>

Thanks,
Alan

Re: [PATCH 2/3] dt-bindings: fpga: Add bindings for ZynqMP fpga driver

[Alan Tull]

On Fri, Oct 19, 2018 at 3:49 AM Nava kishore Manne
<nava.manne@xilinx.com> wrote:

Hi Nava,

Just some nits, below.

>
> Add documentation to describe Xilinx ZynqMP fpga driver
> bindings.
>
> Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> ---
> Changes for v1:
>                 Created a Seperate(New) DT binding file as
>                 suggested by Rob.
>
> Changes for RFC-V2:
>                 -Moved pcap node as a child to firwmare
>                  node as suggested by Rob.
>
>  .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt     | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
>
> diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> new file mode 100644
> index 000000000000..248ff0ee60a8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> @@ -0,0 +1,17 @@
> +--------------------------------------------------------------------------

Please get rid of all these '----' separators (in 4 places).

> +Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC controlled
> +using ZynqMP SoC firmware interface
> +--------------------------------------------------------------------------
> +For Bitstream configuration on ZynqMp Soc uses processor configuration
> +port(PCAP) to configure the programmable logic(PL) through PS by using
> +FW interface.
> +
> +Required properties:
> +- compatible: should contain "xlnx,zynqmp-pcap-fpga"
> +
> +-------
> +Example

Nit: please add a colon so 'Example:'
> +-------
> +       zynqmp_pcap: pcap {
> +               compatible = "xlnx,zynqmp-pcap-fpga";
> +       };
> --
> 2.18.0
>

Thanks,
Alan

[PATCH 2/3] dt-bindings: fpga: Add bindings for ZynqMP fpga driver

[Alan Tull]

On Fri, Oct 19, 2018 at 3:49 AM Nava kishore Manne
<nava.manne@xilinx.com> wrote:

Hi Nava,

Just some nits, below.

>
> Add documentation to describe Xilinx ZynqMP fpga driver
> bindings.
>
> Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> ---
> Changes for v1:
>                 Created a Seperate(New) DT binding file as
>                 suggested by Rob.
>
> Changes for RFC-V2:
>                 -Moved pcap node as a child to firwmare
>                  node as suggested by Rob.
>
>  .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt     | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
>
> diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> new file mode 100644
> index 000000000000..248ff0ee60a8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> @@ -0,0 +1,17 @@
> +--------------------------------------------------------------------------

Please get rid of all these '----' separators (in 4 places).

> +Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC controlled
> +using ZynqMP SoC firmware interface
> +--------------------------------------------------------------------------
> +For Bitstream configuration on ZynqMp Soc uses processor configuration
> +port(PCAP) to configure the programmable logic(PL) through PS by using
> +FW interface.
> +
> +Required properties:
> +- compatible: should contain "xlnx,zynqmp-pcap-fpga"
> +
> +-------
> +Example

Nit: please add a colon so 'Example:'
> +-------
> +       zynqmp_pcap: pcap {
> +               compatible = "xlnx,zynqmp-pcap-fpga";
> +       };
> --
> 2.18.0
>

Thanks,
Alan

RE: [PATCH 0/3] Add Bitstream configuration support for ZynqMP

[Nava kishore Manne]

Hi Alan,

Thanks for the reply...
Please find my response inline.

> -----Original Message-----
> From: Alan Tull [mailto:atull@kernel.org]
> Sent: Monday, October 22, 2018 9:29 PM
> To: Nava kishore Manne <navam@xilinx.com>
> Cc: Moritz Fischer <mdf@kernel.org>; Rob Herring <robh+dt@kernel.org>;
> Mark Rutland <mark.rutland@arm.com>; Michal Simek <michals@xilinx.com>;
> Rajan Vaja <RAJANV@xilinx.com>; Jolly Shah <JOLLYS@xilinx.com>; linux-
> fpga@vger.kernel.org; open list:OPEN FIRMWARE AND FLATTENED DEVICE
> TREE BINDINGS <devicetree@vger.kernel.org>; moderated
> list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE <linux-arm-
> kernel@lists.infradead.org>; linux-kernel <linux-kernel@vger.kernel.org>;
> kishore m <chinnikishore369@gmail.com>
> Subject: Re: [PATCH 0/3] Add Bitstream configuration support for ZynqMP
> 
> On Fri, Oct 19, 2018 at 3:49 AM Nava kishore Manne
> <nava.manne@xilinx.com> wrote:
> 
> Hi Nava,
> 
> >
> > This series of patches are created On top of the below repo.
> > //git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git
> > BRANCH: next/drivers.
> 
> IIUC this is dependent on some patches that aren't released yet.
> Please make this explicit by specifying which patches this is dependent on in
> each future submission of new versions.  It will help so that I don't send these
> upstream prematurely and introduce build breaks.  Of course, we can keep
> reviewing!
> 

This driver depends on the below series of patches
https://lkml.org/lkml/2018/9/12/983 
Which is got integrated into the below upstream repo.
https://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git/tree/drivers/firmware/xilinx?h=for-next 
I hope arm maintainers will send the pull-request in soon to integrate these patches with main repo.
Will add the required info for the dependent patches in s-o-b section 

Regards,
Navakishore.

RE: [PATCH 0/3] Add Bitstream configuration support for ZynqMP

[Nava kishore Manne]

Hi Alan,

Thanks for the reply...
Please find my response inline.

> -----Original Message-----
> From: Alan Tull [mailto:atull@kernel.org]
> Sent: Monday, October 22, 2018 9:29 PM
> To: Nava kishore Manne <navam@xilinx.com>
> Cc: Moritz Fischer <mdf@kernel.org>; Rob Herring <robh+dt@kernel.org>;
> Mark Rutland <mark.rutland@arm.com>; Michal Simek <michals@xilinx.com>;
> Rajan Vaja <RAJANV@xilinx.com>; Jolly Shah <JOLLYS@xilinx.com>; linux-
> fpga@vger.kernel.org; open list:OPEN FIRMWARE AND FLATTENED DEVICE
> TREE BINDINGS <devicetree@vger.kernel.org>; moderated
> list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE <linux-arm-
> kernel@lists.infradead.org>; linux-kernel <linux-kernel@vger.kernel.org>;
> kishore m <chinnikishore369@gmail.com>
> Subject: Re: [PATCH 0/3] Add Bitstream configuration support for ZynqMP
> 
> On Fri, Oct 19, 2018 at 3:49 AM Nava kishore Manne
> <nava.manne@xilinx.com> wrote:
> 
> Hi Nava,
> 
> >
> > This series of patches are created On top of the below repo.
> > //git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git
> > BRANCH: next/drivers.
> 
> IIUC this is dependent on some patches that aren't released yet.
> Please make this explicit by specifying which patches this is dependent on in
> each future submission of new versions.  It will help so that I don't send these
> upstream prematurely and introduce build breaks.  Of course, we can keep
> reviewing!
> 

This driver depends on the below series of patches
https://lkml.org/lkml/2018/9/12/983 
Which is got integrated into the below upstream repo.
https://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git/tree/drivers/firmware/xilinx?h=for-next 
I hope arm maintainers will send the pull-request in soon to integrate these patches with main repo.
Will add the required info for the dependent patches in s-o-b section 

Regards,
Navakishore.

[PATCH 0/3] Add Bitstream configuration support for ZynqMP

[Nava kishore Manne]

Hi Alan,

Thanks for the reply...
Please find my response inline.

> -----Original Message-----
> From: Alan Tull [mailto:atull at kernel.org]
> Sent: Monday, October 22, 2018 9:29 PM
> To: Nava kishore Manne <navam@xilinx.com>
> Cc: Moritz Fischer <mdf@kernel.org>; Rob Herring <robh+dt@kernel.org>;
> Mark Rutland <mark.rutland@arm.com>; Michal Simek <michals@xilinx.com>;
> Rajan Vaja <RAJANV@xilinx.com>; Jolly Shah <JOLLYS@xilinx.com>; linux-
> fpga at vger.kernel.org; open list:OPEN FIRMWARE AND FLATTENED DEVICE
> TREE BINDINGS <devicetree@vger.kernel.org>; moderated
> list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE <linux-arm-
> kernel at lists.infradead.org>; linux-kernel <linux-kernel@vger.kernel.org>;
> kishore m <chinnikishore369@gmail.com>
> Subject: Re: [PATCH 0/3] Add Bitstream configuration support for ZynqMP
> 
> On Fri, Oct 19, 2018 at 3:49 AM Nava kishore Manne
> <nava.manne@xilinx.com> wrote:
> 
> Hi Nava,
> 
> >
> > This series of patches are created On top of the below repo.
> > //git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git
> > BRANCH: next/drivers.
> 
> IIUC this is dependent on some patches that aren't released yet.
> Please make this explicit by specifying which patches this is dependent on in
> each future submission of new versions.  It will help so that I don't send these
> upstream prematurely and introduce build breaks.  Of course, we can keep
> reviewing!
> 

This driver depends on the below series of patches
https://lkml.org/lkml/2018/9/12/983 
Which is got integrated into the below upstream repo.
https://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git/tree/drivers/firmware/xilinx?h=for-next 
I hope arm maintainers will send the pull-request in soon to integrate these patches with main repo.
Will add the required info for the dependent patches in s-o-b section 

Regards,
Navakishore.

RE: [PATCH 2/3] dt-bindings: fpga: Add bindings for ZynqMP fpga driver

[Nava kishore Manne]

Hi Alan,

Thanks for the quick response..
Please find my response inline.

> -----Original Message-----
> From: Alan Tull [mailto:atull@kernel.org]
> Sent: Monday, October 22, 2018 11:12 PM
> To: Nava kishore Manne <navam@xilinx.com>
> Cc: Moritz Fischer <mdf@kernel.org>; Rob Herring <robh+dt@kernel.org>;
> Mark Rutland <mark.rutland@arm.com>; Michal Simek <michals@xilinx.com>;
> Rajan Vaja <RAJANV@xilinx.com>; Jolly Shah <JOLLYS@xilinx.com>; linux-
> fpga@vger.kernel.org; open list:OPEN FIRMWARE AND FLATTENED DEVICE
> TREE BINDINGS <devicetree@vger.kernel.org>; moderated
> list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE <linux-arm-
> kernel@lists.infradead.org>; linux-kernel <linux-kernel@vger.kernel.org>;
> kishore m <chinnikishore369@gmail.com>
> Subject: Re: [PATCH 2/3] dt-bindings: fpga: Add bindings for ZynqMP fpga
> driver
> 
> On Fri, Oct 19, 2018 at 3:49 AM Nava kishore Manne
> <nava.manne@xilinx.com> wrote:
> 
> Hi Nava,
> 
> Just some nits, below.
> 
> >
> > Add documentation to describe Xilinx ZynqMP fpga driver bindings.
> >
> > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> > ---
> > Changes for v1:
> >                 Created a Seperate(New) DT binding file as
> >                 suggested by Rob.
> >
> > Changes for RFC-V2:
> >                 -Moved pcap node as a child to firwmare
> >                  node as suggested by Rob.
> >
> >  .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt     | 17 +++++++++++++++++
> >  1 file changed, 17 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> >
> > diff --git
> > a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> > b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> > new file mode 100644
> > index 000000000000..248ff0ee60a8
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> > @@ -0,0 +1,17 @@
> > +---------------------------------------------------------------------
> > +-----
> 
> Please get rid of all these '----' separators (in 4 places).
> 
Will fix in the next version.

> > +Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC
> > +controlled using ZynqMP SoC firmware interface
> > +---------------------------------------------------------------------
> > +----- For Bitstream configuration on ZynqMp Soc uses processor
> > +configuration
> > +port(PCAP) to configure the programmable logic(PL) through PS by
> > +using FW interface.
> > +
> > +Required properties:
> > +- compatible: should contain "xlnx,zynqmp-pcap-fpga"
> > +
> > +-------
> > +Example
> 
> Nit: please add a colon so 'Example:'
Will fix in the next version

Regards,
Navakishore.

RE: [PATCH 2/3] dt-bindings: fpga: Add bindings for ZynqMP fpga driver

[Nava kishore Manne]

Hi Alan,

Thanks for the quick response..
Please find my response inline.

> -----Original Message-----
> From: Alan Tull [mailto:atull@kernel.org]
> Sent: Monday, October 22, 2018 11:12 PM
> To: Nava kishore Manne <navam@xilinx.com>
> Cc: Moritz Fischer <mdf@kernel.org>; Rob Herring <robh+dt@kernel.org>;
> Mark Rutland <mark.rutland@arm.com>; Michal Simek <michals@xilinx.com>;
> Rajan Vaja <RAJANV@xilinx.com>; Jolly Shah <JOLLYS@xilinx.com>; linux-
> fpga@vger.kernel.org; open list:OPEN FIRMWARE AND FLATTENED DEVICE
> TREE BINDINGS <devicetree@vger.kernel.org>; moderated
> list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE <linux-arm-
> kernel@lists.infradead.org>; linux-kernel <linux-kernel@vger.kernel.org>;
> kishore m <chinnikishore369@gmail.com>
> Subject: Re: [PATCH 2/3] dt-bindings: fpga: Add bindings for ZynqMP fpga
> driver
> 
> On Fri, Oct 19, 2018 at 3:49 AM Nava kishore Manne
> <nava.manne@xilinx.com> wrote:
> 
> Hi Nava,
> 
> Just some nits, below.
> 
> >
> > Add documentation to describe Xilinx ZynqMP fpga driver bindings.
> >
> > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> > ---
> > Changes for v1:
> >                 Created a Seperate(New) DT binding file as
> >                 suggested by Rob.
> >
> > Changes for RFC-V2:
> >                 -Moved pcap node as a child to firwmare
> >                  node as suggested by Rob.
> >
> >  .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt     | 17 +++++++++++++++++
> >  1 file changed, 17 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> >
> > diff --git
> > a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> > b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> > new file mode 100644
> > index 000000000000..248ff0ee60a8
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> > @@ -0,0 +1,17 @@
> > +---------------------------------------------------------------------
> > +-----
> 
> Please get rid of all these '----' separators (in 4 places).
> 
Will fix in the next version.

> > +Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC
> > +controlled using ZynqMP SoC firmware interface
> > +---------------------------------------------------------------------
> > +----- For Bitstream configuration on ZynqMp Soc uses processor
> > +configuration
> > +port(PCAP) to configure the programmable logic(PL) through PS by
> > +using FW interface.
> > +
> > +Required properties:
> > +- compatible: should contain "xlnx,zynqmp-pcap-fpga"
> > +
> > +-------
> > +Example
> 
> Nit: please add a colon so 'Example:'
Will fix in the next version

Regards,
Navakishore.

[PATCH 2/3] dt-bindings: fpga: Add bindings for ZynqMP fpga driver

[Nava kishore Manne]

Hi Alan,

Thanks for the quick response..
Please find my response inline.

> -----Original Message-----
> From: Alan Tull [mailto:atull at kernel.org]
> Sent: Monday, October 22, 2018 11:12 PM
> To: Nava kishore Manne <navam@xilinx.com>
> Cc: Moritz Fischer <mdf@kernel.org>; Rob Herring <robh+dt@kernel.org>;
> Mark Rutland <mark.rutland@arm.com>; Michal Simek <michals@xilinx.com>;
> Rajan Vaja <RAJANV@xilinx.com>; Jolly Shah <JOLLYS@xilinx.com>; linux-
> fpga at vger.kernel.org; open list:OPEN FIRMWARE AND FLATTENED DEVICE
> TREE BINDINGS <devicetree@vger.kernel.org>; moderated
> list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE <linux-arm-
> kernel at lists.infradead.org>; linux-kernel <linux-kernel@vger.kernel.org>;
> kishore m <chinnikishore369@gmail.com>
> Subject: Re: [PATCH 2/3] dt-bindings: fpga: Add bindings for ZynqMP fpga
> driver
> 
> On Fri, Oct 19, 2018 at 3:49 AM Nava kishore Manne
> <nava.manne@xilinx.com> wrote:
> 
> Hi Nava,
> 
> Just some nits, below.
> 
> >
> > Add documentation to describe Xilinx ZynqMP fpga driver bindings.
> >
> > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> > ---
> > Changes for v1:
> >                 Created a Seperate(New) DT binding file as
> >                 suggested by Rob.
> >
> > Changes for RFC-V2:
> >                 -Moved pcap node as a child to firwmare
> >                  node as suggested by Rob.
> >
> >  .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt     | 17 +++++++++++++++++
> >  1 file changed, 17 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> >
> > diff --git
> > a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> > b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> > new file mode 100644
> > index 000000000000..248ff0ee60a8
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> > @@ -0,0 +1,17 @@
> > +---------------------------------------------------------------------
> > +-----
> 
> Please get rid of all these '----' separators (in 4 places).
> 
Will fix in the next version.

> > +Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC
> > +controlled using ZynqMP SoC firmware interface
> > +---------------------------------------------------------------------
> > +----- For Bitstream configuration on ZynqMp Soc uses processor
> > +configuration
> > +port(PCAP) to configure the programmable logic(PL) through PS by
> > +using FW interface.
> > +
> > +Required properties:
> > +- compatible: should contain "xlnx,zynqmp-pcap-fpga"
> > +
> > +-------
> > +Example
> 
> Nit: please add a colon so 'Example:'
Will fix in the next version

Regards,
Navakishore.