[Qemu-devel] [PATCH 0/7] riscv decodetree followup

[Richard Henderson <richard.henderson@linaro.org>]

The first patch is the promised change to argument sets to allow
them to be shared between two decoders.

Then I set about trying to use this... and ran into some other
interesting problems.  The first of which is that 

  bool trans_add(DecodeContext *ctx, struct arg_r *a, uint32_t insn);
  bool trans_add(DecodeContext *ctx, struct arg_r *a, uint16_t insn);

conflicts.

I think the best solution is to remove the insn argument to the
trans_* functions.  When this goes in for real, this will be
a big patch that touches lots of lines in target/arm and target/openrisc.
For now, I'm ignoring that and only building riscv{32,64}-linux-user.

Second, it occured to me that if we smoosh several files together
at build time, we don't have to play silly games with trying to
decode for riscv32 and riscv64 at the same time.  The last patch is,
I think, a big improvement in that.

Full tree at https://github.com/rth7680/qemu.git riscv-dt-rth.


r~


Richard Henderson (7):
  decodetree: Add !extern flag to argument sets
  decodetree: Remove "insn" argument from trans_* expanders
  target/riscv: Update for decodetree insn argument change
  target/riscv: Rename some argument sets in insn32.decode
  target/riscv: Convert @cs_2 insns to share translation functions
  target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
  target/riscv: Splice decodetree inputs for riscv32 vs riscv64

 .../riscv/insn_trans/trans_privileged.inc.c   |  19 +-
 target/riscv/insn_trans/trans_rva.inc.c       |  90 ++------
 target/riscv/insn_trans/trans_rvc.inc.c       | 215 ++++--------------
 target/riscv/insn_trans/trans_rvd.inc.c       |  90 +++-----
 target/riscv/insn_trans/trans_rvf.inc.c       |  78 +++----
 target/riscv/insn_trans/trans_rvi.inc.c       | 165 ++++++--------
 target/riscv/insn_trans/trans_rvm.inc.c       |  48 ++--
 target/riscv/translate.c                      |  30 ++-
 scripts/decodetree.py                         |  39 ++--
 target/riscv/Makefile.objs                    |  23 +-
 target/riscv/insn16-32.decode                 |  31 +++
 target/riscv/insn16-64.decode                 |  33 +++
 target/riscv/insn16.decode                    |  55 ++---
 target/riscv/insn32.decode                    |  68 +-----
 target/riscv/insn64.decode                    |  71 ++++++
 15 files changed, 450 insertions(+), 605 deletions(-)
 create mode 100644 target/riscv/insn16-32.decode
 create mode 100644 target/riscv/insn16-64.decode
 create mode 100644 target/riscv/insn64.decode

-- 
2.17.2