* [RFC 1/3] drm/i915: Rename IS_GEN to IS_GEN_RANGE.
@ 2018-10-23 23:36 Rodrigo Vivi
2018-10-23 23:36 ` [RFC 2/3] drm/i915: Prefer IS_GEN<n> check with bitmask Rodrigo Vivi
` (5 more replies)
0 siblings, 6 replies; 18+ messages in thread
From: Rodrigo Vivi @ 2018-10-23 23:36 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
RANGE makes it longer, but clear.
Diff generated with:
sed 's/IS_GEN(/IS_GEN_RANGE(/g' drivers/gpu/drm/i915/*.{c,h} -i
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_perf.c | 4 ++--
drivers/gpu/drm/i915/intel_bios.c | 2 +-
drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/intel_fbc.c | 2 +-
drivers/gpu/drm/i915/intel_hangcheck.c | 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++----
drivers/gpu/drm/i915/intel_uncore.c | 12 ++++++------
9 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 5b37d5f8e132..3deab30388f2 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2919,7 +2919,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
if (IS_BROXTON(dev_priv)) {
seq_printf(m, "DC3 -> DC5 count: %d\n",
I915_READ(BXT_CSR_DC3_DC5_COUNT));
- } else if (IS_GEN(dev_priv, 9, 11)) {
+ } else if (IS_GEN_RANGE(dev_priv, 9, 11)) {
seq_printf(m, "DC3 -> DC5 count: %d\n",
I915_READ(SKL_CSR_DC3_DC5_COUNT));
seq_printf(m, "DC5 -> DC6 count: %d\n",
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3017ef037fed..f766bb1e873b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2387,7 +2387,7 @@ intel_info(const struct drm_i915_private *dev_priv)
*
* Use GEN_FOREVER for unbound start and or end.
*/
-#define IS_GEN(dev_priv, s, e) \
+#define IS_GEN_RANGE(dev_priv, s, e) \
(!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
/*
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 664b96bb65a3..0888b6e6080f 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1795,7 +1795,7 @@ static int gen8_enable_metric_set(struct drm_i915_private *dev_priv,
* be read back from automatically triggered reports, as part of the
* RPT_ID field.
*/
- if (IS_GEN(dev_priv, 9, 11)) {
+ if (IS_GEN_RANGE(dev_priv, 9, 11)) {
I915_WRITE(GEN8_OA_DEBUG,
_MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
GEN9_OA_DEBUG_INCLUDE_CLK_RATIO));
@@ -3439,7 +3439,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16);
}
- } else if (IS_GEN(dev_priv, 10, 11)) {
+ } else if (IS_GEN_RANGE(dev_priv, 10, 11)) {
dev_priv->perf.oa.ops.is_valid_b_counter_reg =
gen7_is_valid_b_counter_addr;
dev_priv->perf.oa.ops.is_valid_mux_reg =
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 1faa494e2bc9..43cf0b026143 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -446,7 +446,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, u8 bdb_version)
* Only parse SDVO mappings on gens that could have SDVO. This isn't
* accurate and doesn't have to be, as long as it's not too strict.
*/
- if (!IS_GEN(dev_priv, 3, 7)) {
+ if (!IS_GEN_RANGE(dev_priv, 3, 7)) {
DRM_DEBUG_KMS("Skipping SDVO device mapping\n");
return;
}
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 8bfab22068a3..65f6c9bc10cf 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1286,7 +1286,7 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine,
&engine->execlists;
u64 addr;
- if (engine->id == RCS && IS_GEN(dev_priv, 4, 7))
+ if (engine->id == RCS && IS_GEN_RANGE(dev_priv, 4, 7))
drm_printf(m, "\tCCID: 0x%08x\n", I915_READ(CCID));
drm_printf(m, "\tRING_START: 0x%08x\n",
I915_READ(RING_START(engine->mmio_base)));
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index e3cfc3c176e7..c90954cdfb15 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -784,7 +784,7 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
* having a Y offset that isn't divisible by 4 causes FIFO underrun
* and screen flicker.
*/
- if (IS_GEN(dev_priv, 9, 10) &&
+ if (IS_GEN_RANGE(dev_priv, 9, 10) &&
(fbc->state_cache.plane.adjusted_y & 3)) {
fbc->no_fbc_reason = "plane Y offset is misaligned";
return false;
diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c
index e26d05a46451..41921a843d42 100644
--- a/drivers/gpu/drm/i915/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/intel_hangcheck.c
@@ -252,7 +252,7 @@ engine_stuck(struct intel_engine_cs *engine, u64 acthd)
return ENGINE_WAIT_KICK;
}
- if (IS_GEN(dev_priv, 6, 7) && tmp & RING_WAIT_SEMAPHORE) {
+ if (IS_GEN_RANGE(dev_priv, 6, 7) && tmp & RING_WAIT_SEMAPHORE) {
switch (semaphore_passed(engine)) {
default:
return ENGINE_DEAD;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index b8a7a014d46d..608e5c65b655 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -407,7 +407,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
POSTING_READ(mmio);
/* Flush the TLB for this page */
- if (IS_GEN(dev_priv, 6, 7)) {
+ if (IS_GEN_RANGE(dev_priv, 6, 7)) {
i915_reg_t reg = RING_INSTPM(engine->mmio_base);
/* ring should be idle before issuing a sync flush*/
@@ -629,7 +629,7 @@ static int init_render_ring(struct intel_engine_cs *engine)
intel_whitelist_workarounds_apply(engine);
/* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
- if (IS_GEN(dev_priv, 4, 6))
+ if (IS_GEN_RANGE(dev_priv, 4, 6))
I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
/* We need to disable the AsyncFlip performance optimisations in order
@@ -638,7 +638,7 @@ static int init_render_ring(struct intel_engine_cs *engine)
*
* WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
*/
- if (IS_GEN(dev_priv, 6, 7))
+ if (IS_GEN_RANGE(dev_priv, 6, 7))
I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
/* Required for the hardware to program scanline values for waiting */
@@ -663,7 +663,7 @@ static int init_render_ring(struct intel_engine_cs *engine)
_MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
}
- if (IS_GEN(dev_priv, 6, 7))
+ if (IS_GEN_RANGE(dev_priv, 6, 7))
I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
if (INTEL_GEN(dev_priv) >= 6)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 9289515108c3..631b4165fe00 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1567,13 +1567,13 @@ void intel_uncore_init(struct drm_i915_private *dev_priv)
dev_priv->uncore.pmic_bus_access_nb.notifier_call =
i915_pmic_bus_access_notifier;
- if (IS_GEN(dev_priv, 2, 4) || intel_vgpu_active(dev_priv)) {
+ if (IS_GEN_RANGE(dev_priv, 2, 4) || intel_vgpu_active(dev_priv)) {
ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen2);
ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen2);
} else if (IS_GEN5(dev_priv)) {
ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen5);
ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen5);
- } else if (IS_GEN(dev_priv, 6, 7)) {
+ } else if (IS_GEN_RANGE(dev_priv, 6, 7)) {
ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen6);
if (IS_VALLEYVIEW(dev_priv)) {
@@ -1592,7 +1592,7 @@ void intel_uncore_init(struct drm_i915_private *dev_priv)
ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen8);
ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen6);
}
- } else if (IS_GEN(dev_priv, 9, 10)) {
+ } else if (IS_GEN_RANGE(dev_priv, 9, 10)) {
ASSIGN_FW_DOMAINS_TABLE(__gen9_fw_ranges);
ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, fwtable);
ASSIGN_READ_MMIO_VFUNCS(dev_priv, fwtable);
@@ -2321,7 +2321,7 @@ intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv,
} else if (INTEL_GEN(dev_priv) >= 6) {
fw_domains = __gen6_reg_read_fw_domains(offset);
} else {
- WARN_ON(!IS_GEN(dev_priv, 2, 5));
+ WARN_ON(!IS_GEN_RANGE(dev_priv, 2, 5));
fw_domains = 0;
}
@@ -2343,10 +2343,10 @@ intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv,
fw_domains = __fwtable_reg_write_fw_domains(offset);
} else if (IS_GEN8(dev_priv)) {
fw_domains = __gen8_reg_write_fw_domains(offset);
- } else if (IS_GEN(dev_priv, 6, 7)) {
+ } else if (IS_GEN_RANGE(dev_priv, 6, 7)) {
fw_domains = FORCEWAKE_RENDER;
} else {
- WARN_ON(!IS_GEN(dev_priv, 2, 5));
+ WARN_ON(!IS_GEN_RANGE(dev_priv, 2, 5));
fw_domains = 0;
}
--
2.19.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* [RFC 2/3] drm/i915: Prefer IS_GEN<n> check with bitmask.
2018-10-23 23:36 [RFC 1/3] drm/i915: Rename IS_GEN to IS_GEN_RANGE Rodrigo Vivi
@ 2018-10-23 23:36 ` Rodrigo Vivi
2018-10-24 10:22 ` Ville Syrjälä
2018-10-23 23:36 ` [RFC 3/3] drm/i915: Kill GEN_FOREVER Rodrigo Vivi
` (4 subsequent siblings)
5 siblings, 1 reply; 18+ messages in thread
From: Rodrigo Vivi @ 2018-10-23 23:36 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
Whenever possible we should stick with IS_GEN<n> checks.
Bitmaks has been introduced on commit ae7617f0ef18 ("drm/i915:
Allow optimized platform checks") for efficiency.
Let's stick with it whenever possible.
This patch was generated with coccinelle:
spatch -sp_file is_gen.cocci *{c,h} --in-place
is_gen.cocci:
@gen2@ expression e; @@
-INTEL_GEN(e) == 2
+IS_GEN2(e)
@gen3@ expression e; @@
-INTEL_GEN(e) == 3
+IS_GEN3(e)
@gen4@ expression e; @@
-INTEL_GEN(e) == 4
+IS_GEN4(e)
@gen5@ expression e; @@
-INTEL_GEN(e) == 5
+IS_GEN5(e)
@gen6@ expression e; @@
-INTEL_GEN(e) == 6
+IS_GEN6(e)
@gen7@ expression e; @@
-INTEL_GEN(e) == 7
+IS_GEN7(e)
@gen8@ expression e; @@
-INTEL_GEN(e) == 8
+IS_GEN8(e)
@gen9@ expression e; @@
-INTEL_GEN(e) == 9
+IS_GEN9(e)
@gen10@ expression e; @@
-INTEL_GEN(e) == 10
+IS_GEN10(e)
@gen11@ expression e; @@
-INTEL_GEN(e) == 11
+IS_GEN11(e)
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/intel_atomic.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 6 +++---
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/intel_dp.c | 2 +-
drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/intel_fbc.c | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 4 ++--
drivers/gpu/drm/i915/intel_psr.c | 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.h | 4 ++--
drivers/gpu/drm/i915/intel_sprite.c | 2 +-
11 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index baac35f698f9..d755e84fed07 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1329,7 +1329,7 @@ intel_get_dram_info(struct drm_i915_private *dev_priv)
/* Need to calculate bandwidth only for Gen9 */
if (IS_BROXTON(dev_priv))
ret = bxt_get_dram_info(dev_priv);
- else if (INTEL_GEN(dev_priv) == 9)
+ else if (IS_GEN9(dev_priv))
ret = skl_get_dram_info(dev_priv);
else
ret = skl_dram_get_channels_info(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index 760758ad21c1..3526f6d9c1ad 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -232,7 +232,7 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta
if (plane_state && plane_state->base.fb &&
plane_state->base.fb->format->is_yuv &&
plane_state->base.fb->format->num_planes > 1) {
- if (INTEL_GEN(dev_priv) == 9 &&
+ if (IS_GEN9(dev_priv) &&
!IS_GEMINILAKE(dev_priv))
mode = SKL_PS_SCALER_MODE_NV12;
else
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 03df4e33763d..561ad0d4a53d 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -744,7 +744,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
if (INTEL_GEN(dev_priv) >= 10) {
for_each_pipe(dev_priv, pipe)
info->num_scalers[pipe] = 2;
- } else if (INTEL_GEN(dev_priv) == 9) {
+ } else if (IS_GEN9(dev_priv)) {
info->num_scalers[PIPE_A] = 2;
info->num_scalers[PIPE_B] = 2;
info->num_scalers[PIPE_C] = 1;
@@ -843,9 +843,9 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
cherryview_sseu_info_init(dev_priv);
else if (IS_BROADWELL(dev_priv))
broadwell_sseu_info_init(dev_priv);
- else if (INTEL_GEN(dev_priv) == 9)
+ else if (IS_GEN9(dev_priv))
gen9_sseu_info_init(dev_priv);
- else if (INTEL_GEN(dev_priv) == 10)
+ else if (IS_GEN10(dev_priv))
gen10_sseu_info_init(dev_priv);
else if (INTEL_GEN(dev_priv) >= 11)
gen11_sseu_info_init(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index fc7e3b0bd95c..a6869c547f3c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5268,7 +5268,7 @@ static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
return false;
- if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
+ if ((IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) ||
IS_CANNONLAKE(dev_priv))
return true;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8c38efef77a1..761447c456c7 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -455,7 +455,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
if (INTEL_GEN(dev_priv) >= 10) {
source_rates = cnl_rates;
size = ARRAY_SIZE(cnl_rates);
- if (INTEL_GEN(dev_priv) == 10)
+ if (IS_GEN10(dev_priv))
max_rate = cnl_max_source_rate(intel_dp);
else
max_rate = icl_max_source_rate(intel_dp);
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 65f6c9bc10cf..a4b1d82c89da 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -812,7 +812,7 @@ u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)
u32 slice = fls(sseu->slice_mask);
u32 subslice = fls(sseu->subslice_mask[slice]);
- if (INTEL_GEN(dev_priv) == 10)
+ if (IS_GEN10(dev_priv))
mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
GEN8_MCR_SUBSLICE(subslice);
else if (INTEL_GEN(dev_priv) >= 11)
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index c90954cdfb15..96f70d896c10 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -84,7 +84,7 @@ static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
int lines;
intel_fbc_get_plane_source_size(cache, NULL, &lines);
- if (INTEL_GEN(dev_priv) == 7)
+ if (IS_GEN7(dev_priv))
lines = min(lines, 2048);
else if (INTEL_GEN(dev_priv) >= 8)
lines = min(lines, 2560);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 67a4d0735291..3793866a9ee7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4676,13 +4676,13 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
selected_result = method2;
} else if (ddb_allocation >=
fixed16_to_u32_round_up(wp->plane_blocks_per_line)) {
- if (INTEL_GEN(dev_priv) == 9 &&
+ if (IS_GEN9(dev_priv) &&
!IS_GEMINILAKE(dev_priv))
selected_result = min_fixed16(method1, method2);
else
selected_result = method2;
} else if (latency >= wp->linetime_us) {
- if (INTEL_GEN(dev_priv) == 9 &&
+ if (IS_GEN9(dev_priv) &&
!IS_GEMINILAKE(dev_priv))
selected_result = min_fixed16(method1, method2);
else
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 423cdf84059c..bc2d88313ed0 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -574,7 +574,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
if (dev_priv->psr.psr2_enabled) {
u32 chicken = I915_READ(CHICKEN_TRANS(cpu_transcoder));
- if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv))
+ if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv))
chicken |= (PSR2_VSC_ENABLE_PROG_HEADER
| PSR2_ADD_VERTICAL_LINE_COUNT);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index f6ec48a75a69..d3a08d0f02fe 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -93,11 +93,11 @@ hangcheck_action_to_str(const enum intel_engine_hangcheck_action a)
#define I915_MAX_SUBSLICES 8
#define instdone_slice_mask(dev_priv__) \
- (INTEL_GEN(dev_priv__) == 7 ? \
+ (IS_GEN7(dev_priv__) ? \
1 : INTEL_INFO(dev_priv__)->sseu.slice_mask)
#define instdone_subslice_mask(dev_priv__) \
- (INTEL_GEN(dev_priv__) == 7 ? \
+ (IS_GEN7(dev_priv__) ? \
1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask[0])
#define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 7cd59eee5cad..4c9f0b7138b3 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1798,7 +1798,7 @@ static bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
return false;
- if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C)
+ if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C)
return false;
if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0)
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [RFC 3/3] drm/i915: Kill GEN_FOREVER
2018-10-23 23:36 [RFC 1/3] drm/i915: Rename IS_GEN to IS_GEN_RANGE Rodrigo Vivi
2018-10-23 23:36 ` [RFC 2/3] drm/i915: Prefer IS_GEN<n> check with bitmask Rodrigo Vivi
@ 2018-10-23 23:36 ` Rodrigo Vivi
2018-10-24 12:31 ` Daniel Vetter
2018-10-23 23:50 ` ✗ Fi.CI.SPARSE: warning for series starting with [RFC,1/3] drm/i915: Rename IS_GEN to IS_GEN_RANGE Patchwork
` (3 subsequent siblings)
5 siblings, 1 reply; 18+ messages in thread
From: Rodrigo Vivi @ 2018-10-23 23:36 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
commit ac657f6461e5 ("drm/i915: Introduce IS_GEN macro") introduced
GEN_FOREVER that was never used.
My first attempt was to rename it to FOREVER since GEN is
already part of the macro. Then I used coccinelle to change all
-INTEL_GEN(e1) >= e2
+INTEL_GEN_RANGE(e1, e2, FOREVER)
-INTEL_GEN(e1) <= e2
+INTEL_GEN_RANGE(e1, 0, e2)
and I liked it.
However I didn't like very much the remaining
INTEL_GEN(dev_priv) < n
and:
INTEL_GEN(e1) < n
INTEL_GEN_RANGE(e1, 0, n - 1)
didn't make much sense either.
So INTEL_GEN use for > or < seems a better unified way for unlimited
bounds. So, no reason to keep GEN_FOREVER here.
Let's kill before someone start using it.
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f766bb1e873b..24f17e711772 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2373,14 +2373,10 @@ intel_info(const struct drm_i915_private *dev_priv)
#define REVID_FOREVER 0xff
#define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
-#define GEN_FOREVER (0)
-
#define INTEL_GEN_MASK(s, e) ( \
BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
- GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \
- (s) != GEN_FOREVER ? (s) - 1 : 0) \
-)
+ GENMASK((e) - 1, (s) - 1))
/*
* Returns true if Gen is in inclusive range [Start, End].
--
2.19.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread
* ✗ Fi.CI.SPARSE: warning for series starting with [RFC,1/3] drm/i915: Rename IS_GEN to IS_GEN_RANGE.
2018-10-23 23:36 [RFC 1/3] drm/i915: Rename IS_GEN to IS_GEN_RANGE Rodrigo Vivi
2018-10-23 23:36 ` [RFC 2/3] drm/i915: Prefer IS_GEN<n> check with bitmask Rodrigo Vivi
2018-10-23 23:36 ` [RFC 3/3] drm/i915: Kill GEN_FOREVER Rodrigo Vivi
@ 2018-10-23 23:50 ` Patchwork
2018-10-24 0:07 ` ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
5 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2018-10-23 23:50 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: series starting with [RFC,1/3] drm/i915: Rename IS_GEN to IS_GEN_RANGE.
URL : https://patchwork.freedesktop.org/series/51415/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Rename IS_GEN to IS_GEN_RANGE.
Okay!
Commit: drm/i915: Prefer IS_GEN<n> check with bitmask.
-O:drivers/gpu/drm/i915/intel_fbc.c:88:25: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_fbc.c:90:25: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_fbc.c:88:25: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_fbc.c:90:25: warning: expression using sizeof(void)
Commit: drm/i915: Kill GEN_FOREVER
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3708:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3704:16: warning: expression using sizeof(void)
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [RFC,1/3] drm/i915: Rename IS_GEN to IS_GEN_RANGE.
2018-10-23 23:36 [RFC 1/3] drm/i915: Rename IS_GEN to IS_GEN_RANGE Rodrigo Vivi
` (2 preceding siblings ...)
2018-10-23 23:50 ` ✗ Fi.CI.SPARSE: warning for series starting with [RFC,1/3] drm/i915: Rename IS_GEN to IS_GEN_RANGE Patchwork
@ 2018-10-24 0:07 ` Patchwork
2018-10-24 4:50 ` ✓ Fi.CI.IGT: " Patchwork
2018-10-29 10:19 ` [RFC 1/3] " Jani Nikula
5 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2018-10-24 0:07 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: series starting with [RFC,1/3] drm/i915: Rename IS_GEN to IS_GEN_RANGE.
URL : https://patchwork.freedesktop.org/series/51415/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5023 -> Patchwork_10555 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/51415/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_10555 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@amdgpu/amd_basic@cs-compute:
fi-kbl-8809g: NOTRUN -> FAIL (fdo#108094)
igt@amdgpu/amd_prime@amd-to-i915:
fi-kbl-8809g: NOTRUN -> FAIL (fdo#107341)
igt@drv_module_reload@basic-reload:
fi-blb-e6850: NOTRUN -> INCOMPLETE (fdo#107718)
igt@gem_exec_suspend@basic-s3:
fi-icl-u: NOTRUN -> INCOMPLETE (fdo#107713)
igt@kms_flip@basic-flip-vs-modeset:
fi-hsw-4770r: PASS -> DMESG-WARN (fdo#105602)
igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
fi-byt-clapper: PASS -> FAIL (fdo#107362, fdo#103191)
==== Possible fixes ====
igt@drv_selftest@live_execlists:
fi-apl-guc: INCOMPLETE (fdo#106693) -> PASS
igt@gem_ctx_switch@basic-default:
fi-icl-u: DMESG-FAIL -> PASS
igt@gem_exec_suspend@basic-s3:
fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS
igt@kms_frontbuffer_tracking@basic:
fi-byt-clapper: FAIL (fdo#103167) -> PASS
igt@kms_pipe_crc_basic@read-crc-pipe-a:
fi-byt-clapper: FAIL (fdo#107362) -> PASS
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
fdo#106693 https://bugs.freedesktop.org/show_bug.cgi?id=106693
fdo#107341 https://bugs.freedesktop.org/show_bug.cgi?id=107341
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107713 https://bugs.freedesktop.org/show_bug.cgi?id=107713
fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
fdo#108094 https://bugs.freedesktop.org/show_bug.cgi?id=108094
== Participating hosts (49 -> 45) ==
Additional (1): fi-kbl-7560u
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600
== Build changes ==
* Linux: CI_DRM_5023 -> Patchwork_10555
CI_DRM_5023: 166bc98d7b77005943ab670506f164783cdc3f56 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4688: fa6dbf8c048961356fd642df047cb58ab49309b2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10555: 3d4a4c3ccf413ac2264fdfd0507ba69f69cb26a0 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
3d4a4c3ccf41 drm/i915: Kill GEN_FOREVER
553196a3b87f drm/i915: Prefer IS_GEN<n> check with bitmask.
f179a555c700 drm/i915: Rename IS_GEN to IS_GEN_RANGE.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10555/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [RFC,1/3] drm/i915: Rename IS_GEN to IS_GEN_RANGE.
2018-10-23 23:36 [RFC 1/3] drm/i915: Rename IS_GEN to IS_GEN_RANGE Rodrigo Vivi
` (3 preceding siblings ...)
2018-10-24 0:07 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-10-24 4:50 ` Patchwork
2018-10-29 10:19 ` [RFC 1/3] " Jani Nikula
5 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2018-10-24 4:50 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: series starting with [RFC,1/3] drm/i915: Rename IS_GEN to IS_GEN_RANGE.
URL : https://patchwork.freedesktop.org/series/51415/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5023_full -> Patchwork_10555_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_10555_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10555_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10555_full:
=== IGT changes ===
==== Warnings ====
igt@pm_rc6_residency@rc6-accuracy:
shard-snb: PASS -> SKIP
== Known issues ==
Here are the changes found in Patchwork_10555_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@gem_ppgtt@blt-vs-render-ctxn:
shard-kbl: PASS -> INCOMPLETE (fdo#103665, fdo#106023)
igt@kms_busy@extended-modeset-hang-newfb-render-b:
shard-kbl: NOTRUN -> DMESG-WARN (fdo#107956)
igt@kms_busy@extended-pageflip-hang-newfb-render-b:
shard-apl: NOTRUN -> DMESG-WARN (fdo#107956)
igt@kms_color@pipe-b-degamma:
shard-apl: PASS -> FAIL (fdo#104782)
igt@kms_cursor_crc@cursor-256x85-onscreen:
shard-apl: NOTRUN -> FAIL (fdo#103232)
shard-glk: PASS -> FAIL (fdo#103232) +2
igt@kms_cursor_crc@cursor-256x85-random:
shard-apl: PASS -> FAIL (fdo#103232) +4
igt@kms_cursor_crc@cursor-64x64-suspend:
shard-apl: NOTRUN -> FAIL (fdo#103191, fdo#103232)
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
shard-apl: PASS -> FAIL (fdo#103167) +2
igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen:
shard-glk: PASS -> FAIL (fdo#103167) +1
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
shard-skl: PASS -> INCOMPLETE (fdo#104108, fdo#107773)
igt@kms_plane@plane-position-covered-pipe-c-planes:
shard-apl: PASS -> FAIL (fdo#103166)
shard-glk: PASS -> FAIL (fdo#103166) +1
igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
shard-skl: NOTRUN -> FAIL (fdo#108146)
igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
shard-apl: PASS -> FAIL (fdo#108145)
igt@kms_setmode@basic:
shard-apl: PASS -> FAIL (fdo#99912)
shard-kbl: NOTRUN -> FAIL (fdo#99912)
shard-snb: NOTRUN -> FAIL (fdo#99912)
igt@perf@polling:
shard-hsw: PASS -> FAIL (fdo#102252)
==== Possible fixes ====
igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
shard-glk: FAIL (fdo#108145) -> PASS +1
igt@kms_cursor_crc@cursor-256x256-onscreen:
shard-glk: FAIL (fdo#103232) -> PASS
igt@kms_cursor_crc@cursor-size-change:
shard-apl: FAIL (fdo#103232) -> PASS
igt@kms_cursor_legacy@cursora-vs-flipa-toggle:
shard-glk: DMESG-WARN (fdo#106538, fdo#105763) -> PASS +1
igt@kms_flip@busy-flip-interruptible:
shard-skl: FAIL (fdo#103257) -> PASS
igt@kms_flip@flip-vs-expired-vblank-interruptible:
shard-skl: FAIL (fdo#105363) -> PASS
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc:
shard-apl: FAIL (fdo#103167) -> PASS
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
shard-glk: FAIL (fdo#103167) -> PASS
igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
shard-skl: INCOMPLETE (fdo#104108, fdo#107773) -> PASS
igt@kms_plane@plane-position-covered-pipe-a-planes:
shard-apl: FAIL (fdo#103166) -> PASS
igt@kms_rotation_crc@sprite-rotation-180:
shard-apl: INCOMPLETE (fdo#103927) -> PASS
igt@kms_vblank@pipe-a-ts-continuation-suspend:
shard-kbl: INCOMPLETE (fdo#103665) -> PASS +1
igt@perf@short-reads:
shard-skl: FAIL (fdo#103183) -> PASS
igt@pm_rpm@legacy-planes-dpms:
shard-skl: INCOMPLETE (fdo#105959, fdo#107807) -> PASS
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103183 https://bugs.freedesktop.org/show_bug.cgi?id=103183
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
fdo#103257 https://bugs.freedesktop.org/show_bug.cgi?id=103257
fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782
fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763
fdo#105959 https://bugs.freedesktop.org/show_bug.cgi?id=105959
fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023
fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538
fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773
fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807
fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
fdo#108146 https://bugs.freedesktop.org/show_bug.cgi?id=108146
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
== Participating hosts (6 -> 6) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_5023 -> Patchwork_10555
CI_DRM_5023: 166bc98d7b77005943ab670506f164783cdc3f56 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4688: fa6dbf8c048961356fd642df047cb58ab49309b2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10555: 3d4a4c3ccf413ac2264fdfd0507ba69f69cb26a0 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10555/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [RFC 2/3] drm/i915: Prefer IS_GEN<n> check with bitmask.
2018-10-23 23:36 ` [RFC 2/3] drm/i915: Prefer IS_GEN<n> check with bitmask Rodrigo Vivi
@ 2018-10-24 10:22 ` Ville Syrjälä
2018-10-24 14:54 ` Julia Lawall
2018-10-24 23:41 ` Rodrigo Vivi
0 siblings, 2 replies; 18+ messages in thread
From: Ville Syrjälä @ 2018-10-24 10:22 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: Julia Lawall, intel-gfx
On Tue, Oct 23, 2018 at 04:36:19PM -0700, Rodrigo Vivi wrote:
> Whenever possible we should stick with IS_GEN<n> checks.
>
> Bitmaks has been introduced on commit ae7617f0ef18 ("drm/i915:
> Allow optimized platform checks") for efficiency.
>
> Let's stick with it whenever possible.
>
> This patch was generated with coccinelle:
>
> spatch -sp_file is_gen.cocci *{c,h} --in-place
>
> is_gen.cocci:
> @gen2@ expression e; @@
> -INTEL_GEN(e) == 2
> +IS_GEN2(e)
> @gen3@ expression e; @@
> -INTEL_GEN(e) == 3
> +IS_GEN3(e)
> @gen4@ expression e; @@
> -INTEL_GEN(e) == 4
> +IS_GEN4(e)
> @gen5@ expression e; @@
> -INTEL_GEN(e) == 5
> +IS_GEN5(e)
> @gen6@ expression e; @@
> -INTEL_GEN(e) == 6
> +IS_GEN6(e)
> @gen7@ expression e; @@
> -INTEL_GEN(e) == 7
> +IS_GEN7(e)
> @gen8@ expression e; @@
> -INTEL_GEN(e) == 8
> +IS_GEN8(e)
> @gen9@ expression e; @@
> -INTEL_GEN(e) == 9
> +IS_GEN9(e)
> @gen10@ expression e; @@
> -INTEL_GEN(e) == 10
> +IS_GEN10(e)
> @gen11@ expression e; @@
> -INTEL_GEN(e) == 11
> +IS_GEN11(e)
Slightly less repetitive version. Sadly not super neat on
account of having to use the python stuff.
@find@
identifier old =~ "^INTEL_GEN$";
expression exp;
constant gen;
@@
old(exp) == gen
@script:python rename@
old << find.old;
gen << find.gen;
new;
@@
def do_rename(old, gen):
return "IS_GEN" + gen
coccinelle.new = cocci.make_ident(do_rename(old, gen))
print coccinelle.new
@@
identifier find.old;
expression find.exp;
constant find.gen;
identifier rename.new;
@@
- old(exp) == gen
+ new(exp)
I wish it would look something more like this:
@@
identifier old =~ "^INTEL_GEN$";
expression exp;
constant gen;
fresh identifier new = "IS_GEN" ## gen;
@@
- old(exp) == gen
+ new(exp)
But coccinelle doesn't seem to accept the constant in the fresh
identifier thing.
Patch looks fine anyways
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 2 +-
> drivers/gpu/drm/i915/intel_atomic.c | 2 +-
> drivers/gpu/drm/i915/intel_device_info.c | 6 +++---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> drivers/gpu/drm/i915/intel_dp.c | 2 +-
> drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/intel_fbc.c | 2 +-
> drivers/gpu/drm/i915/intel_pm.c | 4 ++--
> drivers/gpu/drm/i915/intel_psr.c | 2 +-
> drivers/gpu/drm/i915/intel_ringbuffer.h | 4 ++--
> drivers/gpu/drm/i915/intel_sprite.c | 2 +-
> 11 files changed, 15 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index baac35f698f9..d755e84fed07 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1329,7 +1329,7 @@ intel_get_dram_info(struct drm_i915_private *dev_priv)
> /* Need to calculate bandwidth only for Gen9 */
> if (IS_BROXTON(dev_priv))
> ret = bxt_get_dram_info(dev_priv);
> - else if (INTEL_GEN(dev_priv) == 9)
> + else if (IS_GEN9(dev_priv))
> ret = skl_get_dram_info(dev_priv);
> else
> ret = skl_dram_get_channels_info(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
> index 760758ad21c1..3526f6d9c1ad 100644
> --- a/drivers/gpu/drm/i915/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/intel_atomic.c
> @@ -232,7 +232,7 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta
> if (plane_state && plane_state->base.fb &&
> plane_state->base.fb->format->is_yuv &&
> plane_state->base.fb->format->num_planes > 1) {
> - if (INTEL_GEN(dev_priv) == 9 &&
> + if (IS_GEN9(dev_priv) &&
> !IS_GEMINILAKE(dev_priv))
> mode = SKL_PS_SCALER_MODE_NV12;
> else
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 03df4e33763d..561ad0d4a53d 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -744,7 +744,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
> if (INTEL_GEN(dev_priv) >= 10) {
> for_each_pipe(dev_priv, pipe)
> info->num_scalers[pipe] = 2;
> - } else if (INTEL_GEN(dev_priv) == 9) {
> + } else if (IS_GEN9(dev_priv)) {
> info->num_scalers[PIPE_A] = 2;
> info->num_scalers[PIPE_B] = 2;
> info->num_scalers[PIPE_C] = 1;
> @@ -843,9 +843,9 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
> cherryview_sseu_info_init(dev_priv);
> else if (IS_BROADWELL(dev_priv))
> broadwell_sseu_info_init(dev_priv);
> - else if (INTEL_GEN(dev_priv) == 9)
> + else if (IS_GEN9(dev_priv))
> gen9_sseu_info_init(dev_priv);
> - else if (INTEL_GEN(dev_priv) == 10)
> + else if (IS_GEN10(dev_priv))
> gen10_sseu_info_init(dev_priv);
> else if (INTEL_GEN(dev_priv) >= 11)
> gen11_sseu_info_init(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index fc7e3b0bd95c..a6869c547f3c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5268,7 +5268,7 @@ static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
> if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
> return false;
>
> - if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
> + if ((IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) ||
> IS_CANNONLAKE(dev_priv))
> return true;
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 8c38efef77a1..761447c456c7 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -455,7 +455,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
> if (INTEL_GEN(dev_priv) >= 10) {
> source_rates = cnl_rates;
> size = ARRAY_SIZE(cnl_rates);
> - if (INTEL_GEN(dev_priv) == 10)
> + if (IS_GEN10(dev_priv))
> max_rate = cnl_max_source_rate(intel_dp);
> else
> max_rate = icl_max_source_rate(intel_dp);
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 65f6c9bc10cf..a4b1d82c89da 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -812,7 +812,7 @@ u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)
> u32 slice = fls(sseu->slice_mask);
> u32 subslice = fls(sseu->subslice_mask[slice]);
>
> - if (INTEL_GEN(dev_priv) == 10)
> + if (IS_GEN10(dev_priv))
> mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
> GEN8_MCR_SUBSLICE(subslice);
> else if (INTEL_GEN(dev_priv) >= 11)
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> index c90954cdfb15..96f70d896c10 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -84,7 +84,7 @@ static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
> int lines;
>
> intel_fbc_get_plane_source_size(cache, NULL, &lines);
> - if (INTEL_GEN(dev_priv) == 7)
> + if (IS_GEN7(dev_priv))
> lines = min(lines, 2048);
> else if (INTEL_GEN(dev_priv) >= 8)
> lines = min(lines, 2560);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 67a4d0735291..3793866a9ee7 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4676,13 +4676,13 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
> selected_result = method2;
> } else if (ddb_allocation >=
> fixed16_to_u32_round_up(wp->plane_blocks_per_line)) {
> - if (INTEL_GEN(dev_priv) == 9 &&
> + if (IS_GEN9(dev_priv) &&
> !IS_GEMINILAKE(dev_priv))
> selected_result = min_fixed16(method1, method2);
> else
> selected_result = method2;
> } else if (latency >= wp->linetime_us) {
> - if (INTEL_GEN(dev_priv) == 9 &&
> + if (IS_GEN9(dev_priv) &&
> !IS_GEMINILAKE(dev_priv))
> selected_result = min_fixed16(method1, method2);
> else
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 423cdf84059c..bc2d88313ed0 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -574,7 +574,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
> if (dev_priv->psr.psr2_enabled) {
> u32 chicken = I915_READ(CHICKEN_TRANS(cpu_transcoder));
>
> - if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv))
> + if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv))
> chicken |= (PSR2_VSC_ENABLE_PROG_HEADER
> | PSR2_ADD_VERTICAL_LINE_COUNT);
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index f6ec48a75a69..d3a08d0f02fe 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -93,11 +93,11 @@ hangcheck_action_to_str(const enum intel_engine_hangcheck_action a)
> #define I915_MAX_SUBSLICES 8
>
> #define instdone_slice_mask(dev_priv__) \
> - (INTEL_GEN(dev_priv__) == 7 ? \
> + (IS_GEN7(dev_priv__) ? \
> 1 : INTEL_INFO(dev_priv__)->sseu.slice_mask)
>
> #define instdone_subslice_mask(dev_priv__) \
> - (INTEL_GEN(dev_priv__) == 7 ? \
> + (IS_GEN7(dev_priv__) ? \
> 1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask[0])
>
> #define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 7cd59eee5cad..4c9f0b7138b3 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1798,7 +1798,7 @@ static bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
> if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
> return false;
>
> - if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C)
> + if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C)
> return false;
>
> if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0)
> --
> 2.19.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [RFC 3/3] drm/i915: Kill GEN_FOREVER
2018-10-23 23:36 ` [RFC 3/3] drm/i915: Kill GEN_FOREVER Rodrigo Vivi
@ 2018-10-24 12:31 ` Daniel Vetter
0 siblings, 0 replies; 18+ messages in thread
From: Daniel Vetter @ 2018-10-24 12:31 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Tue, Oct 23, 2018 at 04:36:20PM -0700, Rodrigo Vivi wrote:
> commit ac657f6461e5 ("drm/i915: Introduce IS_GEN macro") introduced
> GEN_FOREVER that was never used.
>
> My first attempt was to rename it to FOREVER since GEN is
> already part of the macro. Then I used coccinelle to change all
> -INTEL_GEN(e1) >= e2
> +INTEL_GEN_RANGE(e1, e2, FOREVER)
> -INTEL_GEN(e1) <= e2
> +INTEL_GEN_RANGE(e1, 0, e2)
>
> and I liked it.
>
> However I didn't like very much the remaining
> INTEL_GEN(dev_priv) < n
>
> and:
> INTEL_GEN(e1) < n
> INTEL_GEN_RANGE(e1, 0, n - 1)
>
> didn't make much sense either.
>
> So INTEL_GEN use for > or < seems a better unified way for unlimited
> bounds. So, no reason to keep GEN_FOREVER here.
>
> Let's kill before someone start using it.
>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 6 +-----
> 1 file changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f766bb1e873b..24f17e711772 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2373,14 +2373,10 @@ intel_info(const struct drm_i915_private *dev_priv)
> #define REVID_FOREVER 0xff
> #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
>
> -#define GEN_FOREVER (0)
> -
> #define INTEL_GEN_MASK(s, e) ( \
> BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
> BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
> - GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \
> - (s) != GEN_FOREVER ? (s) - 1 : 0) \
> -)
> + GENMASK((e) - 1, (s) - 1))
>
> /*
> * Returns true if Gen is in inclusive range [Start, End].
You missed GEN_FOREVER a bit below here in a comment. With that fixed, on
the series:
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> --
> 2.19.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [RFC 2/3] drm/i915: Prefer IS_GEN<n> check with bitmask.
2018-10-24 10:22 ` Ville Syrjälä
@ 2018-10-24 14:54 ` Julia Lawall
2018-10-24 15:15 ` Ville Syrjälä
2018-10-24 23:41 ` Rodrigo Vivi
1 sibling, 1 reply; 18+ messages in thread
From: Julia Lawall @ 2018-10-24 14:54 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, Rodrigo Vivi
[-- Attachment #1: Type: text/plain, Size: 9365 bytes --]
> I wish it would look something more like this:
>
> @@
> identifier old =~ "^INTEL_GEN$";
> expression exp;
> constant gen;
> fresh identifier new = "IS_GEN" ## gen;
> @@
> - old(exp) == gen
> + new(exp)
>
> But coccinelle doesn't seem to accept the constant in the fresh
> identifier thing.
I think that the idea was to be sure that there would be no whitespace in
the middle of the variable name. But a constant should indeed be fine. I
can adjust that, in case it's useful in the future.
julia
>
>
> Patch looks fine anyways
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> >
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.c | 2 +-
> > drivers/gpu/drm/i915/intel_atomic.c | 2 +-
> > drivers/gpu/drm/i915/intel_device_info.c | 6 +++---
> > drivers/gpu/drm/i915/intel_display.c | 2 +-
> > drivers/gpu/drm/i915/intel_dp.c | 2 +-
> > drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
> > drivers/gpu/drm/i915/intel_fbc.c | 2 +-
> > drivers/gpu/drm/i915/intel_pm.c | 4 ++--
> > drivers/gpu/drm/i915/intel_psr.c | 2 +-
> > drivers/gpu/drm/i915/intel_ringbuffer.h | 4 ++--
> > drivers/gpu/drm/i915/intel_sprite.c | 2 +-
> > 11 files changed, 15 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > index baac35f698f9..d755e84fed07 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -1329,7 +1329,7 @@ intel_get_dram_info(struct drm_i915_private *dev_priv)
> > /* Need to calculate bandwidth only for Gen9 */
> > if (IS_BROXTON(dev_priv))
> > ret = bxt_get_dram_info(dev_priv);
> > - else if (INTEL_GEN(dev_priv) == 9)
> > + else if (IS_GEN9(dev_priv))
> > ret = skl_get_dram_info(dev_priv);
> > else
> > ret = skl_dram_get_channels_info(dev_priv);
> > diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
> > index 760758ad21c1..3526f6d9c1ad 100644
> > --- a/drivers/gpu/drm/i915/intel_atomic.c
> > +++ b/drivers/gpu/drm/i915/intel_atomic.c
> > @@ -232,7 +232,7 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta
> > if (plane_state && plane_state->base.fb &&
> > plane_state->base.fb->format->is_yuv &&
> > plane_state->base.fb->format->num_planes > 1) {
> > - if (INTEL_GEN(dev_priv) == 9 &&
> > + if (IS_GEN9(dev_priv) &&
> > !IS_GEMINILAKE(dev_priv))
> > mode = SKL_PS_SCALER_MODE_NV12;
> > else
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> > index 03df4e33763d..561ad0d4a53d 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > @@ -744,7 +744,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
> > if (INTEL_GEN(dev_priv) >= 10) {
> > for_each_pipe(dev_priv, pipe)
> > info->num_scalers[pipe] = 2;
> > - } else if (INTEL_GEN(dev_priv) == 9) {
> > + } else if (IS_GEN9(dev_priv)) {
> > info->num_scalers[PIPE_A] = 2;
> > info->num_scalers[PIPE_B] = 2;
> > info->num_scalers[PIPE_C] = 1;
> > @@ -843,9 +843,9 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
> > cherryview_sseu_info_init(dev_priv);
> > else if (IS_BROADWELL(dev_priv))
> > broadwell_sseu_info_init(dev_priv);
> > - else if (INTEL_GEN(dev_priv) == 9)
> > + else if (IS_GEN9(dev_priv))
> > gen9_sseu_info_init(dev_priv);
> > - else if (INTEL_GEN(dev_priv) == 10)
> > + else if (IS_GEN10(dev_priv))
> > gen10_sseu_info_init(dev_priv);
> > else if (INTEL_GEN(dev_priv) >= 11)
> > gen11_sseu_info_init(dev_priv);
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index fc7e3b0bd95c..a6869c547f3c 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5268,7 +5268,7 @@ static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
> > if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
> > return false;
> >
> > - if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
> > + if ((IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) ||
> > IS_CANNONLAKE(dev_priv))
> > return true;
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 8c38efef77a1..761447c456c7 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -455,7 +455,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
> > if (INTEL_GEN(dev_priv) >= 10) {
> > source_rates = cnl_rates;
> > size = ARRAY_SIZE(cnl_rates);
> > - if (INTEL_GEN(dev_priv) == 10)
> > + if (IS_GEN10(dev_priv))
> > max_rate = cnl_max_source_rate(intel_dp);
> > else
> > max_rate = icl_max_source_rate(intel_dp);
> > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> > index 65f6c9bc10cf..a4b1d82c89da 100644
> > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > @@ -812,7 +812,7 @@ u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)
> > u32 slice = fls(sseu->slice_mask);
> > u32 subslice = fls(sseu->subslice_mask[slice]);
> >
> > - if (INTEL_GEN(dev_priv) == 10)
> > + if (IS_GEN10(dev_priv))
> > mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
> > GEN8_MCR_SUBSLICE(subslice);
> > else if (INTEL_GEN(dev_priv) >= 11)
> > diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> > index c90954cdfb15..96f70d896c10 100644
> > --- a/drivers/gpu/drm/i915/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/intel_fbc.c
> > @@ -84,7 +84,7 @@ static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
> > int lines;
> >
> > intel_fbc_get_plane_source_size(cache, NULL, &lines);
> > - if (INTEL_GEN(dev_priv) == 7)
> > + if (IS_GEN7(dev_priv))
> > lines = min(lines, 2048);
> > else if (INTEL_GEN(dev_priv) >= 8)
> > lines = min(lines, 2560);
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 67a4d0735291..3793866a9ee7 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4676,13 +4676,13 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
> > selected_result = method2;
> > } else if (ddb_allocation >=
> > fixed16_to_u32_round_up(wp->plane_blocks_per_line)) {
> > - if (INTEL_GEN(dev_priv) == 9 &&
> > + if (IS_GEN9(dev_priv) &&
> > !IS_GEMINILAKE(dev_priv))
> > selected_result = min_fixed16(method1, method2);
> > else
> > selected_result = method2;
> > } else if (latency >= wp->linetime_us) {
> > - if (INTEL_GEN(dev_priv) == 9 &&
> > + if (IS_GEN9(dev_priv) &&
> > !IS_GEMINILAKE(dev_priv))
> > selected_result = min_fixed16(method1, method2);
> > else
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> > index 423cdf84059c..bc2d88313ed0 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -574,7 +574,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
> > if (dev_priv->psr.psr2_enabled) {
> > u32 chicken = I915_READ(CHICKEN_TRANS(cpu_transcoder));
> >
> > - if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv))
> > + if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv))
> > chicken |= (PSR2_VSC_ENABLE_PROG_HEADER
> > | PSR2_ADD_VERTICAL_LINE_COUNT);
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> > index f6ec48a75a69..d3a08d0f02fe 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> > @@ -93,11 +93,11 @@ hangcheck_action_to_str(const enum intel_engine_hangcheck_action a)
> > #define I915_MAX_SUBSLICES 8
> >
> > #define instdone_slice_mask(dev_priv__) \
> > - (INTEL_GEN(dev_priv__) == 7 ? \
> > + (IS_GEN7(dev_priv__) ? \
> > 1 : INTEL_INFO(dev_priv__)->sseu.slice_mask)
> >
> > #define instdone_subslice_mask(dev_priv__) \
> > - (INTEL_GEN(dev_priv__) == 7 ? \
> > + (IS_GEN7(dev_priv__) ? \
> > 1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask[0])
> >
> > #define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
> > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> > index 7cd59eee5cad..4c9f0b7138b3 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -1798,7 +1798,7 @@ static bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
> > if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
> > return false;
> >
> > - if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C)
> > + if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C)
> > return false;
> >
> > if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0)
> > --
> > 2.19.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel
>
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [RFC 2/3] drm/i915: Prefer IS_GEN<n> check with bitmask.
2018-10-24 14:54 ` Julia Lawall
@ 2018-10-24 15:15 ` Ville Syrjälä
0 siblings, 0 replies; 18+ messages in thread
From: Ville Syrjälä @ 2018-10-24 15:15 UTC (permalink / raw)
To: Julia Lawall; +Cc: intel-gfx, Rodrigo Vivi
On Wed, Oct 24, 2018 at 03:54:56PM +0100, Julia Lawall wrote:
> > I wish it would look something more like this:
> >
> > @@
> > identifier old =~ "^INTEL_GEN$";
> > expression exp;
> > constant gen;
> > fresh identifier new = "IS_GEN" ## gen;
> > @@
> > - old(exp) == gen
> > + new(exp)
> >
> > But coccinelle doesn't seem to accept the constant in the fresh
> > identifier thing.
>
> I think that the idea was to be sure that there would be no whitespace in
> the middle of the variable name. But a constant should indeed be fine. I
> can adjust that, in case it's useful in the future.
I think I had another similar case recently where I also wanted
a constant in there. Ah yes, now I remember. I was trying to
convert "n * 1024" to "SZ_nK" etc.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [RFC 2/3] drm/i915: Prefer IS_GEN<n> check with bitmask.
2018-10-24 10:22 ` Ville Syrjälä
2018-10-24 14:54 ` Julia Lawall
@ 2018-10-24 23:41 ` Rodrigo Vivi
2018-10-25 10:59 ` Ville Syrjälä
1 sibling, 1 reply; 18+ messages in thread
From: Rodrigo Vivi @ 2018-10-24 23:41 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Julia Lawall, intel-gfx
On Wed, Oct 24, 2018 at 01:22:57PM +0300, Ville Syrjälä wrote:
> On Tue, Oct 23, 2018 at 04:36:19PM -0700, Rodrigo Vivi wrote:
> > Whenever possible we should stick with IS_GEN<n> checks.
> >
> > Bitmaks has been introduced on commit ae7617f0ef18 ("drm/i915:
> > Allow optimized platform checks") for efficiency.
> >
> > Let's stick with it whenever possible.
> >
> > This patch was generated with coccinelle:
> >
> > spatch -sp_file is_gen.cocci *{c,h} --in-place
> >
> > is_gen.cocci:
> > @gen2@ expression e; @@
> > -INTEL_GEN(e) == 2
> > +IS_GEN2(e)
> > @gen3@ expression e; @@
> > -INTEL_GEN(e) == 3
> > +IS_GEN3(e)
> > @gen4@ expression e; @@
> > -INTEL_GEN(e) == 4
> > +IS_GEN4(e)
> > @gen5@ expression e; @@
> > -INTEL_GEN(e) == 5
> > +IS_GEN5(e)
> > @gen6@ expression e; @@
> > -INTEL_GEN(e) == 6
> > +IS_GEN6(e)
> > @gen7@ expression e; @@
> > -INTEL_GEN(e) == 7
> > +IS_GEN7(e)
> > @gen8@ expression e; @@
> > -INTEL_GEN(e) == 8
> > +IS_GEN8(e)
> > @gen9@ expression e; @@
> > -INTEL_GEN(e) == 9
> > +IS_GEN9(e)
> > @gen10@ expression e; @@
> > -INTEL_GEN(e) == 10
> > +IS_GEN10(e)
> > @gen11@ expression e; @@
> > -INTEL_GEN(e) == 11
> > +IS_GEN11(e)
>
> Slightly less repetitive version.
Thanks. I'm supper newbie on coccinelle and it was
easier to duplicate then trying to learn all this new lang.
But I really appreciate you sharing this. I'd like
to go with this so the better rule keeps on commit message.
> Sadly not super neat on
> account of having to use the python stuff.
however it seems python version didn't work so well here:
init_defs_builtins: /usr/lib64/coccinelle/standard.h
Python error: No module named coccilib.elems
do you have any idea about it?
I couldn't find anything on google or on pip repositories
for that.
Thanks,
Rodrigo.
>
> @find@
> identifier old =~ "^INTEL_GEN$";
> expression exp;
> constant gen;
> @@
> old(exp) == gen
>
> @script:python rename@
> old << find.old;
> gen << find.gen;
> new;
> @@
> def do_rename(old, gen):
> return "IS_GEN" + gen
> coccinelle.new = cocci.make_ident(do_rename(old, gen))
> print coccinelle.new
>
> @@
> identifier find.old;
> expression find.exp;
> constant find.gen;
> identifier rename.new;
> @@
> - old(exp) == gen
> + new(exp)
>
>
> I wish it would look something more like this:
>
> @@
> identifier old =~ "^INTEL_GEN$";
> expression exp;
> constant gen;
> fresh identifier new = "IS_GEN" ## gen;
> @@
> - old(exp) == gen
> + new(exp)
>
> But coccinelle doesn't seem to accept the constant in the fresh
> identifier thing.
>
>
> Patch looks fine anyways
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> >
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.c | 2 +-
> > drivers/gpu/drm/i915/intel_atomic.c | 2 +-
> > drivers/gpu/drm/i915/intel_device_info.c | 6 +++---
> > drivers/gpu/drm/i915/intel_display.c | 2 +-
> > drivers/gpu/drm/i915/intel_dp.c | 2 +-
> > drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
> > drivers/gpu/drm/i915/intel_fbc.c | 2 +-
> > drivers/gpu/drm/i915/intel_pm.c | 4 ++--
> > drivers/gpu/drm/i915/intel_psr.c | 2 +-
> > drivers/gpu/drm/i915/intel_ringbuffer.h | 4 ++--
> > drivers/gpu/drm/i915/intel_sprite.c | 2 +-
> > 11 files changed, 15 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > index baac35f698f9..d755e84fed07 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -1329,7 +1329,7 @@ intel_get_dram_info(struct drm_i915_private *dev_priv)
> > /* Need to calculate bandwidth only for Gen9 */
> > if (IS_BROXTON(dev_priv))
> > ret = bxt_get_dram_info(dev_priv);
> > - else if (INTEL_GEN(dev_priv) == 9)
> > + else if (IS_GEN9(dev_priv))
> > ret = skl_get_dram_info(dev_priv);
> > else
> > ret = skl_dram_get_channels_info(dev_priv);
> > diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
> > index 760758ad21c1..3526f6d9c1ad 100644
> > --- a/drivers/gpu/drm/i915/intel_atomic.c
> > +++ b/drivers/gpu/drm/i915/intel_atomic.c
> > @@ -232,7 +232,7 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta
> > if (plane_state && plane_state->base.fb &&
> > plane_state->base.fb->format->is_yuv &&
> > plane_state->base.fb->format->num_planes > 1) {
> > - if (INTEL_GEN(dev_priv) == 9 &&
> > + if (IS_GEN9(dev_priv) &&
> > !IS_GEMINILAKE(dev_priv))
> > mode = SKL_PS_SCALER_MODE_NV12;
> > else
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> > index 03df4e33763d..561ad0d4a53d 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > @@ -744,7 +744,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
> > if (INTEL_GEN(dev_priv) >= 10) {
> > for_each_pipe(dev_priv, pipe)
> > info->num_scalers[pipe] = 2;
> > - } else if (INTEL_GEN(dev_priv) == 9) {
> > + } else if (IS_GEN9(dev_priv)) {
> > info->num_scalers[PIPE_A] = 2;
> > info->num_scalers[PIPE_B] = 2;
> > info->num_scalers[PIPE_C] = 1;
> > @@ -843,9 +843,9 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
> > cherryview_sseu_info_init(dev_priv);
> > else if (IS_BROADWELL(dev_priv))
> > broadwell_sseu_info_init(dev_priv);
> > - else if (INTEL_GEN(dev_priv) == 9)
> > + else if (IS_GEN9(dev_priv))
> > gen9_sseu_info_init(dev_priv);
> > - else if (INTEL_GEN(dev_priv) == 10)
> > + else if (IS_GEN10(dev_priv))
> > gen10_sseu_info_init(dev_priv);
> > else if (INTEL_GEN(dev_priv) >= 11)
> > gen11_sseu_info_init(dev_priv);
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index fc7e3b0bd95c..a6869c547f3c 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5268,7 +5268,7 @@ static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
> > if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
> > return false;
> >
> > - if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
> > + if ((IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) ||
> > IS_CANNONLAKE(dev_priv))
> > return true;
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 8c38efef77a1..761447c456c7 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -455,7 +455,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
> > if (INTEL_GEN(dev_priv) >= 10) {
> > source_rates = cnl_rates;
> > size = ARRAY_SIZE(cnl_rates);
> > - if (INTEL_GEN(dev_priv) == 10)
> > + if (IS_GEN10(dev_priv))
> > max_rate = cnl_max_source_rate(intel_dp);
> > else
> > max_rate = icl_max_source_rate(intel_dp);
> > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> > index 65f6c9bc10cf..a4b1d82c89da 100644
> > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > @@ -812,7 +812,7 @@ u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)
> > u32 slice = fls(sseu->slice_mask);
> > u32 subslice = fls(sseu->subslice_mask[slice]);
> >
> > - if (INTEL_GEN(dev_priv) == 10)
> > + if (IS_GEN10(dev_priv))
> > mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
> > GEN8_MCR_SUBSLICE(subslice);
> > else if (INTEL_GEN(dev_priv) >= 11)
> > diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> > index c90954cdfb15..96f70d896c10 100644
> > --- a/drivers/gpu/drm/i915/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/intel_fbc.c
> > @@ -84,7 +84,7 @@ static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
> > int lines;
> >
> > intel_fbc_get_plane_source_size(cache, NULL, &lines);
> > - if (INTEL_GEN(dev_priv) == 7)
> > + if (IS_GEN7(dev_priv))
> > lines = min(lines, 2048);
> > else if (INTEL_GEN(dev_priv) >= 8)
> > lines = min(lines, 2560);
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 67a4d0735291..3793866a9ee7 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4676,13 +4676,13 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
> > selected_result = method2;
> > } else if (ddb_allocation >=
> > fixed16_to_u32_round_up(wp->plane_blocks_per_line)) {
> > - if (INTEL_GEN(dev_priv) == 9 &&
> > + if (IS_GEN9(dev_priv) &&
> > !IS_GEMINILAKE(dev_priv))
> > selected_result = min_fixed16(method1, method2);
> > else
> > selected_result = method2;
> > } else if (latency >= wp->linetime_us) {
> > - if (INTEL_GEN(dev_priv) == 9 &&
> > + if (IS_GEN9(dev_priv) &&
> > !IS_GEMINILAKE(dev_priv))
> > selected_result = min_fixed16(method1, method2);
> > else
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> > index 423cdf84059c..bc2d88313ed0 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -574,7 +574,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
> > if (dev_priv->psr.psr2_enabled) {
> > u32 chicken = I915_READ(CHICKEN_TRANS(cpu_transcoder));
> >
> > - if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv))
> > + if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv))
> > chicken |= (PSR2_VSC_ENABLE_PROG_HEADER
> > | PSR2_ADD_VERTICAL_LINE_COUNT);
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> > index f6ec48a75a69..d3a08d0f02fe 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> > @@ -93,11 +93,11 @@ hangcheck_action_to_str(const enum intel_engine_hangcheck_action a)
> > #define I915_MAX_SUBSLICES 8
> >
> > #define instdone_slice_mask(dev_priv__) \
> > - (INTEL_GEN(dev_priv__) == 7 ? \
> > + (IS_GEN7(dev_priv__) ? \
> > 1 : INTEL_INFO(dev_priv__)->sseu.slice_mask)
> >
> > #define instdone_subslice_mask(dev_priv__) \
> > - (INTEL_GEN(dev_priv__) == 7 ? \
> > + (IS_GEN7(dev_priv__) ? \
> > 1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask[0])
> >
> > #define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
> > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> > index 7cd59eee5cad..4c9f0b7138b3 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -1798,7 +1798,7 @@ static bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
> > if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
> > return false;
> >
> > - if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C)
> > + if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C)
> > return false;
> >
> > if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0)
> > --
> > 2.19.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [RFC 2/3] drm/i915: Prefer IS_GEN<n> check with bitmask.
2018-10-24 23:41 ` Rodrigo Vivi
@ 2018-10-25 10:59 ` Ville Syrjälä
2018-10-25 11:11 ` Julia Lawall
0 siblings, 1 reply; 18+ messages in thread
From: Ville Syrjälä @ 2018-10-25 10:59 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: Julia Lawall, intel-gfx
On Wed, Oct 24, 2018 at 04:41:06PM -0700, Rodrigo Vivi wrote:
> On Wed, Oct 24, 2018 at 01:22:57PM +0300, Ville Syrjälä wrote:
> > On Tue, Oct 23, 2018 at 04:36:19PM -0700, Rodrigo Vivi wrote:
> > > Whenever possible we should stick with IS_GEN<n> checks.
> > >
> > > Bitmaks has been introduced on commit ae7617f0ef18 ("drm/i915:
> > > Allow optimized platform checks") for efficiency.
> > >
> > > Let's stick with it whenever possible.
> > >
> > > This patch was generated with coccinelle:
> > >
> > > spatch -sp_file is_gen.cocci *{c,h} --in-place
> > >
> > > is_gen.cocci:
> > > @gen2@ expression e; @@
> > > -INTEL_GEN(e) == 2
> > > +IS_GEN2(e)
> > > @gen3@ expression e; @@
> > > -INTEL_GEN(e) == 3
> > > +IS_GEN3(e)
> > > @gen4@ expression e; @@
> > > -INTEL_GEN(e) == 4
> > > +IS_GEN4(e)
> > > @gen5@ expression e; @@
> > > -INTEL_GEN(e) == 5
> > > +IS_GEN5(e)
> > > @gen6@ expression e; @@
> > > -INTEL_GEN(e) == 6
> > > +IS_GEN6(e)
> > > @gen7@ expression e; @@
> > > -INTEL_GEN(e) == 7
> > > +IS_GEN7(e)
> > > @gen8@ expression e; @@
> > > -INTEL_GEN(e) == 8
> > > +IS_GEN8(e)
> > > @gen9@ expression e; @@
> > > -INTEL_GEN(e) == 9
> > > +IS_GEN9(e)
> > > @gen10@ expression e; @@
> > > -INTEL_GEN(e) == 10
> > > +IS_GEN10(e)
> > > @gen11@ expression e; @@
> > > -INTEL_GEN(e) == 11
> > > +IS_GEN11(e)
> >
> > Slightly less repetitive version.
>
> Thanks. I'm supper newbie on coccinelle and it was
> easier to duplicate then trying to learn all this new lang.
>
> But I really appreciate you sharing this. I'd like
> to go with this so the better rule keeps on commit message.
>
> > Sadly not super neat on
> > account of having to use the python stuff.
>
> however it seems python version didn't work so well here:
>
> init_defs_builtins: /usr/lib64/coccinelle/standard.h
> Python error: No module named coccilib.elems
>
> do you have any idea about it?
Never seen it. On gentoo it just works when I have the python
use flag enabled.
Maybe your distro doesn't include the python support in the
build, or maybe some kind of python version issue?
>
> I couldn't find anything on google or on pip repositories
> for that.
>
> Thanks,
> Rodrigo.
>
> >
> > @find@
> > identifier old =~ "^INTEL_GEN$";
> > expression exp;
> > constant gen;
> > @@
> > old(exp) == gen
> >
> > @script:python rename@
> > old << find.old;
> > gen << find.gen;
> > new;
> > @@
> > def do_rename(old, gen):
> > return "IS_GEN" + gen
> > coccinelle.new = cocci.make_ident(do_rename(old, gen))
> > print coccinelle.new
> >
> > @@
> > identifier find.old;
> > expression find.exp;
> > constant find.gen;
> > identifier rename.new;
> > @@
> > - old(exp) == gen
> > + new(exp)
> >
> >
> > I wish it would look something more like this:
> >
> > @@
> > identifier old =~ "^INTEL_GEN$";
> > expression exp;
> > constant gen;
> > fresh identifier new = "IS_GEN" ## gen;
> > @@
> > - old(exp) == gen
> > + new(exp)
> >
> > But coccinelle doesn't seem to accept the constant in the fresh
> > identifier thing.
> >
> >
> > Patch looks fine anyways
> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > >
> > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_drv.c | 2 +-
> > > drivers/gpu/drm/i915/intel_atomic.c | 2 +-
> > > drivers/gpu/drm/i915/intel_device_info.c | 6 +++---
> > > drivers/gpu/drm/i915/intel_display.c | 2 +-
> > > drivers/gpu/drm/i915/intel_dp.c | 2 +-
> > > drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
> > > drivers/gpu/drm/i915/intel_fbc.c | 2 +-
> > > drivers/gpu/drm/i915/intel_pm.c | 4 ++--
> > > drivers/gpu/drm/i915/intel_psr.c | 2 +-
> > > drivers/gpu/drm/i915/intel_ringbuffer.h | 4 ++--
> > > drivers/gpu/drm/i915/intel_sprite.c | 2 +-
> > > 11 files changed, 15 insertions(+), 15 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > > index baac35f698f9..d755e84fed07 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > @@ -1329,7 +1329,7 @@ intel_get_dram_info(struct drm_i915_private *dev_priv)
> > > /* Need to calculate bandwidth only for Gen9 */
> > > if (IS_BROXTON(dev_priv))
> > > ret = bxt_get_dram_info(dev_priv);
> > > - else if (INTEL_GEN(dev_priv) == 9)
> > > + else if (IS_GEN9(dev_priv))
> > > ret = skl_get_dram_info(dev_priv);
> > > else
> > > ret = skl_dram_get_channels_info(dev_priv);
> > > diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
> > > index 760758ad21c1..3526f6d9c1ad 100644
> > > --- a/drivers/gpu/drm/i915/intel_atomic.c
> > > +++ b/drivers/gpu/drm/i915/intel_atomic.c
> > > @@ -232,7 +232,7 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta
> > > if (plane_state && plane_state->base.fb &&
> > > plane_state->base.fb->format->is_yuv &&
> > > plane_state->base.fb->format->num_planes > 1) {
> > > - if (INTEL_GEN(dev_priv) == 9 &&
> > > + if (IS_GEN9(dev_priv) &&
> > > !IS_GEMINILAKE(dev_priv))
> > > mode = SKL_PS_SCALER_MODE_NV12;
> > > else
> > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> > > index 03df4e33763d..561ad0d4a53d 100644
> > > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > > @@ -744,7 +744,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
> > > if (INTEL_GEN(dev_priv) >= 10) {
> > > for_each_pipe(dev_priv, pipe)
> > > info->num_scalers[pipe] = 2;
> > > - } else if (INTEL_GEN(dev_priv) == 9) {
> > > + } else if (IS_GEN9(dev_priv)) {
> > > info->num_scalers[PIPE_A] = 2;
> > > info->num_scalers[PIPE_B] = 2;
> > > info->num_scalers[PIPE_C] = 1;
> > > @@ -843,9 +843,9 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
> > > cherryview_sseu_info_init(dev_priv);
> > > else if (IS_BROADWELL(dev_priv))
> > > broadwell_sseu_info_init(dev_priv);
> > > - else if (INTEL_GEN(dev_priv) == 9)
> > > + else if (IS_GEN9(dev_priv))
> > > gen9_sseu_info_init(dev_priv);
> > > - else if (INTEL_GEN(dev_priv) == 10)
> > > + else if (IS_GEN10(dev_priv))
> > > gen10_sseu_info_init(dev_priv);
> > > else if (INTEL_GEN(dev_priv) >= 11)
> > > gen11_sseu_info_init(dev_priv);
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > > index fc7e3b0bd95c..a6869c547f3c 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -5268,7 +5268,7 @@ static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
> > > if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
> > > return false;
> > >
> > > - if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
> > > + if ((IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) ||
> > > IS_CANNONLAKE(dev_priv))
> > > return true;
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > > index 8c38efef77a1..761447c456c7 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -455,7 +455,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
> > > if (INTEL_GEN(dev_priv) >= 10) {
> > > source_rates = cnl_rates;
> > > size = ARRAY_SIZE(cnl_rates);
> > > - if (INTEL_GEN(dev_priv) == 10)
> > > + if (IS_GEN10(dev_priv))
> > > max_rate = cnl_max_source_rate(intel_dp);
> > > else
> > > max_rate = icl_max_source_rate(intel_dp);
> > > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> > > index 65f6c9bc10cf..a4b1d82c89da 100644
> > > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > > @@ -812,7 +812,7 @@ u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)
> > > u32 slice = fls(sseu->slice_mask);
> > > u32 subslice = fls(sseu->subslice_mask[slice]);
> > >
> > > - if (INTEL_GEN(dev_priv) == 10)
> > > + if (IS_GEN10(dev_priv))
> > > mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
> > > GEN8_MCR_SUBSLICE(subslice);
> > > else if (INTEL_GEN(dev_priv) >= 11)
> > > diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> > > index c90954cdfb15..96f70d896c10 100644
> > > --- a/drivers/gpu/drm/i915/intel_fbc.c
> > > +++ b/drivers/gpu/drm/i915/intel_fbc.c
> > > @@ -84,7 +84,7 @@ static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
> > > int lines;
> > >
> > > intel_fbc_get_plane_source_size(cache, NULL, &lines);
> > > - if (INTEL_GEN(dev_priv) == 7)
> > > + if (IS_GEN7(dev_priv))
> > > lines = min(lines, 2048);
> > > else if (INTEL_GEN(dev_priv) >= 8)
> > > lines = min(lines, 2560);
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index 67a4d0735291..3793866a9ee7 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -4676,13 +4676,13 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
> > > selected_result = method2;
> > > } else if (ddb_allocation >=
> > > fixed16_to_u32_round_up(wp->plane_blocks_per_line)) {
> > > - if (INTEL_GEN(dev_priv) == 9 &&
> > > + if (IS_GEN9(dev_priv) &&
> > > !IS_GEMINILAKE(dev_priv))
> > > selected_result = min_fixed16(method1, method2);
> > > else
> > > selected_result = method2;
> > > } else if (latency >= wp->linetime_us) {
> > > - if (INTEL_GEN(dev_priv) == 9 &&
> > > + if (IS_GEN9(dev_priv) &&
> > > !IS_GEMINILAKE(dev_priv))
> > > selected_result = min_fixed16(method1, method2);
> > > else
> > > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> > > index 423cdf84059c..bc2d88313ed0 100644
> > > --- a/drivers/gpu/drm/i915/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > > @@ -574,7 +574,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
> > > if (dev_priv->psr.psr2_enabled) {
> > > u32 chicken = I915_READ(CHICKEN_TRANS(cpu_transcoder));
> > >
> > > - if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv))
> > > + if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv))
> > > chicken |= (PSR2_VSC_ENABLE_PROG_HEADER
> > > | PSR2_ADD_VERTICAL_LINE_COUNT);
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> > > index f6ec48a75a69..d3a08d0f02fe 100644
> > > --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> > > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> > > @@ -93,11 +93,11 @@ hangcheck_action_to_str(const enum intel_engine_hangcheck_action a)
> > > #define I915_MAX_SUBSLICES 8
> > >
> > > #define instdone_slice_mask(dev_priv__) \
> > > - (INTEL_GEN(dev_priv__) == 7 ? \
> > > + (IS_GEN7(dev_priv__) ? \
> > > 1 : INTEL_INFO(dev_priv__)->sseu.slice_mask)
> > >
> > > #define instdone_subslice_mask(dev_priv__) \
> > > - (INTEL_GEN(dev_priv__) == 7 ? \
> > > + (IS_GEN7(dev_priv__) ? \
> > > 1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask[0])
> > >
> > > #define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
> > > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> > > index 7cd59eee5cad..4c9f0b7138b3 100644
> > > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > > @@ -1798,7 +1798,7 @@ static bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
> > > if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
> > > return false;
> > >
> > > - if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C)
> > > + if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C)
> > > return false;
> > >
> > > if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0)
> > > --
> > > 2.19.1
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> > --
> > Ville Syrjälä
> > Intel
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [RFC 2/3] drm/i915: Prefer IS_GEN<n> check with bitmask.
2018-10-25 10:59 ` Ville Syrjälä
@ 2018-10-25 11:11 ` Julia Lawall
2018-10-26 19:40 ` Rodrigo Vivi
0 siblings, 1 reply; 18+ messages in thread
From: Julia Lawall @ 2018-10-25 11:11 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, Rodrigo Vivi
[-- Attachment #1: Type: text/plain, Size: 13148 bytes --]
On Thu, 25 Oct 2018, Ville Syrjälä wrote:
> On Wed, Oct 24, 2018 at 04:41:06PM -0700, Rodrigo Vivi wrote:
> > On Wed, Oct 24, 2018 at 01:22:57PM +0300, Ville Syrjälä wrote:
> > > On Tue, Oct 23, 2018 at 04:36:19PM -0700, Rodrigo Vivi wrote:
> > > > Whenever possible we should stick with IS_GEN<n> checks.
> > > >
> > > > Bitmaks has been introduced on commit ae7617f0ef18 ("drm/i915:
> > > > Allow optimized platform checks") for efficiency.
> > > >
> > > > Let's stick with it whenever possible.
> > > >
> > > > This patch was generated with coccinelle:
> > > >
> > > > spatch -sp_file is_gen.cocci *{c,h} --in-place
> > > >
> > > > is_gen.cocci:
> > > > @gen2@ expression e; @@
> > > > -INTEL_GEN(e) == 2
> > > > +IS_GEN2(e)
> > > > @gen3@ expression e; @@
> > > > -INTEL_GEN(e) == 3
> > > > +IS_GEN3(e)
> > > > @gen4@ expression e; @@
> > > > -INTEL_GEN(e) == 4
> > > > +IS_GEN4(e)
> > > > @gen5@ expression e; @@
> > > > -INTEL_GEN(e) == 5
> > > > +IS_GEN5(e)
> > > > @gen6@ expression e; @@
> > > > -INTEL_GEN(e) == 6
> > > > +IS_GEN6(e)
> > > > @gen7@ expression e; @@
> > > > -INTEL_GEN(e) == 7
> > > > +IS_GEN7(e)
> > > > @gen8@ expression e; @@
> > > > -INTEL_GEN(e) == 8
> > > > +IS_GEN8(e)
> > > > @gen9@ expression e; @@
> > > > -INTEL_GEN(e) == 9
> > > > +IS_GEN9(e)
> > > > @gen10@ expression e; @@
> > > > -INTEL_GEN(e) == 10
> > > > +IS_GEN10(e)
> > > > @gen11@ expression e; @@
> > > > -INTEL_GEN(e) == 11
> > > > +IS_GEN11(e)
> > >
> > > Slightly less repetitive version.
> >
> > Thanks. I'm supper newbie on coccinelle and it was
> > easier to duplicate then trying to learn all this new lang.
> >
> > But I really appreciate you sharing this. I'd like
> > to go with this so the better rule keeps on commit message.
> >
> > > Sadly not super neat on
> > > account of having to use the python stuff.
> >
> > however it seems python version didn't work so well here:
> >
> > init_defs_builtins: /usr/lib64/coccinelle/standard.h
> > Python error: No module named coccilib.elems
> >
> > do you have any idea about it?
>
> Never seen it. On gentoo it just works when I have the python
> use flag enabled.
>
> Maybe your distro doesn't include the python support in the
> build, or maybe some kind of python version issue?
Thanks for the report. I will have someone look into it. It's an
internal Coccinelle thing. Perhaps python is not enabled. Do you have
the version of Coccinelle from github?
julia
>
> >
> > I couldn't find anything on google or on pip repositories
> > for that.
> >
> > Thanks,
> > Rodrigo.
> >
> > >
> > > @find@
> > > identifier old =~ "^INTEL_GEN$";
> > > expression exp;
> > > constant gen;
> > > @@
> > > old(exp) == gen
> > >
> > > @script:python rename@
> > > old << find.old;
> > > gen << find.gen;
> > > new;
> > > @@
> > > def do_rename(old, gen):
> > > return "IS_GEN" + gen
> > > coccinelle.new = cocci.make_ident(do_rename(old, gen))
> > > print coccinelle.new
> > >
> > > @@
> > > identifier find.old;
> > > expression find.exp;
> > > constant find.gen;
> > > identifier rename.new;
> > > @@
> > > - old(exp) == gen
> > > + new(exp)
> > >
> > >
> > > I wish it would look something more like this:
> > >
> > > @@
> > > identifier old =~ "^INTEL_GEN$";
> > > expression exp;
> > > constant gen;
> > > fresh identifier new = "IS_GEN" ## gen;
> > > @@
> > > - old(exp) == gen
> > > + new(exp)
> > >
> > > But coccinelle doesn't seem to accept the constant in the fresh
> > > identifier thing.
> > >
> > >
> > > Patch looks fine anyways
> > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > >
> > > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/i915_drv.c | 2 +-
> > > > drivers/gpu/drm/i915/intel_atomic.c | 2 +-
> > > > drivers/gpu/drm/i915/intel_device_info.c | 6 +++---
> > > > drivers/gpu/drm/i915/intel_display.c | 2 +-
> > > > drivers/gpu/drm/i915/intel_dp.c | 2 +-
> > > > drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
> > > > drivers/gpu/drm/i915/intel_fbc.c | 2 +-
> > > > drivers/gpu/drm/i915/intel_pm.c | 4 ++--
> > > > drivers/gpu/drm/i915/intel_psr.c | 2 +-
> > > > drivers/gpu/drm/i915/intel_ringbuffer.h | 4 ++--
> > > > drivers/gpu/drm/i915/intel_sprite.c | 2 +-
> > > > 11 files changed, 15 insertions(+), 15 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > > > index baac35f698f9..d755e84fed07 100644
> > > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > > @@ -1329,7 +1329,7 @@ intel_get_dram_info(struct drm_i915_private *dev_priv)
> > > > /* Need to calculate bandwidth only for Gen9 */
> > > > if (IS_BROXTON(dev_priv))
> > > > ret = bxt_get_dram_info(dev_priv);
> > > > - else if (INTEL_GEN(dev_priv) == 9)
> > > > + else if (IS_GEN9(dev_priv))
> > > > ret = skl_get_dram_info(dev_priv);
> > > > else
> > > > ret = skl_dram_get_channels_info(dev_priv);
> > > > diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
> > > > index 760758ad21c1..3526f6d9c1ad 100644
> > > > --- a/drivers/gpu/drm/i915/intel_atomic.c
> > > > +++ b/drivers/gpu/drm/i915/intel_atomic.c
> > > > @@ -232,7 +232,7 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta
> > > > if (plane_state && plane_state->base.fb &&
> > > > plane_state->base.fb->format->is_yuv &&
> > > > plane_state->base.fb->format->num_planes > 1) {
> > > > - if (INTEL_GEN(dev_priv) == 9 &&
> > > > + if (IS_GEN9(dev_priv) &&
> > > > !IS_GEMINILAKE(dev_priv))
> > > > mode = SKL_PS_SCALER_MODE_NV12;
> > > > else
> > > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> > > > index 03df4e33763d..561ad0d4a53d 100644
> > > > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > > > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > > > @@ -744,7 +744,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
> > > > if (INTEL_GEN(dev_priv) >= 10) {
> > > > for_each_pipe(dev_priv, pipe)
> > > > info->num_scalers[pipe] = 2;
> > > > - } else if (INTEL_GEN(dev_priv) == 9) {
> > > > + } else if (IS_GEN9(dev_priv)) {
> > > > info->num_scalers[PIPE_A] = 2;
> > > > info->num_scalers[PIPE_B] = 2;
> > > > info->num_scalers[PIPE_C] = 1;
> > > > @@ -843,9 +843,9 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
> > > > cherryview_sseu_info_init(dev_priv);
> > > > else if (IS_BROADWELL(dev_priv))
> > > > broadwell_sseu_info_init(dev_priv);
> > > > - else if (INTEL_GEN(dev_priv) == 9)
> > > > + else if (IS_GEN9(dev_priv))
> > > > gen9_sseu_info_init(dev_priv);
> > > > - else if (INTEL_GEN(dev_priv) == 10)
> > > > + else if (IS_GEN10(dev_priv))
> > > > gen10_sseu_info_init(dev_priv);
> > > > else if (INTEL_GEN(dev_priv) >= 11)
> > > > gen11_sseu_info_init(dev_priv);
> > > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > > > index fc7e3b0bd95c..a6869c547f3c 100644
> > > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > > @@ -5268,7 +5268,7 @@ static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
> > > > if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
> > > > return false;
> > > >
> > > > - if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
> > > > + if ((IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) ||
> > > > IS_CANNONLAKE(dev_priv))
> > > > return true;
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > > > index 8c38efef77a1..761447c456c7 100644
> > > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > > @@ -455,7 +455,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
> > > > if (INTEL_GEN(dev_priv) >= 10) {
> > > > source_rates = cnl_rates;
> > > > size = ARRAY_SIZE(cnl_rates);
> > > > - if (INTEL_GEN(dev_priv) == 10)
> > > > + if (IS_GEN10(dev_priv))
> > > > max_rate = cnl_max_source_rate(intel_dp);
> > > > else
> > > > max_rate = icl_max_source_rate(intel_dp);
> > > > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> > > > index 65f6c9bc10cf..a4b1d82c89da 100644
> > > > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > > > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > > > @@ -812,7 +812,7 @@ u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)
> > > > u32 slice = fls(sseu->slice_mask);
> > > > u32 subslice = fls(sseu->subslice_mask[slice]);
> > > >
> > > > - if (INTEL_GEN(dev_priv) == 10)
> > > > + if (IS_GEN10(dev_priv))
> > > > mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
> > > > GEN8_MCR_SUBSLICE(subslice);
> > > > else if (INTEL_GEN(dev_priv) >= 11)
> > > > diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> > > > index c90954cdfb15..96f70d896c10 100644
> > > > --- a/drivers/gpu/drm/i915/intel_fbc.c
> > > > +++ b/drivers/gpu/drm/i915/intel_fbc.c
> > > > @@ -84,7 +84,7 @@ static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
> > > > int lines;
> > > >
> > > > intel_fbc_get_plane_source_size(cache, NULL, &lines);
> > > > - if (INTEL_GEN(dev_priv) == 7)
> > > > + if (IS_GEN7(dev_priv))
> > > > lines = min(lines, 2048);
> > > > else if (INTEL_GEN(dev_priv) >= 8)
> > > > lines = min(lines, 2560);
> > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > index 67a4d0735291..3793866a9ee7 100644
> > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > @@ -4676,13 +4676,13 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
> > > > selected_result = method2;
> > > > } else if (ddb_allocation >=
> > > > fixed16_to_u32_round_up(wp->plane_blocks_per_line)) {
> > > > - if (INTEL_GEN(dev_priv) == 9 &&
> > > > + if (IS_GEN9(dev_priv) &&
> > > > !IS_GEMINILAKE(dev_priv))
> > > > selected_result = min_fixed16(method1, method2);
> > > > else
> > > > selected_result = method2;
> > > > } else if (latency >= wp->linetime_us) {
> > > > - if (INTEL_GEN(dev_priv) == 9 &&
> > > > + if (IS_GEN9(dev_priv) &&
> > > > !IS_GEMINILAKE(dev_priv))
> > > > selected_result = min_fixed16(method1, method2);
> > > > else
> > > > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> > > > index 423cdf84059c..bc2d88313ed0 100644
> > > > --- a/drivers/gpu/drm/i915/intel_psr.c
> > > > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > > > @@ -574,7 +574,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
> > > > if (dev_priv->psr.psr2_enabled) {
> > > > u32 chicken = I915_READ(CHICKEN_TRANS(cpu_transcoder));
> > > >
> > > > - if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv))
> > > > + if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv))
> > > > chicken |= (PSR2_VSC_ENABLE_PROG_HEADER
> > > > | PSR2_ADD_VERTICAL_LINE_COUNT);
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> > > > index f6ec48a75a69..d3a08d0f02fe 100644
> > > > --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> > > > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> > > > @@ -93,11 +93,11 @@ hangcheck_action_to_str(const enum intel_engine_hangcheck_action a)
> > > > #define I915_MAX_SUBSLICES 8
> > > >
> > > > #define instdone_slice_mask(dev_priv__) \
> > > > - (INTEL_GEN(dev_priv__) == 7 ? \
> > > > + (IS_GEN7(dev_priv__) ? \
> > > > 1 : INTEL_INFO(dev_priv__)->sseu.slice_mask)
> > > >
> > > > #define instdone_subslice_mask(dev_priv__) \
> > > > - (INTEL_GEN(dev_priv__) == 7 ? \
> > > > + (IS_GEN7(dev_priv__) ? \
> > > > 1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask[0])
> > > >
> > > > #define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
> > > > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> > > > index 7cd59eee5cad..4c9f0b7138b3 100644
> > > > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > > > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > > > @@ -1798,7 +1798,7 @@ static bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
> > > > if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
> > > > return false;
> > > >
> > > > - if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C)
> > > > + if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C)
> > > > return false;
> > > >
> > > > if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0)
> > > > --
> > > > 2.19.1
> > > >
> > > > _______________________________________________
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > >
> > > --
> > > Ville Syrjälä
> > > Intel
>
> --
> Ville Syrjälä
> Intel
>
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [RFC 2/3] drm/i915: Prefer IS_GEN<n> check with bitmask.
2018-10-25 11:11 ` Julia Lawall
@ 2018-10-26 19:40 ` Rodrigo Vivi
2018-10-26 19:47 ` Julia Lawall
0 siblings, 1 reply; 18+ messages in thread
From: Rodrigo Vivi @ 2018-10-26 19:40 UTC (permalink / raw)
To: Julia Lawall; +Cc: intel-gfx
On Thu, Oct 25, 2018 at 12:11:57PM +0100, Julia Lawall wrote:
>
>
> On Thu, 25 Oct 2018, Ville Syrjälä wrote:
>
> > On Wed, Oct 24, 2018 at 04:41:06PM -0700, Rodrigo Vivi wrote:
> > > On Wed, Oct 24, 2018 at 01:22:57PM +0300, Ville Syrjälä wrote:
> > > > On Tue, Oct 23, 2018 at 04:36:19PM -0700, Rodrigo Vivi wrote:
> > > > > Whenever possible we should stick with IS_GEN<n> checks.
> > > > >
> > > > > Bitmaks has been introduced on commit ae7617f0ef18 ("drm/i915:
> > > > > Allow optimized platform checks") for efficiency.
> > > > >
> > > > > Let's stick with it whenever possible.
> > > > >
> > > > > This patch was generated with coccinelle:
> > > > >
> > > > > spatch -sp_file is_gen.cocci *{c,h} --in-place
> > > > >
> > > > > is_gen.cocci:
> > > > > @gen2@ expression e; @@
> > > > > -INTEL_GEN(e) == 2
> > > > > +IS_GEN2(e)
> > > > > @gen3@ expression e; @@
> > > > > -INTEL_GEN(e) == 3
> > > > > +IS_GEN3(e)
> > > > > @gen4@ expression e; @@
> > > > > -INTEL_GEN(e) == 4
> > > > > +IS_GEN4(e)
> > > > > @gen5@ expression e; @@
> > > > > -INTEL_GEN(e) == 5
> > > > > +IS_GEN5(e)
> > > > > @gen6@ expression e; @@
> > > > > -INTEL_GEN(e) == 6
> > > > > +IS_GEN6(e)
> > > > > @gen7@ expression e; @@
> > > > > -INTEL_GEN(e) == 7
> > > > > +IS_GEN7(e)
> > > > > @gen8@ expression e; @@
> > > > > -INTEL_GEN(e) == 8
> > > > > +IS_GEN8(e)
> > > > > @gen9@ expression e; @@
> > > > > -INTEL_GEN(e) == 9
> > > > > +IS_GEN9(e)
> > > > > @gen10@ expression e; @@
> > > > > -INTEL_GEN(e) == 10
> > > > > +IS_GEN10(e)
> > > > > @gen11@ expression e; @@
> > > > > -INTEL_GEN(e) == 11
> > > > > +IS_GEN11(e)
> > > >
> > > > Slightly less repetitive version.
> > >
> > > Thanks. I'm supper newbie on coccinelle and it was
> > > easier to duplicate then trying to learn all this new lang.
> > >
> > > But I really appreciate you sharing this. I'd like
> > > to go with this so the better rule keeps on commit message.
> > >
> > > > Sadly not super neat on
> > > > account of having to use the python stuff.
> > >
> > > however it seems python version didn't work so well here:
> > >
> > > init_defs_builtins: /usr/lib64/coccinelle/standard.h
> > > Python error: No module named coccilib.elems
> > >
> > > do you have any idea about it?
> >
> > Never seen it. On gentoo it just works when I have the python
> > use flag enabled.
> >
> > Maybe your distro doesn't include the python support in the
> > build, or maybe some kind of python version issue?
>
> Thanks for the report. I will have someone look into it. It's an
> internal Coccinelle thing. Perhaps python is not enabled. Do you have
> the version of Coccinelle from github?
I just tried with coccinelle from github but got same result.
But with this commit before the bump to automake1.16:
commit 4db95998768557c66d6e337be2253032b5d810bc (HEAD -> master)
Author: Thierry Martinez <thierry.martinez@inria.fr>
Date: Wed Sep 12 14:43:41 2018 +0200
Compute depend by calling make recursilevy
The set of files in $(source_files) may change when the tarball is
unpacked.
----
$ python --version
Python 2.7.15
$ python3 --version
Python 3.6.6
----
I believe I'm moving this patch with the repetitive bad
rule for now that I'm sure it works in most of the distros.
Thanks,
Rodrigo.
>
> julia
>
> >
> > >
> > > I couldn't find anything on google or on pip repositories
> > > for that.
> > >
> > > Thanks,
> > > Rodrigo.
> > >
> > > >
> > > > @find@
> > > > identifier old =~ "^INTEL_GEN$";
> > > > expression exp;
> > > > constant gen;
> > > > @@
> > > > old(exp) == gen
> > > >
> > > > @script:python rename@
> > > > old << find.old;
> > > > gen << find.gen;
> > > > new;
> > > > @@
> > > > def do_rename(old, gen):
> > > > return "IS_GEN" + gen
> > > > coccinelle.new = cocci.make_ident(do_rename(old, gen))
> > > > print coccinelle.new
> > > >
> > > > @@
> > > > identifier find.old;
> > > > expression find.exp;
> > > > constant find.gen;
> > > > identifier rename.new;
> > > > @@
> > > > - old(exp) == gen
> > > > + new(exp)
> > > >
> > > >
> > > > I wish it would look something more like this:
> > > >
> > > > @@
> > > > identifier old =~ "^INTEL_GEN$";
> > > > expression exp;
> > > > constant gen;
> > > > fresh identifier new = "IS_GEN" ## gen;
> > > > @@
> > > > - old(exp) == gen
> > > > + new(exp)
> > > >
> > > > But coccinelle doesn't seem to accept the constant in the fresh
> > > > identifier thing.
> > > >
> > > >
> > > > Patch looks fine anyways
> > > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > >
> > > > >
> > > > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/i915/i915_drv.c | 2 +-
> > > > > drivers/gpu/drm/i915/intel_atomic.c | 2 +-
> > > > > drivers/gpu/drm/i915/intel_device_info.c | 6 +++---
> > > > > drivers/gpu/drm/i915/intel_display.c | 2 +-
> > > > > drivers/gpu/drm/i915/intel_dp.c | 2 +-
> > > > > drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
> > > > > drivers/gpu/drm/i915/intel_fbc.c | 2 +-
> > > > > drivers/gpu/drm/i915/intel_pm.c | 4 ++--
> > > > > drivers/gpu/drm/i915/intel_psr.c | 2 +-
> > > > > drivers/gpu/drm/i915/intel_ringbuffer.h | 4 ++--
> > > > > drivers/gpu/drm/i915/intel_sprite.c | 2 +-
> > > > > 11 files changed, 15 insertions(+), 15 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > > > > index baac35f698f9..d755e84fed07 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > > > @@ -1329,7 +1329,7 @@ intel_get_dram_info(struct drm_i915_private *dev_priv)
> > > > > /* Need to calculate bandwidth only for Gen9 */
> > > > > if (IS_BROXTON(dev_priv))
> > > > > ret = bxt_get_dram_info(dev_priv);
> > > > > - else if (INTEL_GEN(dev_priv) == 9)
> > > > > + else if (IS_GEN9(dev_priv))
> > > > > ret = skl_get_dram_info(dev_priv);
> > > > > else
> > > > > ret = skl_dram_get_channels_info(dev_priv);
> > > > > diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
> > > > > index 760758ad21c1..3526f6d9c1ad 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_atomic.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_atomic.c
> > > > > @@ -232,7 +232,7 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta
> > > > > if (plane_state && plane_state->base.fb &&
> > > > > plane_state->base.fb->format->is_yuv &&
> > > > > plane_state->base.fb->format->num_planes > 1) {
> > > > > - if (INTEL_GEN(dev_priv) == 9 &&
> > > > > + if (IS_GEN9(dev_priv) &&
> > > > > !IS_GEMINILAKE(dev_priv))
> > > > > mode = SKL_PS_SCALER_MODE_NV12;
> > > > > else
> > > > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> > > > > index 03df4e33763d..561ad0d4a53d 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > > > > @@ -744,7 +744,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
> > > > > if (INTEL_GEN(dev_priv) >= 10) {
> > > > > for_each_pipe(dev_priv, pipe)
> > > > > info->num_scalers[pipe] = 2;
> > > > > - } else if (INTEL_GEN(dev_priv) == 9) {
> > > > > + } else if (IS_GEN9(dev_priv)) {
> > > > > info->num_scalers[PIPE_A] = 2;
> > > > > info->num_scalers[PIPE_B] = 2;
> > > > > info->num_scalers[PIPE_C] = 1;
> > > > > @@ -843,9 +843,9 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
> > > > > cherryview_sseu_info_init(dev_priv);
> > > > > else if (IS_BROADWELL(dev_priv))
> > > > > broadwell_sseu_info_init(dev_priv);
> > > > > - else if (INTEL_GEN(dev_priv) == 9)
> > > > > + else if (IS_GEN9(dev_priv))
> > > > > gen9_sseu_info_init(dev_priv);
> > > > > - else if (INTEL_GEN(dev_priv) == 10)
> > > > > + else if (IS_GEN10(dev_priv))
> > > > > gen10_sseu_info_init(dev_priv);
> > > > > else if (INTEL_GEN(dev_priv) >= 11)
> > > > > gen11_sseu_info_init(dev_priv);
> > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > > > > index fc7e3b0bd95c..a6869c547f3c 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > > > @@ -5268,7 +5268,7 @@ static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
> > > > > if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
> > > > > return false;
> > > > >
> > > > > - if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) ||
> > > > > + if ((IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) ||
> > > > > IS_CANNONLAKE(dev_priv))
> > > > > return true;
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > > > > index 8c38efef77a1..761447c456c7 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > > > @@ -455,7 +455,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
> > > > > if (INTEL_GEN(dev_priv) >= 10) {
> > > > > source_rates = cnl_rates;
> > > > > size = ARRAY_SIZE(cnl_rates);
> > > > > - if (INTEL_GEN(dev_priv) == 10)
> > > > > + if (IS_GEN10(dev_priv))
> > > > > max_rate = cnl_max_source_rate(intel_dp);
> > > > > else
> > > > > max_rate = icl_max_source_rate(intel_dp);
> > > > > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> > > > > index 65f6c9bc10cf..a4b1d82c89da 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > > > > @@ -812,7 +812,7 @@ u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)
> > > > > u32 slice = fls(sseu->slice_mask);
> > > > > u32 subslice = fls(sseu->subslice_mask[slice]);
> > > > >
> > > > > - if (INTEL_GEN(dev_priv) == 10)
> > > > > + if (IS_GEN10(dev_priv))
> > > > > mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
> > > > > GEN8_MCR_SUBSLICE(subslice);
> > > > > else if (INTEL_GEN(dev_priv) >= 11)
> > > > > diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> > > > > index c90954cdfb15..96f70d896c10 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_fbc.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_fbc.c
> > > > > @@ -84,7 +84,7 @@ static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
> > > > > int lines;
> > > > >
> > > > > intel_fbc_get_plane_source_size(cache, NULL, &lines);
> > > > > - if (INTEL_GEN(dev_priv) == 7)
> > > > > + if (IS_GEN7(dev_priv))
> > > > > lines = min(lines, 2048);
> > > > > else if (INTEL_GEN(dev_priv) >= 8)
> > > > > lines = min(lines, 2560);
> > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > > index 67a4d0735291..3793866a9ee7 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > @@ -4676,13 +4676,13 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
> > > > > selected_result = method2;
> > > > > } else if (ddb_allocation >=
> > > > > fixed16_to_u32_round_up(wp->plane_blocks_per_line)) {
> > > > > - if (INTEL_GEN(dev_priv) == 9 &&
> > > > > + if (IS_GEN9(dev_priv) &&
> > > > > !IS_GEMINILAKE(dev_priv))
> > > > > selected_result = min_fixed16(method1, method2);
> > > > > else
> > > > > selected_result = method2;
> > > > > } else if (latency >= wp->linetime_us) {
> > > > > - if (INTEL_GEN(dev_priv) == 9 &&
> > > > > + if (IS_GEN9(dev_priv) &&
> > > > > !IS_GEMINILAKE(dev_priv))
> > > > > selected_result = min_fixed16(method1, method2);
> > > > > else
> > > > > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> > > > > index 423cdf84059c..bc2d88313ed0 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_psr.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > > > > @@ -574,7 +574,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
> > > > > if (dev_priv->psr.psr2_enabled) {
> > > > > u32 chicken = I915_READ(CHICKEN_TRANS(cpu_transcoder));
> > > > >
> > > > > - if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv))
> > > > > + if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv))
> > > > > chicken |= (PSR2_VSC_ENABLE_PROG_HEADER
> > > > > | PSR2_ADD_VERTICAL_LINE_COUNT);
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> > > > > index f6ec48a75a69..d3a08d0f02fe 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> > > > > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> > > > > @@ -93,11 +93,11 @@ hangcheck_action_to_str(const enum intel_engine_hangcheck_action a)
> > > > > #define I915_MAX_SUBSLICES 8
> > > > >
> > > > > #define instdone_slice_mask(dev_priv__) \
> > > > > - (INTEL_GEN(dev_priv__) == 7 ? \
> > > > > + (IS_GEN7(dev_priv__) ? \
> > > > > 1 : INTEL_INFO(dev_priv__)->sseu.slice_mask)
> > > > >
> > > > > #define instdone_subslice_mask(dev_priv__) \
> > > > > - (INTEL_GEN(dev_priv__) == 7 ? \
> > > > > + (IS_GEN7(dev_priv__) ? \
> > > > > 1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask[0])
> > > > >
> > > > > #define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
> > > > > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> > > > > index 7cd59eee5cad..4c9f0b7138b3 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > > > > @@ -1798,7 +1798,7 @@ static bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
> > > > > if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
> > > > > return false;
> > > > >
> > > > > - if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C)
> > > > > + if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C)
> > > > > return false;
> > > > >
> > > > > if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0)
> > > > > --
> > > > > 2.19.1
> > > > >
> > > > > _______________________________________________
> > > > > Intel-gfx mailing list
> > > > > Intel-gfx@lists.freedesktop.org
> > > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > > >
> > > > --
> > > > Ville Syrjälä
> > > > Intel
> >
> > --
> > Ville Syrjälä
> > Intel
> >
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [RFC 2/3] drm/i915: Prefer IS_GEN<n> check with bitmask.
2018-10-26 19:40 ` Rodrigo Vivi
@ 2018-10-26 19:47 ` Julia Lawall
2018-10-26 19:55 ` Rodrigo Vivi
0 siblings, 1 reply; 18+ messages in thread
From: Julia Lawall @ 2018-10-26 19:47 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 3574 bytes --]
On Fri, 26 Oct 2018, Rodrigo Vivi wrote:
> On Thu, Oct 25, 2018 at 12:11:57PM +0100, Julia Lawall wrote:
> >
> >
> > On Thu, 25 Oct 2018, Ville Syrjälä wrote:
> >
> > > On Wed, Oct 24, 2018 at 04:41:06PM -0700, Rodrigo Vivi wrote:
> > > > On Wed, Oct 24, 2018 at 01:22:57PM +0300, Ville Syrjälä wrote:
> > > > > On Tue, Oct 23, 2018 at 04:36:19PM -0700, Rodrigo Vivi wrote:
> > > > > > Whenever possible we should stick with IS_GEN<n> checks.
> > > > > >
> > > > > > Bitmaks has been introduced on commit ae7617f0ef18 ("drm/i915:
> > > > > > Allow optimized platform checks") for efficiency.
> > > > > >
> > > > > > Let's stick with it whenever possible.
> > > > > >
> > > > > > This patch was generated with coccinelle:
> > > > > >
> > > > > > spatch -sp_file is_gen.cocci *{c,h} --in-place
> > > > > >
> > > > > > is_gen.cocci:
> > > > > > @gen2@ expression e; @@
> > > > > > -INTEL_GEN(e) == 2
> > > > > > +IS_GEN2(e)
> > > > > > @gen3@ expression e; @@
> > > > > > -INTEL_GEN(e) == 3
> > > > > > +IS_GEN3(e)
> > > > > > @gen4@ expression e; @@
> > > > > > -INTEL_GEN(e) == 4
> > > > > > +IS_GEN4(e)
> > > > > > @gen5@ expression e; @@
> > > > > > -INTEL_GEN(e) == 5
> > > > > > +IS_GEN5(e)
> > > > > > @gen6@ expression e; @@
> > > > > > -INTEL_GEN(e) == 6
> > > > > > +IS_GEN6(e)
> > > > > > @gen7@ expression e; @@
> > > > > > -INTEL_GEN(e) == 7
> > > > > > +IS_GEN7(e)
> > > > > > @gen8@ expression e; @@
> > > > > > -INTEL_GEN(e) == 8
> > > > > > +IS_GEN8(e)
> > > > > > @gen9@ expression e; @@
> > > > > > -INTEL_GEN(e) == 9
> > > > > > +IS_GEN9(e)
> > > > > > @gen10@ expression e; @@
> > > > > > -INTEL_GEN(e) == 10
> > > > > > +IS_GEN10(e)
> > > > > > @gen11@ expression e; @@
> > > > > > -INTEL_GEN(e) == 11
> > > > > > +IS_GEN11(e)
> > > > >
> > > > > Slightly less repetitive version.
> > > >
> > > > Thanks. I'm supper newbie on coccinelle and it was
> > > > easier to duplicate then trying to learn all this new lang.
> > > >
> > > > But I really appreciate you sharing this. I'd like
> > > > to go with this so the better rule keeps on commit message.
> > > >
> > > > > Sadly not super neat on
> > > > > account of having to use the python stuff.
> > > >
> > > > however it seems python version didn't work so well here:
> > > >
> > > > init_defs_builtins: /usr/lib64/coccinelle/standard.h
> > > > Python error: No module named coccilib.elems
> > > >
> > > > do you have any idea about it?
> > >
> > > Never seen it. On gentoo it just works when I have the python
> > > use flag enabled.
> > >
> > > Maybe your distro doesn't include the python support in the
> > > build, or maybe some kind of python version issue?
> >
> > Thanks for the report. I will have someone look into it. It's an
> > internal Coccinelle thing. Perhaps python is not enabled. Do you have
> > the version of Coccinelle from github?
>
> I just tried with coccinelle from github but got same result.
>
> But with this commit before the bump to automake1.16:
>
> commit 4db95998768557c66d6e337be2253032b5d810bc (HEAD -> master)
> Author: Thierry Martinez <thierry.martinez@inria.fr>
> Date: Wed Sep 12 14:43:41 2018 +0200
>
> Compute depend by calling make recursilevy
>
> The set of files in $(source_files) may change when the tarball is
> unpacked.
>
> ----
>
> $ python --version
> Python 2.7.15
> $ python3 --version
> Python 3.6.6
>
> ----
>
> I believe I'm moving this patch with the repetitive bad
> rule for now that I'm sure it works in most of the distros.
Sorry, I'm not sure to understand the last sentence. Are things ok now, or
not?
thanks,
julia
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [RFC 2/3] drm/i915: Prefer IS_GEN<n> check with bitmask.
2018-10-26 19:47 ` Julia Lawall
@ 2018-10-26 19:55 ` Rodrigo Vivi
0 siblings, 0 replies; 18+ messages in thread
From: Rodrigo Vivi @ 2018-10-26 19:55 UTC (permalink / raw)
To: Julia Lawall; +Cc: intel-gfx
On Fri, Oct 26, 2018 at 09:47:05PM +0200, Julia Lawall wrote:
>
>
> On Fri, 26 Oct 2018, Rodrigo Vivi wrote:
>
> > On Thu, Oct 25, 2018 at 12:11:57PM +0100, Julia Lawall wrote:
> > >
> > >
> > > On Thu, 25 Oct 2018, Ville Syrjälä wrote:
> > >
> > > > On Wed, Oct 24, 2018 at 04:41:06PM -0700, Rodrigo Vivi wrote:
> > > > > On Wed, Oct 24, 2018 at 01:22:57PM +0300, Ville Syrjälä wrote:
> > > > > > On Tue, Oct 23, 2018 at 04:36:19PM -0700, Rodrigo Vivi wrote:
> > > > > > > Whenever possible we should stick with IS_GEN<n> checks.
> > > > > > >
> > > > > > > Bitmaks has been introduced on commit ae7617f0ef18 ("drm/i915:
> > > > > > > Allow optimized platform checks") for efficiency.
> > > > > > >
> > > > > > > Let's stick with it whenever possible.
> > > > > > >
> > > > > > > This patch was generated with coccinelle:
> > > > > > >
> > > > > > > spatch -sp_file is_gen.cocci *{c,h} --in-place
> > > > > > >
> > > > > > > is_gen.cocci:
> > > > > > > @gen2@ expression e; @@
> > > > > > > -INTEL_GEN(e) == 2
> > > > > > > +IS_GEN2(e)
> > > > > > > @gen3@ expression e; @@
> > > > > > > -INTEL_GEN(e) == 3
> > > > > > > +IS_GEN3(e)
> > > > > > > @gen4@ expression e; @@
> > > > > > > -INTEL_GEN(e) == 4
> > > > > > > +IS_GEN4(e)
> > > > > > > @gen5@ expression e; @@
> > > > > > > -INTEL_GEN(e) == 5
> > > > > > > +IS_GEN5(e)
> > > > > > > @gen6@ expression e; @@
> > > > > > > -INTEL_GEN(e) == 6
> > > > > > > +IS_GEN6(e)
> > > > > > > @gen7@ expression e; @@
> > > > > > > -INTEL_GEN(e) == 7
> > > > > > > +IS_GEN7(e)
> > > > > > > @gen8@ expression e; @@
> > > > > > > -INTEL_GEN(e) == 8
> > > > > > > +IS_GEN8(e)
> > > > > > > @gen9@ expression e; @@
> > > > > > > -INTEL_GEN(e) == 9
> > > > > > > +IS_GEN9(e)
> > > > > > > @gen10@ expression e; @@
> > > > > > > -INTEL_GEN(e) == 10
> > > > > > > +IS_GEN10(e)
> > > > > > > @gen11@ expression e; @@
> > > > > > > -INTEL_GEN(e) == 11
> > > > > > > +IS_GEN11(e)
> > > > > >
> > > > > > Slightly less repetitive version.
> > > > >
> > > > > Thanks. I'm supper newbie on coccinelle and it was
> > > > > easier to duplicate then trying to learn all this new lang.
> > > > >
> > > > > But I really appreciate you sharing this. I'd like
> > > > > to go with this so the better rule keeps on commit message.
> > > > >
> > > > > > Sadly not super neat on
> > > > > > account of having to use the python stuff.
> > > > >
> > > > > however it seems python version didn't work so well here:
> > > > >
> > > > > init_defs_builtins: /usr/lib64/coccinelle/standard.h
> > > > > Python error: No module named coccilib.elems
> > > > >
> > > > > do you have any idea about it?
> > > >
> > > > Never seen it. On gentoo it just works when I have the python
> > > > use flag enabled.
> > > >
> > > > Maybe your distro doesn't include the python support in the
> > > > build, or maybe some kind of python version issue?
> > >
> > > Thanks for the report. I will have someone look into it. It's an
> > > internal Coccinelle thing. Perhaps python is not enabled. Do you have
> > > the version of Coccinelle from github?
> >
> > I just tried with coccinelle from github but got same result.
> >
> > But with this commit before the bump to automake1.16:
> >
> > commit 4db95998768557c66d6e337be2253032b5d810bc (HEAD -> master)
> > Author: Thierry Martinez <thierry.martinez@inria.fr>
> > Date: Wed Sep 12 14:43:41 2018 +0200
> >
> > Compute depend by calling make recursilevy
> >
> > The set of files in $(source_files) may change when the tarball is
> > unpacked.
> >
> > ----
> >
> > $ python --version
> > Python 2.7.15
> > $ python3 --version
> > Python 3.6.6
> >
> > ----
> >
> > I believe I'm moving this patch with the repetitive bad
> > rule for now that I'm sure it works in most of the distros.
>
> Sorry, I'm not sure to understand the last sentence. Are things ok now, or
> not?
Well, I'd like to learn more and be able to run the python rules
on my system. So if you still have any idea I'd like to listen.
But I don't see any rush on that since for this patch
we can go with the simple repetitive rule that works on default
coccinelle that comes with fedora 28.
In other words, for this patch we are good.
For the future I'd like to learn, but with no pressure or rush!
I really appreciate your support
Thanks a lot,
Rodrigo.
>
> thanks,
> julia
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [RFC 1/3] drm/i915: Rename IS_GEN to IS_GEN_RANGE.
2018-10-23 23:36 [RFC 1/3] drm/i915: Rename IS_GEN to IS_GEN_RANGE Rodrigo Vivi
` (4 preceding siblings ...)
2018-10-24 4:50 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-10-29 10:19 ` Jani Nikula
2018-10-29 17:52 ` Rodrigo Vivi
5 siblings, 1 reply; 18+ messages in thread
From: Jani Nikula @ 2018-10-29 10:19 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
On Tue, 23 Oct 2018, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> RANGE makes it longer, but clear.
IS_GEN_RANGE() was the first proposal, but in review this was changed to
IS_GEN() following IS_REVID() and IS_<platform>_REVID().
IMO unnecessary change.
BR,
Jani.
>
> Diff generated with:
>
> sed 's/IS_GEN(/IS_GEN_RANGE(/g' drivers/gpu/drm/i915/*.{c,h} -i
>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_perf.c | 4 ++--
> drivers/gpu/drm/i915/intel_bios.c | 2 +-
> drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/intel_fbc.c | 2 +-
> drivers/gpu/drm/i915/intel_hangcheck.c | 2 +-
> drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++----
> drivers/gpu/drm/i915/intel_uncore.c | 12 ++++++------
> 9 files changed, 18 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 5b37d5f8e132..3deab30388f2 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2919,7 +2919,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
> if (IS_BROXTON(dev_priv)) {
> seq_printf(m, "DC3 -> DC5 count: %d\n",
> I915_READ(BXT_CSR_DC3_DC5_COUNT));
> - } else if (IS_GEN(dev_priv, 9, 11)) {
> + } else if (IS_GEN_RANGE(dev_priv, 9, 11)) {
> seq_printf(m, "DC3 -> DC5 count: %d\n",
> I915_READ(SKL_CSR_DC3_DC5_COUNT));
> seq_printf(m, "DC5 -> DC6 count: %d\n",
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3017ef037fed..f766bb1e873b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2387,7 +2387,7 @@ intel_info(const struct drm_i915_private *dev_priv)
> *
> * Use GEN_FOREVER for unbound start and or end.
> */
> -#define IS_GEN(dev_priv, s, e) \
> +#define IS_GEN_RANGE(dev_priv, s, e) \
> (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
>
> /*
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 664b96bb65a3..0888b6e6080f 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -1795,7 +1795,7 @@ static int gen8_enable_metric_set(struct drm_i915_private *dev_priv,
> * be read back from automatically triggered reports, as part of the
> * RPT_ID field.
> */
> - if (IS_GEN(dev_priv, 9, 11)) {
> + if (IS_GEN_RANGE(dev_priv, 9, 11)) {
> I915_WRITE(GEN8_OA_DEBUG,
> _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
> GEN9_OA_DEBUG_INCLUDE_CLK_RATIO));
> @@ -3439,7 +3439,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
>
> dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16);
> }
> - } else if (IS_GEN(dev_priv, 10, 11)) {
> + } else if (IS_GEN_RANGE(dev_priv, 10, 11)) {
> dev_priv->perf.oa.ops.is_valid_b_counter_reg =
> gen7_is_valid_b_counter_addr;
> dev_priv->perf.oa.ops.is_valid_mux_reg =
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index 1faa494e2bc9..43cf0b026143 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -446,7 +446,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, u8 bdb_version)
> * Only parse SDVO mappings on gens that could have SDVO. This isn't
> * accurate and doesn't have to be, as long as it's not too strict.
> */
> - if (!IS_GEN(dev_priv, 3, 7)) {
> + if (!IS_GEN_RANGE(dev_priv, 3, 7)) {
> DRM_DEBUG_KMS("Skipping SDVO device mapping\n");
> return;
> }
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 8bfab22068a3..65f6c9bc10cf 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1286,7 +1286,7 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine,
> &engine->execlists;
> u64 addr;
>
> - if (engine->id == RCS && IS_GEN(dev_priv, 4, 7))
> + if (engine->id == RCS && IS_GEN_RANGE(dev_priv, 4, 7))
> drm_printf(m, "\tCCID: 0x%08x\n", I915_READ(CCID));
> drm_printf(m, "\tRING_START: 0x%08x\n",
> I915_READ(RING_START(engine->mmio_base)));
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> index e3cfc3c176e7..c90954cdfb15 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -784,7 +784,7 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
> * having a Y offset that isn't divisible by 4 causes FIFO underrun
> * and screen flicker.
> */
> - if (IS_GEN(dev_priv, 9, 10) &&
> + if (IS_GEN_RANGE(dev_priv, 9, 10) &&
> (fbc->state_cache.plane.adjusted_y & 3)) {
> fbc->no_fbc_reason = "plane Y offset is misaligned";
> return false;
> diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c
> index e26d05a46451..41921a843d42 100644
> --- a/drivers/gpu/drm/i915/intel_hangcheck.c
> +++ b/drivers/gpu/drm/i915/intel_hangcheck.c
> @@ -252,7 +252,7 @@ engine_stuck(struct intel_engine_cs *engine, u64 acthd)
> return ENGINE_WAIT_KICK;
> }
>
> - if (IS_GEN(dev_priv, 6, 7) && tmp & RING_WAIT_SEMAPHORE) {
> + if (IS_GEN_RANGE(dev_priv, 6, 7) && tmp & RING_WAIT_SEMAPHORE) {
> switch (semaphore_passed(engine)) {
> default:
> return ENGINE_DEAD;
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index b8a7a014d46d..608e5c65b655 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -407,7 +407,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
> POSTING_READ(mmio);
>
> /* Flush the TLB for this page */
> - if (IS_GEN(dev_priv, 6, 7)) {
> + if (IS_GEN_RANGE(dev_priv, 6, 7)) {
> i915_reg_t reg = RING_INSTPM(engine->mmio_base);
>
> /* ring should be idle before issuing a sync flush*/
> @@ -629,7 +629,7 @@ static int init_render_ring(struct intel_engine_cs *engine)
> intel_whitelist_workarounds_apply(engine);
>
> /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
> - if (IS_GEN(dev_priv, 4, 6))
> + if (IS_GEN_RANGE(dev_priv, 4, 6))
> I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
>
> /* We need to disable the AsyncFlip performance optimisations in order
> @@ -638,7 +638,7 @@ static int init_render_ring(struct intel_engine_cs *engine)
> *
> * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
> */
> - if (IS_GEN(dev_priv, 6, 7))
> + if (IS_GEN_RANGE(dev_priv, 6, 7))
> I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
>
> /* Required for the hardware to program scanline values for waiting */
> @@ -663,7 +663,7 @@ static int init_render_ring(struct intel_engine_cs *engine)
> _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
> }
>
> - if (IS_GEN(dev_priv, 6, 7))
> + if (IS_GEN_RANGE(dev_priv, 6, 7))
> I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
>
> if (INTEL_GEN(dev_priv) >= 6)
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 9289515108c3..631b4165fe00 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1567,13 +1567,13 @@ void intel_uncore_init(struct drm_i915_private *dev_priv)
> dev_priv->uncore.pmic_bus_access_nb.notifier_call =
> i915_pmic_bus_access_notifier;
>
> - if (IS_GEN(dev_priv, 2, 4) || intel_vgpu_active(dev_priv)) {
> + if (IS_GEN_RANGE(dev_priv, 2, 4) || intel_vgpu_active(dev_priv)) {
> ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen2);
> ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen2);
> } else if (IS_GEN5(dev_priv)) {
> ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen5);
> ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen5);
> - } else if (IS_GEN(dev_priv, 6, 7)) {
> + } else if (IS_GEN_RANGE(dev_priv, 6, 7)) {
> ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen6);
>
> if (IS_VALLEYVIEW(dev_priv)) {
> @@ -1592,7 +1592,7 @@ void intel_uncore_init(struct drm_i915_private *dev_priv)
> ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen8);
> ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen6);
> }
> - } else if (IS_GEN(dev_priv, 9, 10)) {
> + } else if (IS_GEN_RANGE(dev_priv, 9, 10)) {
> ASSIGN_FW_DOMAINS_TABLE(__gen9_fw_ranges);
> ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, fwtable);
> ASSIGN_READ_MMIO_VFUNCS(dev_priv, fwtable);
> @@ -2321,7 +2321,7 @@ intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv,
> } else if (INTEL_GEN(dev_priv) >= 6) {
> fw_domains = __gen6_reg_read_fw_domains(offset);
> } else {
> - WARN_ON(!IS_GEN(dev_priv, 2, 5));
> + WARN_ON(!IS_GEN_RANGE(dev_priv, 2, 5));
> fw_domains = 0;
> }
>
> @@ -2343,10 +2343,10 @@ intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv,
> fw_domains = __fwtable_reg_write_fw_domains(offset);
> } else if (IS_GEN8(dev_priv)) {
> fw_domains = __gen8_reg_write_fw_domains(offset);
> - } else if (IS_GEN(dev_priv, 6, 7)) {
> + } else if (IS_GEN_RANGE(dev_priv, 6, 7)) {
> fw_domains = FORCEWAKE_RENDER;
> } else {
> - WARN_ON(!IS_GEN(dev_priv, 2, 5));
> + WARN_ON(!IS_GEN_RANGE(dev_priv, 2, 5));
> fw_domains = 0;
> }
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [RFC 1/3] drm/i915: Rename IS_GEN to IS_GEN_RANGE.
2018-10-29 10:19 ` [RFC 1/3] " Jani Nikula
@ 2018-10-29 17:52 ` Rodrigo Vivi
0 siblings, 0 replies; 18+ messages in thread
From: Rodrigo Vivi @ 2018-10-29 17:52 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Mon, Oct 29, 2018 at 12:19:37PM +0200, Jani Nikula wrote:
> On Tue, 23 Oct 2018, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> > RANGE makes it longer, but clear.
>
> IS_GEN_RANGE() was the first proposal, but in review this was changed to
> IS_GEN() following IS_REVID() and IS_<platform>_REVID().
>
> IMO unnecessary change.
consider this one dropped then.
other 2 patches from this series got pushed.
Thanks,
Rodrigo.
>
> BR,
> Jani.
>
> >
> > Diff generated with:
> >
> > sed 's/IS_GEN(/IS_GEN_RANGE(/g' drivers/gpu/drm/i915/*.{c,h} -i
> >
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
> > drivers/gpu/drm/i915/i915_drv.h | 2 +-
> > drivers/gpu/drm/i915/i915_perf.c | 4 ++--
> > drivers/gpu/drm/i915/intel_bios.c | 2 +-
> > drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
> > drivers/gpu/drm/i915/intel_fbc.c | 2 +-
> > drivers/gpu/drm/i915/intel_hangcheck.c | 2 +-
> > drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++----
> > drivers/gpu/drm/i915/intel_uncore.c | 12 ++++++------
> > 9 files changed, 18 insertions(+), 18 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 5b37d5f8e132..3deab30388f2 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -2919,7 +2919,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
> > if (IS_BROXTON(dev_priv)) {
> > seq_printf(m, "DC3 -> DC5 count: %d\n",
> > I915_READ(BXT_CSR_DC3_DC5_COUNT));
> > - } else if (IS_GEN(dev_priv, 9, 11)) {
> > + } else if (IS_GEN_RANGE(dev_priv, 9, 11)) {
> > seq_printf(m, "DC3 -> DC5 count: %d\n",
> > I915_READ(SKL_CSR_DC3_DC5_COUNT));
> > seq_printf(m, "DC5 -> DC6 count: %d\n",
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 3017ef037fed..f766bb1e873b 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -2387,7 +2387,7 @@ intel_info(const struct drm_i915_private *dev_priv)
> > *
> > * Use GEN_FOREVER for unbound start and or end.
> > */
> > -#define IS_GEN(dev_priv, s, e) \
> > +#define IS_GEN_RANGE(dev_priv, s, e) \
> > (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
> >
> > /*
> > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> > index 664b96bb65a3..0888b6e6080f 100644
> > --- a/drivers/gpu/drm/i915/i915_perf.c
> > +++ b/drivers/gpu/drm/i915/i915_perf.c
> > @@ -1795,7 +1795,7 @@ static int gen8_enable_metric_set(struct drm_i915_private *dev_priv,
> > * be read back from automatically triggered reports, as part of the
> > * RPT_ID field.
> > */
> > - if (IS_GEN(dev_priv, 9, 11)) {
> > + if (IS_GEN_RANGE(dev_priv, 9, 11)) {
> > I915_WRITE(GEN8_OA_DEBUG,
> > _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
> > GEN9_OA_DEBUG_INCLUDE_CLK_RATIO));
> > @@ -3439,7 +3439,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
> >
> > dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16);
> > }
> > - } else if (IS_GEN(dev_priv, 10, 11)) {
> > + } else if (IS_GEN_RANGE(dev_priv, 10, 11)) {
> > dev_priv->perf.oa.ops.is_valid_b_counter_reg =
> > gen7_is_valid_b_counter_addr;
> > dev_priv->perf.oa.ops.is_valid_mux_reg =
> > diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> > index 1faa494e2bc9..43cf0b026143 100644
> > --- a/drivers/gpu/drm/i915/intel_bios.c
> > +++ b/drivers/gpu/drm/i915/intel_bios.c
> > @@ -446,7 +446,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, u8 bdb_version)
> > * Only parse SDVO mappings on gens that could have SDVO. This isn't
> > * accurate and doesn't have to be, as long as it's not too strict.
> > */
> > - if (!IS_GEN(dev_priv, 3, 7)) {
> > + if (!IS_GEN_RANGE(dev_priv, 3, 7)) {
> > DRM_DEBUG_KMS("Skipping SDVO device mapping\n");
> > return;
> > }
> > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> > index 8bfab22068a3..65f6c9bc10cf 100644
> > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > @@ -1286,7 +1286,7 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine,
> > &engine->execlists;
> > u64 addr;
> >
> > - if (engine->id == RCS && IS_GEN(dev_priv, 4, 7))
> > + if (engine->id == RCS && IS_GEN_RANGE(dev_priv, 4, 7))
> > drm_printf(m, "\tCCID: 0x%08x\n", I915_READ(CCID));
> > drm_printf(m, "\tRING_START: 0x%08x\n",
> > I915_READ(RING_START(engine->mmio_base)));
> > diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> > index e3cfc3c176e7..c90954cdfb15 100644
> > --- a/drivers/gpu/drm/i915/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/intel_fbc.c
> > @@ -784,7 +784,7 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
> > * having a Y offset that isn't divisible by 4 causes FIFO underrun
> > * and screen flicker.
> > */
> > - if (IS_GEN(dev_priv, 9, 10) &&
> > + if (IS_GEN_RANGE(dev_priv, 9, 10) &&
> > (fbc->state_cache.plane.adjusted_y & 3)) {
> > fbc->no_fbc_reason = "plane Y offset is misaligned";
> > return false;
> > diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c
> > index e26d05a46451..41921a843d42 100644
> > --- a/drivers/gpu/drm/i915/intel_hangcheck.c
> > +++ b/drivers/gpu/drm/i915/intel_hangcheck.c
> > @@ -252,7 +252,7 @@ engine_stuck(struct intel_engine_cs *engine, u64 acthd)
> > return ENGINE_WAIT_KICK;
> > }
> >
> > - if (IS_GEN(dev_priv, 6, 7) && tmp & RING_WAIT_SEMAPHORE) {
> > + if (IS_GEN_RANGE(dev_priv, 6, 7) && tmp & RING_WAIT_SEMAPHORE) {
> > switch (semaphore_passed(engine)) {
> > default:
> > return ENGINE_DEAD;
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index b8a7a014d46d..608e5c65b655 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -407,7 +407,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
> > POSTING_READ(mmio);
> >
> > /* Flush the TLB for this page */
> > - if (IS_GEN(dev_priv, 6, 7)) {
> > + if (IS_GEN_RANGE(dev_priv, 6, 7)) {
> > i915_reg_t reg = RING_INSTPM(engine->mmio_base);
> >
> > /* ring should be idle before issuing a sync flush*/
> > @@ -629,7 +629,7 @@ static int init_render_ring(struct intel_engine_cs *engine)
> > intel_whitelist_workarounds_apply(engine);
> >
> > /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
> > - if (IS_GEN(dev_priv, 4, 6))
> > + if (IS_GEN_RANGE(dev_priv, 4, 6))
> > I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
> >
> > /* We need to disable the AsyncFlip performance optimisations in order
> > @@ -638,7 +638,7 @@ static int init_render_ring(struct intel_engine_cs *engine)
> > *
> > * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
> > */
> > - if (IS_GEN(dev_priv, 6, 7))
> > + if (IS_GEN_RANGE(dev_priv, 6, 7))
> > I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
> >
> > /* Required for the hardware to program scanline values for waiting */
> > @@ -663,7 +663,7 @@ static int init_render_ring(struct intel_engine_cs *engine)
> > _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
> > }
> >
> > - if (IS_GEN(dev_priv, 6, 7))
> > + if (IS_GEN_RANGE(dev_priv, 6, 7))
> > I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
> >
> > if (INTEL_GEN(dev_priv) >= 6)
> > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> > index 9289515108c3..631b4165fe00 100644
> > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > @@ -1567,13 +1567,13 @@ void intel_uncore_init(struct drm_i915_private *dev_priv)
> > dev_priv->uncore.pmic_bus_access_nb.notifier_call =
> > i915_pmic_bus_access_notifier;
> >
> > - if (IS_GEN(dev_priv, 2, 4) || intel_vgpu_active(dev_priv)) {
> > + if (IS_GEN_RANGE(dev_priv, 2, 4) || intel_vgpu_active(dev_priv)) {
> > ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen2);
> > ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen2);
> > } else if (IS_GEN5(dev_priv)) {
> > ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen5);
> > ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen5);
> > - } else if (IS_GEN(dev_priv, 6, 7)) {
> > + } else if (IS_GEN_RANGE(dev_priv, 6, 7)) {
> > ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen6);
> >
> > if (IS_VALLEYVIEW(dev_priv)) {
> > @@ -1592,7 +1592,7 @@ void intel_uncore_init(struct drm_i915_private *dev_priv)
> > ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen8);
> > ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen6);
> > }
> > - } else if (IS_GEN(dev_priv, 9, 10)) {
> > + } else if (IS_GEN_RANGE(dev_priv, 9, 10)) {
> > ASSIGN_FW_DOMAINS_TABLE(__gen9_fw_ranges);
> > ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, fwtable);
> > ASSIGN_READ_MMIO_VFUNCS(dev_priv, fwtable);
> > @@ -2321,7 +2321,7 @@ intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv,
> > } else if (INTEL_GEN(dev_priv) >= 6) {
> > fw_domains = __gen6_reg_read_fw_domains(offset);
> > } else {
> > - WARN_ON(!IS_GEN(dev_priv, 2, 5));
> > + WARN_ON(!IS_GEN_RANGE(dev_priv, 2, 5));
> > fw_domains = 0;
> > }
> >
> > @@ -2343,10 +2343,10 @@ intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv,
> > fw_domains = __fwtable_reg_write_fw_domains(offset);
> > } else if (IS_GEN8(dev_priv)) {
> > fw_domains = __gen8_reg_write_fw_domains(offset);
> > - } else if (IS_GEN(dev_priv, 6, 7)) {
> > + } else if (IS_GEN_RANGE(dev_priv, 6, 7)) {
> > fw_domains = FORCEWAKE_RENDER;
> > } else {
> > - WARN_ON(!IS_GEN(dev_priv, 2, 5));
> > + WARN_ON(!IS_GEN_RANGE(dev_priv, 2, 5));
> > fw_domains = 0;
> > }
>
> --
> Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2018-10-29 17:52 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-10-23 23:36 [RFC 1/3] drm/i915: Rename IS_GEN to IS_GEN_RANGE Rodrigo Vivi
2018-10-23 23:36 ` [RFC 2/3] drm/i915: Prefer IS_GEN<n> check with bitmask Rodrigo Vivi
2018-10-24 10:22 ` Ville Syrjälä
2018-10-24 14:54 ` Julia Lawall
2018-10-24 15:15 ` Ville Syrjälä
2018-10-24 23:41 ` Rodrigo Vivi
2018-10-25 10:59 ` Ville Syrjälä
2018-10-25 11:11 ` Julia Lawall
2018-10-26 19:40 ` Rodrigo Vivi
2018-10-26 19:47 ` Julia Lawall
2018-10-26 19:55 ` Rodrigo Vivi
2018-10-23 23:36 ` [RFC 3/3] drm/i915: Kill GEN_FOREVER Rodrigo Vivi
2018-10-24 12:31 ` Daniel Vetter
2018-10-23 23:50 ` ✗ Fi.CI.SPARSE: warning for series starting with [RFC,1/3] drm/i915: Rename IS_GEN to IS_GEN_RANGE Patchwork
2018-10-24 0:07 ` ✓ Fi.CI.BAT: success " Patchwork
2018-10-24 4:50 ` ✓ Fi.CI.IGT: " Patchwork
2018-10-29 10:19 ` [RFC 1/3] " Jani Nikula
2018-10-29 17:52 ` Rodrigo Vivi
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