From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: From: Chris Brandt Subject: [PATCH v5 1/3] clk: renesas: r7s9210: Add SDHI clocks Date: Wed, 24 Oct 2018 17:22:59 -0500 Message-Id: <20181024222301.21455-2-chris.brandt@renesas.com> In-Reply-To: <20181024222301.21455-1-chris.brandt@renesas.com> References: <20181024222301.21455-1-chris.brandt@renesas.com> To: Ulf Hansson , Rob Herring , Mark Rutland , Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: Wolfram Sang , linux-clk@vger.kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Chris Brandt List-ID: Add SDHI clocks for RZ/A2 Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven --- (Geert will apply to his tree) --- drivers/clk/renesas/r7s9210-cpg-mssr.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clk/renesas/r7s9210-cpg-mssr.c b/drivers/clk/renesas/r7s9210-cpg-mssr.c index 5135f13ec628..9056da15dc72 100644 --- a/drivers/clk/renesas/r7s9210-cpg-mssr.c +++ b/drivers/clk/renesas/r7s9210-cpg-mssr.c @@ -98,6 +98,11 @@ static const struct mssr_mod_clk r7s9210_mod_clks[] __initconst = { DEF_MOD_STB("spi2", 95, R7S9210_CLK_P1), DEF_MOD_STB("spi1", 96, R7S9210_CLK_P1), DEF_MOD_STB("spi0", 97, R7S9210_CLK_P1), + + DEF_MOD_STB("sdhi11", 100, R7S9210_CLK_B), + DEF_MOD_STB("sdhi10", 101, R7S9210_CLK_B), + DEF_MOD_STB("sdhi01", 102, R7S9210_CLK_B), + DEF_MOD_STB("sdhi00", 103, R7S9210_CLK_B), }; /* The clock dividers in the table vary based on DT and register settings */ -- 2.16.1