From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Mon, 29 Oct 2018 07:06:41 +0100 Subject: [U-Boot] [PATCH v5 13/13] aspeed: ast2500: fix D2-PLL clock setting in RGMII mode In-Reply-To: <20181029060641.13824-1-clg@kaod.org> References: <20181029060641.13824-1-clg@kaod.org> Message-ID: <20181029060641.13824-14-clg@kaod.org> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable To: u-boot@lists.denx.de The algorithm in the ast2500_calc_clock_config() routine suffers from integer rounding and the requested rate does not get the appropriate set of Numerator, Denumerator, Post Divider parameters. This is the case for the D2-PLL clock used by the MAC controllers in RGMII mode. The requested rated is 250MHz but a 251MHz is assigned. The easiest way to fix this problem is to introduce an array of clock settings defining the N, M, P parameters for well known frequencies used by the Aspeed SoC. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Simon Glass Reviewed-by: Joel Stanley Acked-by: Joe Hershberger --- drivers/clk/aspeed/clk_ast2500.c | 38 ++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2= 500.c index 2182320f607f..dbee13a18297 100644 --- a/drivers/clk/aspeed/clk_ast2500.c +++ b/drivers/clk/aspeed/clk_ast2500.c @@ -165,6 +165,35 @@ static ulong ast2500_clk_get_rate(struct clk *clk) return rate; } =20 +struct ast2500_clock_config { + ulong input_rate; + ulong rate; + struct ast2500_div_config cfg; +}; + +static const struct ast2500_clock_config ast2500_clock_config_defaults[] = =3D { + { 24000000, 250000000, { .num =3D 124, .denum =3D 1, .post_div =3D 5 } }, +}; + +static bool ast2500_get_clock_config_default(ulong input_rate, + ulong requested_rate, + struct ast2500_div_config *cfg) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(ast2500_clock_config_defaults); i++) { + const struct ast2500_clock_config *default_cfg =3D + &ast2500_clock_config_defaults[i]; + if (default_cfg->input_rate =3D=3D input_rate && + default_cfg->rate =3D=3D requested_rate) { + *cfg =3D default_cfg->cfg; + return true; + } + } + + return false; +} + /* * @input_rate - the rate of input clock in Hz * @requested_rate - desired output rate in Hz @@ -189,6 +218,12 @@ static ulong ast2500_calc_clock_config(ulong input_rat= e, ulong requested_rate, ulong delta =3D rate_khz; ulong new_rate_khz =3D 0; =20 + /* + * Look for a well known frequency first. + */ + if (ast2500_get_clock_config_default(input_rate, requested_rate, cfg)) + return requested_rate; + for (; it.denum <=3D max_vals.denum; ++it.denum) { for (it.post_div =3D 0; it.post_div <=3D max_vals.post_div; ++it.post_div) { @@ -318,6 +353,9 @@ static ulong ast2500_configure_d2pll(struct ast2500_scu= *scu, ulong rate) /* * The values and the meaning of the next three * parameters are undocumented. Taken from Aspeed SDK. + * + * TODO(clg@kaod.org): the SIP and SIC values depend on the + * Numerator value */ const u32 d2_pll_ext_param =3D 0x2c; const u32 d2_pll_sip =3D 0x11; --=20 2.17.2