From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C15DC46475 for ; Mon, 29 Oct 2018 07:26:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 241692080A for ; Mon, 29 Oct 2018 07:26:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b="fUhqPpuk" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 241692080A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=alliedtelesis.co.nz Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729504AbeJ2QNz (ORCPT ); Mon, 29 Oct 2018 12:13:55 -0400 Received: from gate2.alliedtelesis.co.nz ([202.36.163.20]:51824 "EHLO gate2.alliedtelesis.co.nz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729370AbeJ2QNZ (ORCPT ); Mon, 29 Oct 2018 12:13:25 -0400 Received: from mmarshal3.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id D1E048781F; Mon, 29 Oct 2018 20:25:53 +1300 (NZDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1540797953; bh=aa81lk+tnvlI+U6sRrADkZjfMbd7061EJ7B4jRO4Mkw=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=fUhqPpuk6HVATv7DZN19baA3cvUvop8ygtGR1P9zfdqBYEbLc+qH+Bol3n72xlAuT tu9V8J63kE6hE9RpGiYYhx5xNr5+16xzBUU8O535oGfSNmNaMzbTQfDNQE8KVQxSNv m1SnF/MA9gCiAFotKYiHM75/E8RxCeuuD5xaIGuP23ScyRzV7OpGjr+HvwekHG/BGV nwHpZPqS9phLWATmjvBVBV1ECFO8+Cvervfa3TOIsmfrG98nNzy68QXybwmTrMdHBG Zz1DxrdARWfSfOsefMeGev8TXOkogn0oGaOx9eZrMFLuePcuc+V1BnEVpyXwnv/3wR QtJ43HrMLNTpA== Received: from smtp (Not Verified[10.32.16.33]) by mmarshal3.atlnz.lc with Trustwave SEG (v7,5,8,10121) id ; Mon, 29 Oct 2018 20:25:53 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by smtp (Postfix) with ESMTP id BBC8713EFD8; Mon, 29 Oct 2018 20:25:53 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id E11BC1E21FF; Mon, 29 Oct 2018 20:25:48 +1300 (NZDT) From: Chris Packham To: linux@armlinux.org.uk Cc: u.kleine-koenig@pengutronix.de, jlu@pengutronix.de, bp@alien8.de, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Packham , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH v5 5/8] ARM: l2x0: add marvell,ecc-enable property for aurora Date: Mon, 29 Oct 2018 20:25:32 +1300 Message-Id: <20181029072535.31667-6-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181029072535.31667-1-chris.packham@alliedtelesis.co.nz> References: <20181029072535.31667-1-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable x-atlnz-ls: pat Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The aurora cache on the Marvell Armada-XP SoC supports ECC protection for the L2 data arrays. Add a "marvell,ecc-enable" device tree property which can be used to enable this. Signed-off-by: Chris Packham [jlu@pengutronix.de: use aurora specific define AURORA_ACR_ECC_EN] Signed-off-by: Jan Luebbe --- =20Documentation/devicetree/bindings/arm/l2c2x0.txt | 2 ++ =20arch/arm/mm/cache-l2x0.c | 7 +++++++ =202 files changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt b/Documenta= tion/devicetree/bindings/arm/l2c2x0.txt index fbe6cb21f4cf..15a84f0ba9f1 100644 --- a/Documentation/devicetree/bindings/arm/l2c2x0.txt +++ b/Documentation/devicetree/bindings/arm/l2c2x0.txt @@ -76,6 +76,8 @@ Optional properties: =20 specified to indicate that such transforms are precluded. =20- arm,parity-enable : enable parity checking on the L2 cache (L220 or = PL310). =20- arm,parity-disable : disable parity checking on the L2 cache (L220 o= r PL310). +- marvell,ecc-enable : enable ECC protection on the L2 cache +- marvell,ecc-disable : disable ECC protection on the L2 cache =20- arm,outer-sync-disable : disable the outer sync operation on the L2 = cache. =20 Some core tiles, especially ARM PB11MPCore have a faulty L220 cache = that =20 will randomly hang unless outer sync operations are disabled. diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index b70bee74750d..644f786e4fa9 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -1505,6 +1505,13 @@ static void __init aurora_of_parse(const struct de= vice_node *np, =20 mask |=3D AURORA_ACR_FORCE_WRITE_POLICY_MASK; =20 } =20 + if (of_property_read_bool(np, "marvell,ecc-enable")) { + mask |=3D AURORA_ACR_ECC_EN; + val |=3D AURORA_ACR_ECC_EN; + } else if (of_property_read_bool(np, "marvell,ecc-disable")) { + mask |=3D AURORA_ACR_ECC_EN; + } + =20 if (of_property_read_bool(np, "arm,parity-enable")) { =20 mask |=3D AURORA_ACR_PARITY_EN; =20 val |=3D AURORA_ACR_PARITY_EN; --=20 2.19.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v5,5/8] ARM: l2x0: add marvell,ecc-enable property for aurora From: Chris Packham Message-Id: <20181029072535.31667-6-chris.packham@alliedtelesis.co.nz> Date: Mon, 29 Oct 2018 20:25:32 +1300 To: linux@armlinux.org.uk Cc: u.kleine-koenig@pengutronix.de, jlu@pengutronix.de, bp@alien8.de, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Packham , Rob Herring , Mark Rutland , devicetree@vger.kernel.org List-ID: VGhlIGF1cm9yYSBjYWNoZSBvbiB0aGUgTWFydmVsbCBBcm1hZGEtWFAgU29DIHN1cHBvcnRzIEVD QyBwcm90ZWN0aW9uCmZvciB0aGUgTDIgZGF0YSBhcnJheXMuIEFkZCBhICJtYXJ2ZWxsLGVjYy1l bmFibGUiIGRldmljZSB0cmVlIHByb3BlcnR5CndoaWNoIGNhbiBiZSB1c2VkIHRvIGVuYWJsZSB0 aGlzLgoKU2lnbmVkLW9mZi1ieTogQ2hyaXMgUGFja2hhbSA8Y2hyaXMucGFja2hhbUBhbGxpZWR0 ZWxlc2lzLmNvLm56Pgpbamx1QHBlbmd1dHJvbml4LmRlOiB1c2UgYXVyb3JhIHNwZWNpZmljIGRl ZmluZSBBVVJPUkFfQUNSX0VDQ19FTl0KU2lnbmVkLW9mZi1ieTogSmFuIEx1ZWJiZSA8amx1QHBl bmd1dHJvbml4LmRlPgotLS0KIERvY3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9hcm0v bDJjMngwLnR4dCB8IDIgKysKIGFyY2gvYXJtL21tL2NhY2hlLWwyeDAuYyAgICAgICAgICAgICAg ICAgICAgICAgICB8IDcgKysrKysrKwogMiBmaWxlcyBjaGFuZ2VkLCA5IGluc2VydGlvbnMoKykK CmRpZmYgLS1naXQgYS9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvYXJtL2wyYzJ4 MC50eHQgYi9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvYXJtL2wyYzJ4MC50eHQK aW5kZXggZmJlNmNiMjFmNGNmLi4xNWE4NGYwYmE5ZjEgMTAwNjQ0Ci0tLSBhL0RvY3VtZW50YXRp b24vZGV2aWNldHJlZS9iaW5kaW5ncy9hcm0vbDJjMngwLnR4dAorKysgYi9Eb2N1bWVudGF0aW9u L2RldmljZXRyZWUvYmluZGluZ3MvYXJtL2wyYzJ4MC50eHQKQEAgLTc2LDYgKzc2LDggQEAgT3B0 aW9uYWwgcHJvcGVydGllczoKICAgc3BlY2lmaWVkIHRvIGluZGljYXRlIHRoYXQgc3VjaCB0cmFu c2Zvcm1zIGFyZSBwcmVjbHVkZWQuCiAtIGFybSxwYXJpdHktZW5hYmxlIDogZW5hYmxlIHBhcml0 eSBjaGVja2luZyBvbiB0aGUgTDIgY2FjaGUgKEwyMjAgb3IgUEwzMTApLgogLSBhcm0scGFyaXR5 LWRpc2FibGUgOiBkaXNhYmxlIHBhcml0eSBjaGVja2luZyBvbiB0aGUgTDIgY2FjaGUgKEwyMjAg b3IgUEwzMTApLgorLSBtYXJ2ZWxsLGVjYy1lbmFibGUgOiBlbmFibGUgRUNDIHByb3RlY3Rpb24g b24gdGhlIEwyIGNhY2hlCistIG1hcnZlbGwsZWNjLWRpc2FibGUgOiBkaXNhYmxlIEVDQyBwcm90 ZWN0aW9uIG9uIHRoZSBMMiBjYWNoZQogLSBhcm0sb3V0ZXItc3luYy1kaXNhYmxlIDogZGlzYWJs ZSB0aGUgb3V0ZXIgc3luYyBvcGVyYXRpb24gb24gdGhlIEwyIGNhY2hlLgogICBTb21lIGNvcmUg dGlsZXMsIGVzcGVjaWFsbHkgQVJNIFBCMTFNUENvcmUgaGF2ZSBhIGZhdWx0eSBMMjIwIGNhY2hl IHRoYXQKICAgd2lsbCByYW5kb21seSBoYW5nIHVubGVzcyBvdXRlciBzeW5jIG9wZXJhdGlvbnMg YXJlIGRpc2FibGVkLgpkaWZmIC0tZ2l0IGEvYXJjaC9hcm0vbW0vY2FjaGUtbDJ4MC5jIGIvYXJj aC9hcm0vbW0vY2FjaGUtbDJ4MC5jCmluZGV4IGI3MGJlZTc0NzUwZC4uNjQ0Zjc4NmU0ZmE5IDEw MDY0NAotLS0gYS9hcmNoL2FybS9tbS9jYWNoZS1sMngwLmMKKysrIGIvYXJjaC9hcm0vbW0vY2Fj aGUtbDJ4MC5jCkBAIC0xNTA1LDYgKzE1MDUsMTMgQEAgc3RhdGljIHZvaWQgX19pbml0IGF1cm9y YV9vZl9wYXJzZShjb25zdCBzdHJ1Y3QgZGV2aWNlX25vZGUgKm5wLAogCQltYXNrIHw9IEFVUk9S QV9BQ1JfRk9SQ0VfV1JJVEVfUE9MSUNZX01BU0s7CiAJfQogCisJaWYgKG9mX3Byb3BlcnR5X3Jl YWRfYm9vbChucCwgIm1hcnZlbGwsZWNjLWVuYWJsZSIpKSB7CisJCW1hc2sgfD0gQVVST1JBX0FD Ul9FQ0NfRU47CisJCXZhbCB8PSBBVVJPUkFfQUNSX0VDQ19FTjsKKwl9IGVsc2UgaWYgKG9mX3By b3BlcnR5X3JlYWRfYm9vbChucCwgIm1hcnZlbGwsZWNjLWRpc2FibGUiKSkgeworCQltYXNrIHw9 IEFVUk9SQV9BQ1JfRUNDX0VOOworCX0KKwogCWlmIChvZl9wcm9wZXJ0eV9yZWFkX2Jvb2wobnAs ICJhcm0scGFyaXR5LWVuYWJsZSIpKSB7CiAJCW1hc2sgfD0gQVVST1JBX0FDUl9QQVJJVFlfRU47 CiAJCXZhbCB8PSBBVVJPUkFfQUNSX1BBUklUWV9FTjsK From mboxrd@z Thu Jan 1 00:00:00 1970 From: chris.packham@alliedtelesis.co.nz (Chris Packham) Date: Mon, 29 Oct 2018 20:25:32 +1300 Subject: [PATCH v5 5/8] ARM: l2x0: add marvell,ecc-enable property for aurora In-Reply-To: <20181029072535.31667-1-chris.packham@alliedtelesis.co.nz> References: <20181029072535.31667-1-chris.packham@alliedtelesis.co.nz> Message-ID: <20181029072535.31667-6-chris.packham@alliedtelesis.co.nz> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org The aurora cache on the Marvell Armada-XP SoC supports ECC protection for the L2 data arrays. Add a "marvell,ecc-enable" device tree property which can be used to enable this. Signed-off-by: Chris Packham [jlu at pengutronix.de: use aurora specific define AURORA_ACR_ECC_EN] Signed-off-by: Jan Luebbe --- Documentation/devicetree/bindings/arm/l2c2x0.txt | 2 ++ arch/arm/mm/cache-l2x0.c | 7 +++++++ 2 files changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt b/Documentation/devicetree/bindings/arm/l2c2x0.txt index fbe6cb21f4cf..15a84f0ba9f1 100644 --- a/Documentation/devicetree/bindings/arm/l2c2x0.txt +++ b/Documentation/devicetree/bindings/arm/l2c2x0.txt @@ -76,6 +76,8 @@ Optional properties: specified to indicate that such transforms are precluded. - arm,parity-enable : enable parity checking on the L2 cache (L220 or PL310). - arm,parity-disable : disable parity checking on the L2 cache (L220 or PL310). +- marvell,ecc-enable : enable ECC protection on the L2 cache +- marvell,ecc-disable : disable ECC protection on the L2 cache - arm,outer-sync-disable : disable the outer sync operation on the L2 cache. Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that will randomly hang unless outer sync operations are disabled. diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index b70bee74750d..644f786e4fa9 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -1505,6 +1505,13 @@ static void __init aurora_of_parse(const struct device_node *np, mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK; } + if (of_property_read_bool(np, "marvell,ecc-enable")) { + mask |= AURORA_ACR_ECC_EN; + val |= AURORA_ACR_ECC_EN; + } else if (of_property_read_bool(np, "marvell,ecc-disable")) { + mask |= AURORA_ACR_ECC_EN; + } + if (of_property_read_bool(np, "arm,parity-enable")) { mask |= AURORA_ACR_PARITY_EN; val |= AURORA_ACR_PARITY_EN; -- 2.19.1