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From: Chris Packham <chris.packham@alliedtelesis.co.nz>
To: linux@armlinux.org.uk
Cc: u.kleine-koenig@pengutronix.de, jlu@pengutronix.de, bp@alien8.de,
	linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	Chris Packham <chris.packham@alliedtelesis.co.nz>,
	Mauro Carvalho Chehab <mchehab@kernel.org>
Subject: [PATCH v5 8/8] EDAC: armada_xp: Add support for more SoCs
Date: Mon, 29 Oct 2018 20:25:35 +1300	[thread overview]
Message-ID: <20181029072535.31667-9-chris.packham@alliedtelesis.co.nz> (raw)
In-Reply-To: <20181029072535.31667-1-chris.packham@alliedtelesis.co.nz>

The Armada 38x and other integrated SoCs use a reduced pin count so the
width of the SDRAM interface is smaller than the Armada XP SoCs. This
means that the definition of "full" and "half" width is reduced from
64/32 to 32/16.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
 drivers/edac/armada_xp_edac.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/edac/armada_xp_edac.c b/drivers/edac/armada_xp_edac.c
index 70cff01afc8d..03a18b54467a 100644
--- a/drivers/edac/armada_xp_edac.c
+++ b/drivers/edac/armada_xp_edac.c
@@ -341,6 +341,11 @@ static int axp_mc_probe(struct platform_device *pdev)
 
 	axp_mc_read_config(mci);
 
+	/* These SoCs have a reduced width bus */
+	if (of_machine_is_compatible("marvell,armada380") ||
+	    of_machine_is_compatible("marvell,armadaxp-98dx3236"))
+		drvdata->width /= 2;
+
 	/* configure SBE threshold */
 	/* it seems that SBEs are not captured otherwise */
 	writel(1 << SDRAM_ERR_CTRL_THR_OFFSET, drvdata->base + SDRAM_ERR_CTRL_REG);
-- 
2.19.1

WARNING: multiple messages have this Message-ID (diff)
From: Chris Packham <chris.packham@alliedtelesis.co.nz>
To: linux@armlinux.org.uk
Cc: u.kleine-koenig@pengutronix.de, jlu@pengutronix.de, bp@alien8.de,
	linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	Chris Packham <chris.packham@alliedtelesis.co.nz>,
	Mauro Carvalho Chehab <mchehab@kernel.org>
Subject: [v5,8/8] EDAC: armada_xp: Add support for more SoCs
Date: Mon, 29 Oct 2018 20:25:35 +1300	[thread overview]
Message-ID: <20181029072535.31667-9-chris.packham@alliedtelesis.co.nz> (raw)

The Armada 38x and other integrated SoCs use a reduced pin count so the
width of the SDRAM interface is smaller than the Armada XP SoCs. This
means that the definition of "full" and "half" width is reduced from
64/32 to 32/16.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
 drivers/edac/armada_xp_edac.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/edac/armada_xp_edac.c b/drivers/edac/armada_xp_edac.c
index 70cff01afc8d..03a18b54467a 100644
--- a/drivers/edac/armada_xp_edac.c
+++ b/drivers/edac/armada_xp_edac.c
@@ -341,6 +341,11 @@ static int axp_mc_probe(struct platform_device *pdev)
 
 	axp_mc_read_config(mci);
 
+	/* These SoCs have a reduced width bus */
+	if (of_machine_is_compatible("marvell,armada380") ||
+	    of_machine_is_compatible("marvell,armadaxp-98dx3236"))
+		drvdata->width /= 2;
+
 	/* configure SBE threshold */
 	/* it seems that SBEs are not captured otherwise */
 	writel(1 << SDRAM_ERR_CTRL_THR_OFFSET, drvdata->base + SDRAM_ERR_CTRL_REG);

WARNING: multiple messages have this Message-ID (diff)
From: chris.packham@alliedtelesis.co.nz (Chris Packham)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 8/8] EDAC: armada_xp: Add support for more SoCs
Date: Mon, 29 Oct 2018 20:25:35 +1300	[thread overview]
Message-ID: <20181029072535.31667-9-chris.packham@alliedtelesis.co.nz> (raw)
In-Reply-To: <20181029072535.31667-1-chris.packham@alliedtelesis.co.nz>

The Armada 38x and other integrated SoCs use a reduced pin count so the
width of the SDRAM interface is smaller than the Armada XP SoCs. This
means that the definition of "full" and "half" width is reduced from
64/32 to 32/16.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
 drivers/edac/armada_xp_edac.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/edac/armada_xp_edac.c b/drivers/edac/armada_xp_edac.c
index 70cff01afc8d..03a18b54467a 100644
--- a/drivers/edac/armada_xp_edac.c
+++ b/drivers/edac/armada_xp_edac.c
@@ -341,6 +341,11 @@ static int axp_mc_probe(struct platform_device *pdev)
 
 	axp_mc_read_config(mci);
 
+	/* These SoCs have a reduced width bus */
+	if (of_machine_is_compatible("marvell,armada380") ||
+	    of_machine_is_compatible("marvell,armadaxp-98dx3236"))
+		drvdata->width /= 2;
+
 	/* configure SBE threshold */
 	/* it seems that SBEs are not captured otherwise */
 	writel(1 << SDRAM_ERR_CTRL_THR_OFFSET, drvdata->base + SDRAM_ERR_CTRL_REG);
-- 
2.19.1

  parent reply	other threads:[~2018-10-29  7:26 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-29  7:25 [PATCH v5 0/8] EDAC drivers for Armada XP L2 and DDR Chris Packham
2018-10-29  7:25 ` Chris Packham
2018-10-29  7:25 ` [PATCH v5 1/8] ARM: l2c: move cache-aurora-l2.h to asm/hardware Chris Packham
2018-10-29  7:25   ` Chris Packham
2018-10-29  7:25   ` [v5,1/8] " Chris Packham
2018-10-29  7:25 ` [PATCH v5 2/8] ARM: aurora-l2: add prefix to MAX_RANGE_SIZE Chris Packham
2018-10-29  7:25   ` Chris Packham
2018-10-29  7:25   ` [v5,2/8] " Chris Packham
2018-10-29  7:25 ` [PATCH v5 3/8] ARM: aurora-l2: add defines for parity and ECC registers Chris Packham
2018-10-29  7:25   ` Chris Packham
2018-10-29  7:25   ` [v5,3/8] " Chris Packham
2018-10-29  7:25 ` [PATCH v5 4/8] ARM: l2x0: support parity-enable/disable on aurora Chris Packham
2018-10-29  7:25   ` Chris Packham
2018-10-29  7:25   ` [v5,4/8] " Chris Packham
2018-10-29  7:25 ` [PATCH v5 5/8] ARM: l2x0: add marvell,ecc-enable property for aurora Chris Packham
2018-10-29  7:25   ` Chris Packham
2018-10-29  7:25   ` [v5,5/8] " Chris Packham
2018-10-30 19:31   ` [PATCH v5 5/8] " Rob Herring
2018-10-30 19:31     ` Rob Herring
2018-10-30 19:31     ` Rob Herring
2018-10-30 19:31     ` [v5,5/8] " Rob Herring
2018-11-08 15:17   ` [PATCH v5 5/8] " Borislav Petkov
2018-11-08 15:17     ` Borislav Petkov
2018-11-08 15:17     ` [v5,5/8] " Borislav Petkov
2018-10-29  7:25 ` [PATCH v5 6/8] EDAC: Add missing debugfs_create_x32 wrapper Chris Packham
2018-10-29  7:25   ` Chris Packham
2018-10-29  7:25   ` [v5,6/8] " Chris Packham
2018-10-29  7:25 ` [PATCH v5 7/8] EDAC: Add driver for the Marvell Armada XP SDRAM and L2 cache ECC Chris Packham
2018-10-29  7:25   ` Chris Packham
2018-10-29  7:25   ` [v5,7/8] " Chris Packham
2018-10-29  7:25 ` Chris Packham [this message]
2018-10-29  7:25   ` [PATCH v5 8/8] EDAC: armada_xp: Add support for more SoCs Chris Packham
2018-10-29  7:25   ` [v5,8/8] " Chris Packham

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