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McKenney" To: Arnd Bergmann Cc: andrea.parri@amarulasolutions.com, Peter Zijlstra , Josh Triplett , Linux Kernel Mailing List Subject: Re: [RFR] Store tearing Reply-To: paulmck@linux.ibm.com References: <20181028230627.GA3420@andrea> <20181028231003.GA4021@andrea> <20181029012042.GR4170@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-TM-AS-GCONF: 00 x-cbid: 18102911-0040-0000-0000-00000488398C X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00009947; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000268; SDB=6.01109627; UDB=6.00574892; IPR=6.00889720; MB=3.00023950; MTD=3.00000008; XFM=3.00000015; UTC=2018-10-29 11:27:26 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18102911-0041-0000-0000-000008905745 Message-Id: <20181029112725.GV4170@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2018-10-29_09:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=825 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1807170000 definitions=main-1810290109 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Oct 29, 2018 at 10:23:07AM +0100, Arnd Bergmann wrote: > On Mon, Oct 29, 2018 at 2:21 AM Paul E. McKenney wrote: > > > > On Mon, Oct 29, 2018 at 12:10:03AM +0100, Andrea Parri wrote: > > > Hopefully, with Paul's proper email address this time, > > > > > > Andrea > > > > > > On Mon, Oct 29, 2018 at 12:06:27AM +0100, Andrea Parri wrote: > > > > Hi, > > > > > > > > memory-barriers.txt says: > > > > > > > > [on "store tearing"] > > > > > > > > "In fact, a recent bug (since fixed) caused GCC to incorrectly use > > > > this optimization in a volatile store.". > > > > > > > > I was wondering if you could help me retrieve some reference/discussions > > > > about this? > > > > This was quite some time ago, but it involved a 32-bit volatile store > > of a constant such as 0x10001. The machine in question had a narrow > > store-immediate instruction, so the compiler emitted a pair of 16-bit > > store-immediate instructions. This bug was fixed, though only after > > significant screaming and shouting. > > A related issue I remember was on ARMv5 (an architecture without > unaligned access) where a function like )not sure if this specific > one triggers it, but something like it did) > > struct my_registers { > u32 a; > u32 b; > u32 c; > } __attribute__((packed)); > #define __raw_writel(p, v) do { (volatile u32 __iomem *)(p) = (v); } while (0) > void my_write_a(struct my_registers __iomem *r, u32 val) > { > __raw_writel(&r->a, val); > } > > The above is undefined behavior because we cast from an unaligned > data type to a 32-bit aligned type, and gcc resolved this by turning the > intended 32-bit store into a set of 8 bit stores. We worked around this > by changing __raw_writel() into a inline assembly that always uses a > 32-bit store. I had either missed or forgotten this one, nice example of store tearing! Thanx, Paul