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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id d8sm10438618otd.69.2018.10.30.12.31.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 30 Oct 2018 12:31:38 -0700 (PDT) Date: Tue, 30 Oct 2018 14:31:37 -0500 From: Rob Herring To: Chris Packham Cc: linux@armlinux.org.uk, u.kleine-koenig@pengutronix.de, jlu@pengutronix.de, bp@alien8.de, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Packham , Mark Rutland , devicetree@vger.kernel.org Subject: Re: [PATCH v5 5/8] ARM: l2x0: add marvell,ecc-enable property for aurora Message-ID: <20181030193137.GA28258@bogus> References: <20181029072535.31667-1-chris.packham@alliedtelesis.co.nz> <20181029072535.31667-6-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20181029072535.31667-6-chris.packham@alliedtelesis.co.nz> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 29 Oct 2018 20:25:32 +1300, Chris Packham wrote: > The aurora cache on the Marvell Armada-XP SoC supports ECC protection > for the L2 data arrays. Add a "marvell,ecc-enable" device tree property > which can be used to enable this. > > Signed-off-by: Chris Packham > [jlu@pengutronix.de: use aurora specific define AURORA_ACR_ECC_EN] > Signed-off-by: Jan Luebbe > --- > Documentation/devicetree/bindings/arm/l2c2x0.txt | 2 ++ > arch/arm/mm/cache-l2x0.c | 7 +++++++ > 2 files changed, 9 insertions(+) > Reviewed-by: Rob Herring From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v5,5/8] ARM: l2x0: add marvell,ecc-enable property for aurora From: Rob Herring Message-Id: <20181030193137.GA28258@bogus> Date: Tue, 30 Oct 2018 14:31:37 -0500 To: Chris Packham Cc: linux@armlinux.org.uk, u.kleine-koenig@pengutronix.de, jlu@pengutronix.de, bp@alien8.de, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Rutland , devicetree@vger.kernel.org List-ID: T24gTW9uLCAyOSBPY3QgMjAxOCAyMDoyNTozMiArMTMwMCwgQ2hyaXMgUGFja2hhbSB3cm90ZToK PiBUaGUgYXVyb3JhIGNhY2hlIG9uIHRoZSBNYXJ2ZWxsIEFybWFkYS1YUCBTb0Mgc3VwcG9ydHMg RUNDIHByb3RlY3Rpb24KPiBmb3IgdGhlIEwyIGRhdGEgYXJyYXlzLiBBZGQgYSAibWFydmVsbCxl Y2MtZW5hYmxlIiBkZXZpY2UgdHJlZSBwcm9wZXJ0eQo+IHdoaWNoIGNhbiBiZSB1c2VkIHRvIGVu YWJsZSB0aGlzLgo+IAo+IFNpZ25lZC1vZmYtYnk6IENocmlzIFBhY2toYW0gPGNocmlzLnBhY2to YW1AYWxsaWVkdGVsZXNpcy5jby5uej4KPiBbamx1QHBlbmd1dHJvbml4LmRlOiB1c2UgYXVyb3Jh IHNwZWNpZmljIGRlZmluZSBBVVJPUkFfQUNSX0VDQ19FTl0KPiBTaWduZWQtb2ZmLWJ5OiBKYW4g THVlYmJlIDxqbHVAcGVuZ3V0cm9uaXguZGU+Cj4gLS0tCj4gIERvY3VtZW50YXRpb24vZGV2aWNl dHJlZS9iaW5kaW5ncy9hcm0vbDJjMngwLnR4dCB8IDIgKysKPiAgYXJjaC9hcm0vbW0vY2FjaGUt bDJ4MC5jICAgICAgICAgICAgICAgICAgICAgICAgIHwgNyArKysrKysrCj4gIDIgZmlsZXMgY2hh bmdlZCwgOSBpbnNlcnRpb25zKCspCj4gCgpSZXZpZXdlZC1ieTogUm9iIEhlcnJpbmcgPHJvYmhA a2VybmVsLm9yZz4K From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rob Herring Subject: Re: [PATCH v5 5/8] ARM: l2x0: add marvell,ecc-enable property for aurora Date: Tue, 30 Oct 2018 14:31:37 -0500 Message-ID: <20181030193137.GA28258@bogus> References: <20181029072535.31667-1-chris.packham@alliedtelesis.co.nz> <20181029072535.31667-6-chris.packham@alliedtelesis.co.nz> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <20181029072535.31667-6-chris.packham@alliedtelesis.co.nz> Sender: linux-kernel-owner@vger.kernel.org Cc: linux@armlinux.org.uk, u.kleine-koenig@pengutronix.de, jlu@pengutronix.de, bp@alien8.de, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Packham , Mark Rutland , devicetree@vger.kernel.org List-Id: devicetree@vger.kernel.org On Mon, 29 Oct 2018 20:25:32 +1300, Chris Packham wrote: > The aurora cache on the Marvell Armada-XP SoC supports ECC protection > for the L2 data arrays. Add a "marvell,ecc-enable" device tree property > which can be used to enable this. > > Signed-off-by: Chris Packham > [jlu@pengutronix.de: use aurora specific define AURORA_ACR_ECC_EN] > Signed-off-by: Jan Luebbe > --- > Documentation/devicetree/bindings/arm/l2c2x0.txt | 2 ++ > arch/arm/mm/cache-l2x0.c | 7 +++++++ > 2 files changed, 9 insertions(+) > Reviewed-by: Rob Herring From mboxrd@z Thu Jan 1 00:00:00 1970 From: robh@kernel.org (Rob Herring) Date: Tue, 30 Oct 2018 14:31:37 -0500 Subject: [PATCH v5 5/8] ARM: l2x0: add marvell,ecc-enable property for aurora In-Reply-To: <20181029072535.31667-6-chris.packham@alliedtelesis.co.nz> References: <20181029072535.31667-1-chris.packham@alliedtelesis.co.nz> <20181029072535.31667-6-chris.packham@alliedtelesis.co.nz> Message-ID: <20181030193137.GA28258@bogus> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Mon, 29 Oct 2018 20:25:32 +1300, Chris Packham wrote: > The aurora cache on the Marvell Armada-XP SoC supports ECC protection > for the L2 data arrays. Add a "marvell,ecc-enable" device tree property > which can be used to enable this. > > Signed-off-by: Chris Packham > [jlu at pengutronix.de: use aurora specific define AURORA_ACR_ECC_EN] > Signed-off-by: Jan Luebbe > --- > Documentation/devicetree/bindings/arm/l2c2x0.txt | 2 ++ > arch/arm/mm/cache-l2x0.c | 7 +++++++ > 2 files changed, 9 insertions(+) > Reviewed-by: Rob Herring