* [PATCH 1/4] drm/i915: remove palette_offsets from device info in favor of _PICK()
@ 2018-10-31 11:04 Jani Nikula
2018-10-31 11:04 ` [PATCH 2/4] drm/i915: define _MMIO_PLANE() in terms of _PLANE() not _MMIO_PIPE() Jani Nikula
` (6 more replies)
0 siblings, 7 replies; 11+ messages in thread
From: Jani Nikula @ 2018-10-31 11:04 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
The device info offset arrays for unevenly spaced register offsets is
great for widely used registers. However, the palette registers are only
used in one function, i9xx_load_luts_internal(), and only for GMCH
platforms, wasting device info. Replace palette_offsets with _PICK() in
palette register definition.
While the use of _PICK() does not check for pipe C existence, neither
does the current offset array usage, and leads to bogus address when
pipe C is passed to PALETTE() on non-CHV. Using _PICK() at least leads
to a sensible register offset, just non-existing on non-CHV. Either way,
this shouldn't happen anyway.
Remove unused old palette macros while at it.
Bloat-o-meter results below for completeness.
add/remove: 0/0 grow/shrink: 3/6 up/down: 94/-278 (-184)
Function old new delta
i9xx_load_luts_internal 394 483 +89
i915_driver_load 5103 5107 +4
g4x_pre_enable_dp 378 379 +1
intel_engines_init_mmio 1117 1116 -1
intel_engine_lookup_user 47 46 -1
hdmi_port_clock_valid 310 309 -1
gen11_irq_handler 707 706 -1
intel_device_info_dump_runtime 329 311 -18
intel_device_info_runtime_init 5166 4910 -256
Total: Before=918650, After=918466, chg -0.02%
add/remove: 0/0 grow/shrink: 0/48 up/down: 0/-576 (-576)
Data old new delta
intel_valleyview_info 200 188 -12
intel_skylake_gt4_info 200 188 -12
intel_skylake_gt3_info 200 188 -12
intel_skylake_gt2_info 200 188 -12
intel_skylake_gt1_info 200 188 -12
intel_sandybridge_m_gt2_info 200 188 -12
intel_sandybridge_m_gt1_info 200 188 -12
intel_sandybridge_d_gt2_info 200 188 -12
intel_sandybridge_d_gt1_info 200 188 -12
intel_pineview_info 200 188 -12
intel_kabylake_gt3_info 200 188 -12
intel_kabylake_gt2_info 200 188 -12
intel_kabylake_gt1_info 200 188 -12
intel_ivybridge_q_info 200 188 -12
intel_ivybridge_m_gt2_info 200 188 -12
intel_ivybridge_m_gt1_info 200 188 -12
intel_ivybridge_d_gt2_info 200 188 -12
intel_ivybridge_d_gt1_info 200 188 -12
intel_ironlake_m_info 200 188 -12
intel_ironlake_d_info 200 188 -12
intel_icelake_11_info 200 188 -12
intel_i965gm_info 200 188 -12
intel_i965g_info 200 188 -12
intel_i945gm_info 200 188 -12
intel_i945g_info 200 188 -12
intel_i915gm_info 200 188 -12
intel_i915g_info 200 188 -12
intel_i865g_info 200 188 -12
intel_i85x_info 200 188 -12
intel_i845g_info 200 188 -12
intel_i830_info 200 188 -12
intel_haswell_gt3_info 200 188 -12
intel_haswell_gt2_info 200 188 -12
intel_haswell_gt1_info 200 188 -12
intel_gm45_info 200 188 -12
intel_geminilake_info 200 188 -12
intel_g45_info 200 188 -12
intel_g33_info 200 188 -12
intel_coffeelake_gt3_info 200 188 -12
intel_coffeelake_gt2_info 200 188 -12
intel_coffeelake_gt1_info 200 188 -12
intel_cherryview_info 200 188 -12
intel_cannonlake_info 200 188 -12
intel_broxton_info 200 188 -12
intel_broadwell_rsvd_info 200 188 -12
intel_broadwell_gt3_info 200 188 -12
intel_broadwell_gt2_info 200 188 -12
intel_broadwell_gt1_info 200 188 -12
Total: Before=195529, After=194953, chg -0.29%
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 7 ++-----
drivers/gpu/drm/i915/i915_reg.h | 16 +++++++---------
drivers/gpu/drm/i915/intel_device_info.h | 1 -
3 files changed, 9 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 44e745921ac1..4ccab8372dd4 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -36,16 +36,13 @@
.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
- TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
- .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
+ TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET } \
#define GEN_CHV_PIPEOFFSETS \
.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
CHV_PIPE_C_OFFSET }, \
.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
- CHV_TRANSCODER_C_OFFSET, }, \
- .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
- CHV_PALETTE_C_OFFSET }
+ CHV_TRANSCODER_C_OFFSET, } \
#define CURSOR_OFFSETS \
.cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bcee91bcfba6..d97cf98e3edf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3439,11 +3439,13 @@ enum i915_power_well_id {
/*
* Palette regs
*/
-#define PALETTE_A_OFFSET 0xa000
-#define PALETTE_B_OFFSET 0xa800
-#define CHV_PALETTE_C_OFFSET 0xc000
-#define PALETTE(pipe, i) _MMIO(dev_priv->info.palette_offsets[pipe] + \
- dev_priv->info.display_mmio_offset + (i) * 4)
+#define _PALETTE_A 0xa000
+#define _PALETTE_B 0xa800
+#define _CHV_PALETTE_C 0xc000
+#define PALETTE(pipe, i) _MMIO(dev_priv->info.display_mmio_offset + \
+ _PICK((pipe), _PALETTE_A, \
+ _PALETTE_B, _CHV_PALETTE_C) + \
+ (i) * 4)
/* MCH MMIO space */
@@ -10645,10 +10647,6 @@ enum skl_power_gate {
#define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
#define READ_DATA_VALID(n) (1 << (n))
-/* For UMS only (deprecated): */
-#define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
-#define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
-
/* MOCS (Memory Object Control State) registers */
#define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index b4c2c4eae78b..86ce1db1b33a 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -177,7 +177,6 @@ struct intel_device_info {
/* Register offsets for the various display pipes and transcoders */
int pipe_offsets[I915_MAX_TRANSCODERS];
int trans_offsets[I915_MAX_TRANSCODERS];
- int palette_offsets[I915_MAX_PIPES];
int cursor_offsets[I915_MAX_PIPES];
/* Slice/subslice/EU info */
--
2.11.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 2/4] drm/i915: define _MMIO_PLANE() in terms of _PLANE() not _MMIO_PIPE()
2018-10-31 11:04 [PATCH 1/4] drm/i915: remove palette_offsets from device info in favor of _PICK() Jani Nikula
@ 2018-10-31 11:04 ` Jani Nikula
2018-10-31 13:00 ` Ville Syrjälä
2018-10-31 11:04 ` [PATCH 3/4] drm/i915: reorder and reindent the register choosing helper wrappers Jani Nikula
` (5 subsequent siblings)
6 siblings, 1 reply; 11+ messages in thread
From: Jani Nikula @ 2018-10-31 11:04 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Minor semantic nit, no functional changes.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d97cf98e3edf..0d0145967482 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -160,7 +160,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b)
#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
#define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b)
-#define _MMIO_PLANE(plane, a, b) _MMIO_PIPE(plane, a, b)
+#define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b))
#define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b)
#define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
#define _PORT(port, a, b) _PICK_EVEN(port, a, b)
--
2.11.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 3/4] drm/i915: reorder and reindent the register choosing helper wrappers
2018-10-31 11:04 [PATCH 1/4] drm/i915: remove palette_offsets from device info in favor of _PICK() Jani Nikula
2018-10-31 11:04 ` [PATCH 2/4] drm/i915: define _MMIO_PLANE() in terms of _PLANE() not _MMIO_PIPE() Jani Nikula
@ 2018-10-31 11:04 ` Jani Nikula
2018-10-31 13:02 ` Ville Syrjälä
2018-10-31 11:04 ` [PATCH 4/4] drm/i915: also group device info array helper macros with others Jani Nikula
` (4 subsequent siblings)
6 siblings, 1 reply; 11+ messages in thread
From: Jani Nikula @ 2018-10-31 11:04 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Try to make it slightly less of an eye sore. No functional changes.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 31 +++++++++++++++++--------------
1 file changed, 17 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0d0145967482..22db12b070af 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -157,20 +157,23 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
/*
* Named helper wrappers around _PICK_EVEN() and _PICK().
*/
-#define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b)
-#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
-#define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b)
-#define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b))
-#define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b)
-#define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
-#define _PORT(port, a, b) _PICK_EVEN(port, a, b)
-#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
-#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
-#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
-#define _PLL(pll, a, b) _PICK_EVEN(pll, a, b)
-#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
-#define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
-#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
+#define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b)
+#define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b)
+#define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b)
+#define _PORT(port, a, b) _PICK_EVEN(port, a, b)
+#define _PLL(pll, a, b) _PICK_EVEN(pll, a, b)
+
+#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
+#define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b))
+#define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
+#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
+#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
+
+#define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
+
+#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
+#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
+#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
#define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
#define _MASKED_FIELD(mask, value) ({ \
--
2.11.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 4/4] drm/i915: also group device info array helper macros with others
2018-10-31 11:04 [PATCH 1/4] drm/i915: remove palette_offsets from device info in favor of _PICK() Jani Nikula
2018-10-31 11:04 ` [PATCH 2/4] drm/i915: define _MMIO_PLANE() in terms of _PLANE() not _MMIO_PIPE() Jani Nikula
2018-10-31 11:04 ` [PATCH 3/4] drm/i915: reorder and reindent the register choosing helper wrappers Jani Nikula
@ 2018-10-31 11:04 ` Jani Nikula
2018-10-31 13:05 ` Ville Syrjälä
2018-10-31 12:57 ` ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: remove palette_offsets from device info in favor of _PICK() Patchwork
` (3 subsequent siblings)
6 siblings, 1 reply; 11+ messages in thread
From: Jani Nikula @ 2018-10-31 11:04 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Keep the register choosing macros together. No functional changes.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 26 ++++++++++++++------------
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 22db12b070af..6327a5f02da5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -175,6 +175,20 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
+/*
+ * Device info offset array based helpers for groups of registers with unevenly
+ * spaced base offsets.
+ */
+#define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \
+ dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
+ dev_priv->info.display_mmio_offset)
+#define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \
+ dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
+ dev_priv->info.display_mmio_offset)
+#define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \
+ dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
+ dev_priv->info.display_mmio_offset)
+
#define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
#define _MASKED_FIELD(mask, value) ({ \
if (__builtin_constant_p(mask)) \
@@ -4052,10 +4066,6 @@ enum {
#define TRANSCODER_DSI0_OFFSET 0x6b000
#define TRANSCODER_DSI1_OFFSET 0x6b800
-#define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \
- dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
- dev_priv->info.display_mmio_offset)
-
#define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A)
#define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A)
#define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A)
@@ -5624,10 +5634,6 @@ enum {
#define PIPE_DSI0_OFFSET 0x7b000
#define PIPE_DSI1_OFFSET 0x7b800
-#define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \
- dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
- dev_priv->info.display_mmio_offset)
-
#define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF)
#define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL)
#define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
@@ -6075,10 +6081,6 @@ enum {
#define _CURBBASE_IVB 0x71084
#define _CURBPOS_IVB 0x71088
-#define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \
- dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
- dev_priv->info.display_mmio_offset)
-
#define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
#define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
#define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
--
2.11.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: remove palette_offsets from device info in favor of _PICK()
2018-10-31 11:04 [PATCH 1/4] drm/i915: remove palette_offsets from device info in favor of _PICK() Jani Nikula
` (2 preceding siblings ...)
2018-10-31 11:04 ` [PATCH 4/4] drm/i915: also group device info array helper macros with others Jani Nikula
@ 2018-10-31 12:57 ` Patchwork
2018-10-31 12:59 ` [PATCH 1/4] " Ville Syrjälä
` (2 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2018-10-31 12:57 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/4] drm/i915: remove palette_offsets from device info in favor of _PICK()
URL : https://patchwork.freedesktop.org/series/51802/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5062 -> Patchwork_10662 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/51802/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_10662 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@gem_exec_suspend@basic-s3:
fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718)
igt@kms_flip@basic-flip-vs-modeset:
fi-skl-6700hq: PASS -> DMESG-WARN (fdo#105998)
igt@kms_frontbuffer_tracking@basic:
fi-icl-u: PASS -> FAIL (fdo#103167)
igt@kms_pipe_crc_basic@hang-read-crc-pipe-b:
fi-byt-clapper: PASS -> FAIL (fdo#107362, fdo#103191)
==== Possible fixes ====
igt@kms_chamelium@common-hpd-after-suspend:
fi-skl-6700k2: INCOMPLETE (fdo#104108, fdo#105524, k.org#199541) -> PASS
igt@kms_flip@basic-flip-vs-dpms:
fi-skl-6700hq: DMESG-WARN (fdo#105998) -> PASS
igt@kms_pipe_crc_basic@read-crc-pipe-b:
fi-byt-clapper: FAIL (fdo#107362) -> PASS
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fdo#105524 https://bugs.freedesktop.org/show_bug.cgi?id=105524
fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
k.org#199541 https://bugzilla.kernel.org/show_bug.cgi?id=199541
== Participating hosts (49 -> 42) ==
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-gdg-551 fi-pnv-d510
== Build changes ==
* Linux: CI_DRM_5062 -> Patchwork_10662
CI_DRM_5062: 3aa71a0d803ee01605f9a3026ddd989a591a73c6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4703: f882a542a3eb24e78e51aa6410a3a67c0efb4e97 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10662: f586520210ac6732cba884a5be3da74227fe53e3 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f586520210ac drm/i915: also group device info array helper macros with others
feaa6abaf111 drm/i915: reorder and reindent the register choosing helper wrappers
900ed489f2c9 drm/i915: define _MMIO_PLANE() in terms of _PLANE() not _MMIO_PIPE()
ab0e5d165ab8 drm/i915: remove palette_offsets from device info in favor of _PICK()
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10662/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/4] drm/i915: remove palette_offsets from device info in favor of _PICK()
2018-10-31 11:04 [PATCH 1/4] drm/i915: remove palette_offsets from device info in favor of _PICK() Jani Nikula
` (3 preceding siblings ...)
2018-10-31 12:57 ` ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: remove palette_offsets from device info in favor of _PICK() Patchwork
@ 2018-10-31 12:59 ` Ville Syrjälä
2018-11-01 17:09 ` ✓ Fi.CI.BAT: success for series starting with [1/4] " Patchwork
2018-11-01 19:04 ` ✓ Fi.CI.IGT: " Patchwork
6 siblings, 0 replies; 11+ messages in thread
From: Ville Syrjälä @ 2018-10-31 12:59 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Wed, Oct 31, 2018 at 01:04:50PM +0200, Jani Nikula wrote:
> The device info offset arrays for unevenly spaced register offsets is
> great for widely used registers. However, the palette registers are only
> used in one function, i9xx_load_luts_internal(), and only for GMCH
> platforms, wasting device info. Replace palette_offsets with _PICK() in
> palette register definition.
>
> While the use of _PICK() does not check for pipe C existence, neither
> does the current offset array usage, and leads to bogus address when
> pipe C is passed to PALETTE() on non-CHV. Using _PICK() at least leads
> to a sensible register offset, just non-existing on non-CHV. Either way,
> this shouldn't happen anyway.
>
> Remove unused old palette macros while at it.
>
> Bloat-o-meter results below for completeness.
>
> add/remove: 0/0 grow/shrink: 3/6 up/down: 94/-278 (-184)
> Function old new delta
> i9xx_load_luts_internal 394 483 +89
> i915_driver_load 5103 5107 +4
> g4x_pre_enable_dp 378 379 +1
> intel_engines_init_mmio 1117 1116 -1
> intel_engine_lookup_user 47 46 -1
> hdmi_port_clock_valid 310 309 -1
> gen11_irq_handler 707 706 -1
> intel_device_info_dump_runtime 329 311 -18
> intel_device_info_runtime_init 5166 4910 -256
> Total: Before=918650, After=918466, chg -0.02%
>
> add/remove: 0/0 grow/shrink: 0/48 up/down: 0/-576 (-576)
> Data old new delta
> intel_valleyview_info 200 188 -12
> intel_skylake_gt4_info 200 188 -12
> intel_skylake_gt3_info 200 188 -12
> intel_skylake_gt2_info 200 188 -12
> intel_skylake_gt1_info 200 188 -12
> intel_sandybridge_m_gt2_info 200 188 -12
> intel_sandybridge_m_gt1_info 200 188 -12
> intel_sandybridge_d_gt2_info 200 188 -12
> intel_sandybridge_d_gt1_info 200 188 -12
> intel_pineview_info 200 188 -12
> intel_kabylake_gt3_info 200 188 -12
> intel_kabylake_gt2_info 200 188 -12
> intel_kabylake_gt1_info 200 188 -12
> intel_ivybridge_q_info 200 188 -12
> intel_ivybridge_m_gt2_info 200 188 -12
> intel_ivybridge_m_gt1_info 200 188 -12
> intel_ivybridge_d_gt2_info 200 188 -12
> intel_ivybridge_d_gt1_info 200 188 -12
> intel_ironlake_m_info 200 188 -12
> intel_ironlake_d_info 200 188 -12
> intel_icelake_11_info 200 188 -12
> intel_i965gm_info 200 188 -12
> intel_i965g_info 200 188 -12
> intel_i945gm_info 200 188 -12
> intel_i945g_info 200 188 -12
> intel_i915gm_info 200 188 -12
> intel_i915g_info 200 188 -12
> intel_i865g_info 200 188 -12
> intel_i85x_info 200 188 -12
> intel_i845g_info 200 188 -12
> intel_i830_info 200 188 -12
> intel_haswell_gt3_info 200 188 -12
> intel_haswell_gt2_info 200 188 -12
> intel_haswell_gt1_info 200 188 -12
> intel_gm45_info 200 188 -12
> intel_geminilake_info 200 188 -12
> intel_g45_info 200 188 -12
> intel_g33_info 200 188 -12
> intel_coffeelake_gt3_info 200 188 -12
> intel_coffeelake_gt2_info 200 188 -12
> intel_coffeelake_gt1_info 200 188 -12
> intel_cherryview_info 200 188 -12
> intel_cannonlake_info 200 188 -12
> intel_broxton_info 200 188 -12
> intel_broadwell_rsvd_info 200 188 -12
> intel_broadwell_gt3_info 200 188 -12
> intel_broadwell_gt2_info 200 188 -12
> intel_broadwell_gt1_info 200 188 -12
> Total: Before=195529, After=194953, chg -0.29%
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_pci.c | 7 ++-----
> drivers/gpu/drm/i915/i915_reg.h | 16 +++++++---------
> drivers/gpu/drm/i915/intel_device_info.h | 1 -
> 3 files changed, 9 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 44e745921ac1..4ccab8372dd4 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -36,16 +36,13 @@
> .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
> PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
> .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
> - TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
> - .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
> + TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET } \
>
> #define GEN_CHV_PIPEOFFSETS \
> .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
> CHV_PIPE_C_OFFSET }, \
> .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
> - CHV_TRANSCODER_C_OFFSET, }, \
> - .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
> - CHV_PALETTE_C_OFFSET }
> + CHV_TRANSCODER_C_OFFSET, } \
>
> #define CURSOR_OFFSETS \
> .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bcee91bcfba6..d97cf98e3edf 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3439,11 +3439,13 @@ enum i915_power_well_id {
> /*
> * Palette regs
> */
> -#define PALETTE_A_OFFSET 0xa000
> -#define PALETTE_B_OFFSET 0xa800
> -#define CHV_PALETTE_C_OFFSET 0xc000
> -#define PALETTE(pipe, i) _MMIO(dev_priv->info.palette_offsets[pipe] + \
> - dev_priv->info.display_mmio_offset + (i) * 4)
> +#define _PALETTE_A 0xa000
> +#define _PALETTE_B 0xa800
> +#define _CHV_PALETTE_C 0xc000
> +#define PALETTE(pipe, i) _MMIO(dev_priv->info.display_mmio_offset + \
> + _PICK((pipe), _PALETTE_A, \
> + _PALETTE_B, _CHV_PALETTE_C) + \
> + (i) * 4)
Confused... Ah yes, we use a totally separate register define
for the legacy lut on non-gmch platforms. That explains why there's
nothing about those platforms in the patch.
Seems okay
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> /* MCH MMIO space */
>
> @@ -10645,10 +10647,6 @@ enum skl_power_gate {
> #define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
> #define READ_DATA_VALID(n) (1 << (n))
>
> -/* For UMS only (deprecated): */
> -#define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
> -#define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
> -
> /* MOCS (Memory Object Control State) registers */
> #define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index b4c2c4eae78b..86ce1db1b33a 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -177,7 +177,6 @@ struct intel_device_info {
> /* Register offsets for the various display pipes and transcoders */
> int pipe_offsets[I915_MAX_TRANSCODERS];
> int trans_offsets[I915_MAX_TRANSCODERS];
> - int palette_offsets[I915_MAX_PIPES];
> int cursor_offsets[I915_MAX_PIPES];
>
> /* Slice/subslice/EU info */
> --
> 2.11.0
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/4] drm/i915: define _MMIO_PLANE() in terms of _PLANE() not _MMIO_PIPE()
2018-10-31 11:04 ` [PATCH 2/4] drm/i915: define _MMIO_PLANE() in terms of _PLANE() not _MMIO_PIPE() Jani Nikula
@ 2018-10-31 13:00 ` Ville Syrjälä
0 siblings, 0 replies; 11+ messages in thread
From: Ville Syrjälä @ 2018-10-31 13:00 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Wed, Oct 31, 2018 at 01:04:51PM +0200, Jani Nikula wrote:
> Minor semantic nit, no functional changes.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d97cf98e3edf..0d0145967482 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -160,7 +160,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b)
> #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
> #define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b)
> -#define _MMIO_PLANE(plane, a, b) _MMIO_PIPE(plane, a, b)
> +#define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b))
> #define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b)
> #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
> #define _PORT(port, a, b) _PICK_EVEN(port, a, b)
> --
> 2.11.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 3/4] drm/i915: reorder and reindent the register choosing helper wrappers
2018-10-31 11:04 ` [PATCH 3/4] drm/i915: reorder and reindent the register choosing helper wrappers Jani Nikula
@ 2018-10-31 13:02 ` Ville Syrjälä
0 siblings, 0 replies; 11+ messages in thread
From: Ville Syrjälä @ 2018-10-31 13:02 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Wed, Oct 31, 2018 at 01:04:52PM +0200, Jani Nikula wrote:
> Try to make it slightly less of an eye sore. No functional changes.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 31 +++++++++++++++++--------------
> 1 file changed, 17 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0d0145967482..22db12b070af 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -157,20 +157,23 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> /*
> * Named helper wrappers around _PICK_EVEN() and _PICK().
> */
> -#define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b)
> -#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
> -#define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b)
> -#define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b))
> -#define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b)
> -#define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
> -#define _PORT(port, a, b) _PICK_EVEN(port, a, b)
> -#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
> -#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
> -#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
> -#define _PLL(pll, a, b) _PICK_EVEN(pll, a, b)
> -#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
> -#define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
> -#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
> +#define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b)
> +#define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b)
> +#define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b)
> +#define _PORT(port, a, b) _PICK_EVEN(port, a, b)
> +#define _PLL(pll, a, b) _PICK_EVEN(pll, a, b)
> +
> +#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
> +#define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b))
> +#define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
> +#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
> +#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
> +
> +#define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
Hmm. Not sure why this is a vararg macro.
Anyways, patch seesm fine
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> +
> +#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
> +#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
> +#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
>
> #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
> #define _MASKED_FIELD(mask, value) ({ \
> --
> 2.11.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 4/4] drm/i915: also group device info array helper macros with others
2018-10-31 11:04 ` [PATCH 4/4] drm/i915: also group device info array helper macros with others Jani Nikula
@ 2018-10-31 13:05 ` Ville Syrjälä
0 siblings, 0 replies; 11+ messages in thread
From: Ville Syrjälä @ 2018-10-31 13:05 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Wed, Oct 31, 2018 at 01:04:53PM +0200, Jani Nikula wrote:
> Keep the register choosing macros together. No functional changes.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 26 ++++++++++++++------------
> 1 file changed, 14 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 22db12b070af..6327a5f02da5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -175,6 +175,20 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
> #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
>
> +/*
> + * Device info offset array based helpers for groups of registers with unevenly
> + * spaced base offsets.
> + */
> +#define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \
> + dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
> + dev_priv->info.display_mmio_offset)
> +#define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \
> + dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
> + dev_priv->info.display_mmio_offset)
> +#define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \
> + dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
> + dev_priv->info.display_mmio_offset)
I guess this guy could should be called _MMIO_CURSOR2(). But that's
material for another patch.
This one is
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> +
> #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
> #define _MASKED_FIELD(mask, value) ({ \
> if (__builtin_constant_p(mask)) \
> @@ -4052,10 +4066,6 @@ enum {
> #define TRANSCODER_DSI0_OFFSET 0x6b000
> #define TRANSCODER_DSI1_OFFSET 0x6b800
>
> -#define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \
> - dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
> - dev_priv->info.display_mmio_offset)
> -
> #define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A)
> #define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A)
> #define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A)
> @@ -5624,10 +5634,6 @@ enum {
> #define PIPE_DSI0_OFFSET 0x7b000
> #define PIPE_DSI1_OFFSET 0x7b800
>
> -#define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \
> - dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
> - dev_priv->info.display_mmio_offset)
> -
> #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF)
> #define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL)
> #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
> @@ -6075,10 +6081,6 @@ enum {
> #define _CURBBASE_IVB 0x71084
> #define _CURBPOS_IVB 0x71088
>
> -#define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \
> - dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
> - dev_priv->info.display_mmio_offset)
> -
> #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
> #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
> #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
> --
> 2.11.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: remove palette_offsets from device info in favor of _PICK()
2018-10-31 11:04 [PATCH 1/4] drm/i915: remove palette_offsets from device info in favor of _PICK() Jani Nikula
` (4 preceding siblings ...)
2018-10-31 12:59 ` [PATCH 1/4] " Ville Syrjälä
@ 2018-11-01 17:09 ` Patchwork
2018-11-01 19:04 ` ✓ Fi.CI.IGT: " Patchwork
6 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2018-11-01 17:09 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/4] drm/i915: remove palette_offsets from device info in favor of _PICK()
URL : https://patchwork.freedesktop.org/series/51802/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5067 -> Patchwork_10693 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/51802/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_10693 that come from known issues:
=== IGT changes ===
==== Possible fixes ====
igt@gem_cpu_reloc@basic:
fi-skl-6700hq: INCOMPLETE (fdo#108011) -> PASS
igt@gem_exec_suspend@basic-s3:
fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS
igt@kms_frontbuffer_tracking@basic:
fi-byt-clapper: FAIL (fdo#103167) -> PASS
igt@prime_vgem@basic-fence-flip:
fi-cfl-8700k: FAIL (fdo#104008) -> PASS
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
fdo#108011 https://bugs.freedesktop.org/show_bug.cgi?id=108011
== Participating hosts (45 -> 42) ==
Additional (1): fi-pnv-d510
Missing (4): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_5067 -> Patchwork_10693
CI_DRM_5067: f784551fd7bad04465b1455a1d05b0e0aeae72a6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4704: ace031dcb1e8bf2b32b4b0d54a55eb30e8f41d6f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10693: 43def29e2750ea3b86c644ba34e59cf485b1cfa4 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
43def29e2750 drm/i915: also group device info array helper macros with others
349c35c1a4ed drm/i915: reorder and reindent the register choosing helper wrappers
d24b498ecce0 drm/i915: define _MMIO_PLANE() in terms of _PLANE() not _MMIO_PIPE()
50641c5b1ecb drm/i915: remove palette_offsets from device info in favor of _PICK()
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10693/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [1/4] drm/i915: remove palette_offsets from device info in favor of _PICK()
2018-10-31 11:04 [PATCH 1/4] drm/i915: remove palette_offsets from device info in favor of _PICK() Jani Nikula
` (5 preceding siblings ...)
2018-11-01 17:09 ` ✓ Fi.CI.BAT: success for series starting with [1/4] " Patchwork
@ 2018-11-01 19:04 ` Patchwork
6 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2018-11-01 19:04 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/4] drm/i915: remove palette_offsets from device info in favor of _PICK()
URL : https://patchwork.freedesktop.org/series/51802/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5067_full -> Patchwork_10693_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_10693_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10693_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10693_full:
=== IGT changes ===
==== Warnings ====
igt@kms_vblank@pipe-b-wait-idle:
shard-snb: SKIP -> PASS +1
== Known issues ==
Here are the changes found in Patchwork_10693_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@gem_exec_schedule@pi-ringfull-bsd:
shard-skl: NOTRUN -> FAIL (fdo#103158)
igt@gem_exec_whisper@normal:
shard-skl: PASS -> TIMEOUT (fdo#108592)
igt@kms_available_modes_crc@available_mode_test_crc:
shard-apl: PASS -> FAIL (fdo#106641)
igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) +1
igt@kms_cursor_crc@cursor-256x85-random:
shard-glk: PASS -> FAIL (fdo#103232)
igt@kms_cursor_crc@cursor-64x21-random:
shard-apl: PASS -> FAIL (fdo#103232) +1
igt@kms_draw_crc@draw-method-xrgb8888-blt-untiled:
shard-skl: PASS -> FAIL (fdo#103232)
igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen:
shard-glk: PASS -> FAIL (fdo#103167) +2
igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-pwrite:
shard-skl: PASS -> FAIL (fdo#103167, fdo#105682)
igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
shard-skl: NOTRUN -> FAIL (fdo#108145) +2
igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
shard-apl: PASS -> FAIL (fdo#103166) +2
igt@kms_plane_multiple@atomic-pipe-b-tiling-x:
shard-glk: PASS -> FAIL (fdo#103166)
igt@kms_setmode@basic:
shard-apl: PASS -> FAIL (fdo#99912)
igt@kms_vblank@pipe-b-ts-continuation-suspend:
shard-skl: PASS -> INCOMPLETE (fdo#104108, fdo#107773)
igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
shard-apl: PASS -> INCOMPLETE (fdo#103927)
igt@perf_pmu@semaphore-wait-vecs0:
shard-snb: SKIP -> INCOMPLETE (fdo#105411)
igt@pm_rpm@cursor:
shard-skl: PASS -> INCOMPLETE (fdo#107807)
==== Possible fixes ====
igt@drv_hangman@error-state-capture-blt:
shard-apl: INCOMPLETE (fdo#103927) -> PASS
igt@gem_ppgtt@blt-vs-render-ctxn:
shard-skl: TIMEOUT (fdo#108039) -> PASS
igt@kms_busy@extended-modeset-hang-newfb-render-c:
shard-hsw: DMESG-WARN (fdo#107956) -> PASS
igt@kms_chv_cursor_fail@pipe-b-256x256-right-edge:
shard-skl: FAIL (fdo#104671) -> PASS
igt@kms_color@pipe-c-degamma:
shard-apl: FAIL (fdo#104782) -> PASS
igt@kms_cursor_crc@cursor-128x128-dpms:
shard-glk: FAIL (fdo#103232) -> PASS
igt@kms_cursor_crc@cursor-256x85-sliding:
shard-apl: FAIL (fdo#103232) -> PASS +1
igt@kms_cursor_crc@cursor-64x21-random:
shard-hsw: DMESG-WARN (fdo#102614) -> PASS
igt@kms_cursor_crc@cursor-size-change:
shard-hsw: DMESG-FAIL (fdo#103232, fdo#102614) -> PASS
igt@kms_cursor_legacy@cursora-vs-flipa-toggle:
shard-glk: DMESG-WARN (fdo#105763, fdo#106538) -> PASS
igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled:
shard-skl: FAIL (fdo#103184) -> PASS
igt@kms_flip@plain-flip-fb-recreate:
shard-skl: FAIL (fdo#100368) -> PASS
igt@kms_flip_tiling@flip-changes-tiling-yf:
shard-skl: FAIL (fdo#108228, fdo#108303) -> PASS
igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-render:
shard-glk: FAIL (fdo#103167) -> PASS +1
igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
shard-apl: FAIL (fdo#103166) -> PASS +3
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158
fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184
fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fdo#104671 https://bugs.freedesktop.org/show_bug.cgi?id=104671
fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782
fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
fdo#105682 https://bugs.freedesktop.org/show_bug.cgi?id=105682
fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763
fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538
fdo#106641 https://bugs.freedesktop.org/show_bug.cgi?id=106641
fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773
fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807
fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
fdo#108039 https://bugs.freedesktop.org/show_bug.cgi?id=108039
fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
fdo#108228 https://bugs.freedesktop.org/show_bug.cgi?id=108228
fdo#108303 https://bugs.freedesktop.org/show_bug.cgi?id=108303
fdo#108592 https://bugs.freedesktop.org/show_bug.cgi?id=108592
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
== Participating hosts (6 -> 6) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_5067 -> Patchwork_10693
CI_DRM_5067: f784551fd7bad04465b1455a1d05b0e0aeae72a6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4704: ace031dcb1e8bf2b32b4b0d54a55eb30e8f41d6f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10693: 43def29e2750ea3b86c644ba34e59cf485b1cfa4 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10693/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2018-11-01 19:04 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-10-31 11:04 [PATCH 1/4] drm/i915: remove palette_offsets from device info in favor of _PICK() Jani Nikula
2018-10-31 11:04 ` [PATCH 2/4] drm/i915: define _MMIO_PLANE() in terms of _PLANE() not _MMIO_PIPE() Jani Nikula
2018-10-31 13:00 ` Ville Syrjälä
2018-10-31 11:04 ` [PATCH 3/4] drm/i915: reorder and reindent the register choosing helper wrappers Jani Nikula
2018-10-31 13:02 ` Ville Syrjälä
2018-10-31 11:04 ` [PATCH 4/4] drm/i915: also group device info array helper macros with others Jani Nikula
2018-10-31 13:05 ` Ville Syrjälä
2018-10-31 12:57 ` ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: remove palette_offsets from device info in favor of _PICK() Patchwork
2018-10-31 12:59 ` [PATCH 1/4] " Ville Syrjälä
2018-11-01 17:09 ` ✓ Fi.CI.BAT: success for series starting with [1/4] " Patchwork
2018-11-01 19:04 ` ✓ Fi.CI.IGT: " Patchwork
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.