From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Wed, 31 Oct 2018 18:15:56 +0100 Subject: [U-Boot] [PATCH 03/13] mmc: tmio: Do not set divider to 1 in DDR mode In-Reply-To: <20181031171606.13561-1-marek.vasut+renesas@gmail.com> References: <20181031171606.13561-1-marek.vasut+renesas@gmail.com> Message-ID: <20181031171606.13561-3-marek.vasut+renesas@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de The TMIO core has a quirk where divider == 1 must not be set in DDR modes. Handle this by setting divider to 2, as suggested in the documentation. Signed-off-by: Marek Vasut Cc: Masahiro Yamada --- drivers/mmc/tmio-common.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c index 9eb2984ed3..072171d4b3 100644 --- a/drivers/mmc/tmio-common.c +++ b/drivers/mmc/tmio-common.c @@ -565,6 +565,10 @@ static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv, divisor = DIV_ROUND_UP(mclk, mmc->clock); + /* Do not set divider to 0xff in DDR mode */ + if (mmc->ddr_mode && (divisor == 1)) + divisor = 2; + if (divisor <= 1) val = (priv->caps & TMIO_SD_CAP_RCAR) ? TMIO_SD_CLKCTL_RCAR_DIV1 : TMIO_SD_CLKCTL_DIV1; -- 2.18.0