Re: [PATCH v8 29/38] drm/i915/icl: Add DSS_CTL Registers

[Manasi Navare <manasi.d.navare@intel.com>]

On Thu, Nov 01, 2018 at 05:27:47PM +0200, Jani Nikula wrote:
> On Tue, 30 Oct 2018, Jani Nikula <jani.nikula@intel.com> wrote:
> > From: Anusha Srivatsa <anusha.srivatsa@intel.com>
> >
> > Add defines for DSS_CTL registers.
> > These registers specify the big joiner, splitter,
> > overlap pixels and info regarding
> > compression enabled on left or right branch.
> >
> > v2:
> > - rebase. Remove overlapping defines(James Ausmus)
> > - Rename the register to ICL_DSS_CTL1/2_PIPE_ (manasi)
> > - take pixels as an argument for overlap.(Manasi)
> >
> > v3:
> > - rebase. merge DSS_CTL1/2 introduced in Madhav's patch
> >   to avoid confusion (madhav chauhan)
> > - Rename registers in accordance to BSpec (Madhav, Rodrigo)
> > - Add define to conditionally check the buffer target depth (James Ausmus)
> >
> > v4:
> > - remove redundant definitions.(madhav)
> >
> > v5:
> > - Add mask for overlap pixels.
> > - Code Style changes.(Madhav)
> > v6:
> > - Code style changes. (Madhav)
> >
> > Suggested-by: Madhav Chauhan <madhav.chauhan@intel.com>
> > Cc: Madhav Chauhan <madhav.chauhan@intel.com>
> > cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: James Ausmus <james.ausmus@intel.com>
> > Cc: Gaurav Singh <gaurav.k.singh@intel.com>
> > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> 
> Pushed to dinq.

This does not have changes mentioned in v3, not the latest patch.
Latest patch is this one:

https://patchwork.freedesktop.org/patch/258331/

> 
> BR,
> Jani.
> 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h | 33 +++++++++++++++++++++++++++++++++
> >  1 file changed, 33 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 639667d0fb00..b9aaa71dabe2 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -10033,6 +10033,39 @@ enum skl_power_gate {
> >  						    _ICL_DSI_IO_MODECTL_1)
> >  #define  COMBO_PHY_MODE_DSI				(1 << 0)
> >  
> > +/* Display Stream Splitter Control */
> > +#define DSS_CTL1				_MMIO(0x67400)
> > +#define  SPLITTER_ENABLE			(1 << 31)
> > +#define  JOINER_ENABLE				(1 << 30)
> > +#define  DUAL_LINK_MODE_INTERLEAVE		(1 << 24)
> > +#define  DUAL_LINK_MODE_FRONTBACK		(0 << 24)
> > +#define  OVERLAP_PIXELS_MASK			(0xf << 16)
> > +#define  OVERLAP_PIXELS(pixels)			((pixels) << 16)
> > +#define  LEFT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
> > +#define  LEFT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
> > +#define  MAX_DL_BUFFER_TARGET_DEPTH		0x5A0
> > +
> > +#define DSS_CTL2				_MMIO(0x67404)
> > +#define  LEFT_BRANCH_VDSC_ENABLE		(1 << 31)
> > +#define  RIGHT_BRANCH_VDSC_ENABLE		(1 << 15)
> > +#define  RIGHT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
> > +#define  RIGHT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
> > +
> > +#define _PIPE_DSS_CTL1_PB			0x78200
> > +#define _PIPE_DSS_CTL1_PC			0x78400

This should have been _ICL_PIPE_DSS_CTL1_PB/PC as per the latest patch

Manasi

> > +#define PIPE_DSS_CTL1(pipe)			_MMIO_PIPE((pipe) - PIPE_B, \
> > +							   _PIPE_DSS_CTL1_PB, \
> > +							   _PIPE_DSS_CTL1_PC)
> > +#define  BIG_JOINER_ENABLE			(1 << 29)
> > +#define  MASTER_BIG_JOINER_ENABLE		(1 << 28)
> > +#define  VGA_CENTERING_ENABLE			(1 << 27)
> > +
> > +#define _PIPE_DSS_CTL2_PB			0x78204
> > +#define _PIPE_DSS_CTL2_PC			0x78404
> > +#define PIPE_DSS_CTL2(pipe)			_MMIO_PIPE((pipe) - PIPE_B, \
> > +							   _PIPE_DSS_CTL2_PB, \
> > +							   _PIPE_DSS_CTL2_PC)
> > +
> >  #define BXT_P_DSI_REGULATOR_CFG			_MMIO(0x160020)
> >  #define  STAP_SELECT					(1 << 0)
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center
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