[PATCH v10 00/15] drm/i915/icl: dsi enabling

[PATCH v10 00/15] drm/i915/icl: dsi enabling

[Jani Nikula]

Next version of [1]. Sorry for the spam, needed to get the authorship
straight. Fixed power domains and compute config hook initialization.

BR,
Jani.

[1] https://patchwork.freedesktop.org/series/51011/


Jani Nikula (1):
  drm/i915/icl: add dummy DSI GPIO element execution function

Madhav Chauhan (14):
  drm/i915/icl: Allocate DSI encoder/connector
  drm/i915/icl: Fill DSI ports info
  drm/i915/icl: Allocate DSI hosts and imlement host transfer
  drm/i915/icl: Add get config functionality for DSI
  drm/i915/icl: Get HW state for DSI encoder
  drm/i915/icl: Add DSI encoder remaining functions
  drm/i915/icl: Configure DSI Dual link mode
  drm/i915/icl: Consider DSI for getting transcoder state
  drm/i915/icl: Get pipe timings for DSI
  drm/i915/icl: Define missing bitfield for shortplug reg
  drm/i915/icl: Define Panel power ctrl register
  drm/i915/icl: Define display GPIO pins for DSI
  HACK: drm/i915/icl: Add changes to program DSI panel GPIOs
  HACK: drm/i915/icl: Configure backlight functions for DSI

 drivers/gpu/drm/i915/i915_reg.h      |  12 +
 drivers/gpu/drm/i915/icl_dsi.c       | 417 ++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_display.c |  34 ++-
 drivers/gpu/drm/i915/intel_dsi_vbt.c |  58 ++++-
 drivers/gpu/drm/i915/intel_panel.c   |   3 +-
 5 files changed, 505 insertions(+), 19 deletions(-)

-- 
2.11.0

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[PATCH v10 01/15] drm/i915/icl: Allocate DSI encoder/connector

[Jani Nikula]

From: Madhav Chauhan <madhav.chauhan@intel.com>

This patch allocates memory for DSI encoder and connector
which will be used for various DSI encoder/connector operations
and attaching the same to DRM subsystem. This patch also extracts
DSI modes info from VBT and save the desired mode info to connector.

v2 by Jani:
 - Drop GEN11 prefix from encoder name
 - Drop extra parenthesis
 - Drop extra local variable
 - Squash encoder power domain here

v3 by Jani:
 - Squash connector and connector helper functions here
 - Move intel_dsi_vbt_init call here

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c | 117 ++++++++++++++++++++++++++++++++++++++---
 1 file changed, 109 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 01f422df8c23..a40083a7eb6a 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -26,6 +26,7 @@
  */
 
 #include <drm/drm_mipi_dsi.h>
+#include <drm/drm_atomic_helper.h>
 #include "intel_dsi.h"
 
 static inline int header_credits_available(struct drm_i915_private *dev_priv,
@@ -799,10 +800,9 @@ static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
 	wait_for_cmds_dispatched_to_panel(encoder);
 }
 
-static void __attribute__((unused))
-gen11_dsi_pre_enable(struct intel_encoder *encoder,
-		     const struct intel_crtc_state *pipe_config,
-		     const struct drm_connector_state *conn_state)
+static void gen11_dsi_pre_enable(struct intel_encoder *encoder,
+				 const struct intel_crtc_state *pipe_config,
+				 const struct drm_connector_state *conn_state)
 {
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 
@@ -945,10 +945,9 @@ static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
 	}
 }
 
-static void __attribute__((unused)) gen11_dsi_disable(
-			struct intel_encoder *encoder,
-			const struct intel_crtc_state *old_crtc_state,
-			const struct drm_connector_state *old_conn_state)
+static void gen11_dsi_disable(struct intel_encoder *encoder,
+			      const struct intel_crtc_state *old_crtc_state,
+			      const struct drm_connector_state *old_conn_state)
 {
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 
@@ -972,10 +971,112 @@ static void __attribute__((unused)) gen11_dsi_disable(
 	gen11_dsi_disable_io_power(encoder);
 }
 
+static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
+{
+	intel_encoder_destroy(encoder);
+}
+
+static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = {
+	.destroy = gen11_dsi_encoder_destroy,
+};
+
+static const struct drm_connector_funcs gen11_dsi_connector_funcs = {
+	.late_register = intel_connector_register,
+	.early_unregister = intel_connector_unregister,
+	.destroy = intel_connector_destroy,
+	.fill_modes = drm_helper_probe_single_connector_modes,
+	.atomic_get_property = intel_digital_connector_atomic_get_property,
+	.atomic_set_property = intel_digital_connector_atomic_set_property,
+	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+	.atomic_duplicate_state = intel_digital_connector_duplicate_state,
+};
+
+static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = {
+	.get_modes = intel_dsi_get_modes,
+	.mode_valid = intel_dsi_mode_valid,
+	.atomic_check = intel_digital_connector_atomic_check,
+};
+
 void icl_dsi_init(struct drm_i915_private *dev_priv)
 {
+	struct drm_device *dev = &dev_priv->drm;
+	struct intel_dsi *intel_dsi;
+	struct intel_encoder *encoder;
+	struct intel_connector *intel_connector;
+	struct drm_connector *connector;
+	struct drm_display_mode *scan, *fixed_mode = NULL;
 	enum port port;
 
 	if (!intel_bios_is_dsi_present(dev_priv, &port))
 		return;
+
+	intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
+	if (!intel_dsi)
+		return;
+
+	intel_connector = intel_connector_alloc();
+	if (!intel_connector) {
+		kfree(intel_dsi);
+		return;
+	}
+
+	encoder = &intel_dsi->base;
+	intel_dsi->attached_connector = intel_connector;
+	connector = &intel_connector->base;
+
+	/* register DSI encoder with DRM subsystem */
+	drm_encoder_init(dev, &encoder->base, &gen11_dsi_encoder_funcs,
+			 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port));
+
+	encoder->pre_enable = gen11_dsi_pre_enable;
+	encoder->disable = gen11_dsi_disable;
+	encoder->port = port;
+	encoder->type = INTEL_OUTPUT_DSI;
+	encoder->cloneable = 0;
+	encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
+	encoder->power_domain = POWER_DOMAIN_PORT_DSI;
+
+	/* register DSI connector with DRM subsystem */
+	drm_connector_init(dev, connector, &gen11_dsi_connector_funcs,
+			   DRM_MODE_CONNECTOR_DSI);
+	drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs);
+	connector->display_info.subpixel_order = SubPixelHorizontalRGB;
+	connector->interlace_allowed = false;
+	connector->doublescan_allowed = false;
+
+	/* attach connector to encoder */
+	intel_connector_attach_encoder(intel_connector, encoder);
+
+	/* fill mode info from VBT */
+	mutex_lock(&dev->mode_config.mutex);
+	intel_dsi_vbt_get_modes(intel_dsi);
+	list_for_each_entry(scan, &connector->probed_modes, head) {
+		if (scan->type & DRM_MODE_TYPE_PREFERRED) {
+			fixed_mode = drm_mode_duplicate(dev, scan);
+			break;
+		}
+	}
+	mutex_unlock(&dev->mode_config.mutex);
+
+	if (!fixed_mode) {
+		DRM_ERROR("DSI fixed mode info missing\n");
+		goto err;
+	}
+
+	connector->display_info.width_mm = fixed_mode->width_mm;
+	connector->display_info.height_mm = fixed_mode->height_mm;
+	intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
+	intel_panel_setup_backlight(connector, INVALID_PIPE);
+
+	if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
+		DRM_DEBUG_KMS("no device found\n");
+		goto err;
+	}
+
+	return;
+
+err:
+	drm_encoder_cleanup(&encoder->base);
+	kfree(intel_dsi);
+	kfree(intel_connector);
 }
-- 
2.11.0

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[PATCH v10 02/15] drm/i915/icl: Fill DSI ports info

[Jani Nikula]

From: Madhav Chauhan <madhav.chauhan@intel.com>

This patch fills backlight, CABC and general port
info for Gen11 DSI.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index a40083a7eb6a..fe408ff77924 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -1068,6 +1068,14 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
 	intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
 	intel_panel_setup_backlight(connector, INVALID_PIPE);
 
+	if (dev_priv->vbt.dsi.config->dual_link)
+		intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B);
+	else
+		intel_dsi->ports = BIT(port);
+
+	intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
+	intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
+
 	if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
 		DRM_DEBUG_KMS("no device found\n");
 		goto err;
-- 
2.11.0

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[PATCH v10 03/15] drm/i915/icl: Allocate DSI hosts and imlement host transfer

[Jani Nikula]

From: Madhav Chauhan <madhav.chauhan@intel.com>

Allocate DSI host structure for each DSI port available on gen11 and
register them with DSI fwk of DRM. Some of the DSI host operations are
also registered as part of this.

Retrieves DSI pkt (from DSI msg) to be sent over DSI link using DRM DSI
exported functions. A wrapper function is also added as "DSI host
transfer" for sending DSI data/cmd. Add DSI packet payload to command
payload queue using credit based mechanism for *long* packets.

v2 by Jani:
 - indentation
 - Use the new credit available helper
 - Use int for free_credits
 - Add intel_dsi local variable for better code flow
 - Use the new credit available helper
 - Use int for free_credits, i, and j

v3 by Jani:
 - Squash DSI host allocation and transfer patches together

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c | 147 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 147 insertions(+)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index fe408ff77924..806b8c323b53 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -108,6 +108,90 @@ static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
 	}
 }
 
+static bool add_payld_to_queue(struct intel_dsi_host *host, const u8 *data,
+			       u32 len)
+{
+	struct intel_dsi *intel_dsi = host->intel_dsi;
+	struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
+	enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
+	int free_credits;
+	int i, j;
+
+	for (i = 0; i < len; i += 4) {
+		u32 tmp = 0;
+
+		free_credits = payload_credits_available(dev_priv, dsi_trans);
+		if (free_credits < 1) {
+			DRM_ERROR("Payload credit not available\n");
+			return false;
+		}
+
+		for (j = 0; j < min_t(u32, len - i, 4); j++)
+			tmp |= *data++ << 8 * j;
+
+		I915_WRITE(DSI_CMD_TXPYLD(dsi_trans), tmp);
+	}
+
+	return true;
+}
+
+static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
+			    struct mipi_dsi_packet pkt, bool enable_lpdt)
+{
+	struct intel_dsi *intel_dsi = host->intel_dsi;
+	struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
+	enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
+	u32 tmp;
+	int free_credits;
+
+	/* check if header credit available */
+	free_credits = header_credits_available(dev_priv, dsi_trans);
+	if (free_credits < 1) {
+		DRM_ERROR("send pkt header failed, not enough hdr credits\n");
+		return -1;
+	}
+
+	tmp = I915_READ(DSI_CMD_TXHDR(dsi_trans));
+
+	if (pkt.payload)
+		tmp |= PAYLOAD_PRESENT;
+	else
+		tmp &= ~PAYLOAD_PRESENT;
+
+	tmp &= ~VBLANK_FENCE;
+
+	if (enable_lpdt)
+		tmp |= LP_DATA_TRANSFER;
+
+	tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK);
+	tmp |= ((pkt.header[0] & VC_MASK) << VC_SHIFT);
+	tmp |= ((pkt.header[0] & DT_MASK) << DT_SHIFT);
+	tmp |= (pkt.header[1] << PARAM_WC_LOWER_SHIFT);
+	tmp |= (pkt.header[2] << PARAM_WC_UPPER_SHIFT);
+	I915_WRITE(DSI_CMD_TXHDR(dsi_trans), tmp);
+
+	return 0;
+}
+
+static int dsi_send_pkt_payld(struct intel_dsi_host *host,
+			      struct mipi_dsi_packet pkt)
+{
+	/* payload queue can accept *256 bytes*, check limit */
+	if (pkt.payload_length > MAX_PLOAD_CREDIT * 4) {
+		DRM_ERROR("payload size exceeds max queue limit\n");
+		return -1;
+	}
+
+	/* load data into command payload queue */
+	if (!add_payld_to_queue(host, pkt.payload,
+				pkt.payload_length)) {
+		DRM_ERROR("adding payload to queue failed\n");
+		return -1;
+	}
+
+	return 0;
+}
+
 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -997,6 +1081,58 @@ static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs
 	.atomic_check = intel_digital_connector_atomic_check,
 };
 
+static int gen11_dsi_host_attach(struct mipi_dsi_host *host,
+				 struct mipi_dsi_device *dsi)
+{
+	return 0;
+}
+
+static int gen11_dsi_host_detach(struct mipi_dsi_host *host,
+				 struct mipi_dsi_device *dsi)
+{
+	return 0;
+}
+
+static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host,
+				       const struct mipi_dsi_msg *msg)
+{
+	struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
+	struct mipi_dsi_packet dsi_pkt;
+	ssize_t ret;
+	bool enable_lpdt = false;
+
+	ret = mipi_dsi_create_packet(&dsi_pkt, msg);
+	if (ret < 0)
+		return ret;
+
+	if (msg->flags & MIPI_DSI_MSG_USE_LPM)
+		enable_lpdt = true;
+
+	/* send packet header */
+	ret  = dsi_send_pkt_hdr(intel_dsi_host, dsi_pkt, enable_lpdt);
+	if (ret < 0)
+		return ret;
+
+	/* only long packet contains payload */
+	if (mipi_dsi_packet_format_is_long(msg->type)) {
+		ret = dsi_send_pkt_payld(intel_dsi_host, dsi_pkt);
+		if (ret < 0)
+			return ret;
+	}
+
+	//TODO: add payload receive code if needed
+
+	ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length;
+
+	return ret;
+}
+
+static const struct mipi_dsi_host_ops gen11_dsi_host_ops = {
+	.attach = gen11_dsi_host_attach,
+	.detach = gen11_dsi_host_detach,
+	.transfer = gen11_dsi_host_transfer,
+};
+
 void icl_dsi_init(struct drm_i915_private *dev_priv)
 {
 	struct drm_device *dev = &dev_priv->drm;
@@ -1068,6 +1204,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
 	intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
 	intel_panel_setup_backlight(connector, INVALID_PIPE);
 
+
 	if (dev_priv->vbt.dsi.config->dual_link)
 		intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B);
 	else
@@ -1076,6 +1213,16 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
 	intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
 	intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
 
+	for_each_dsi_port(port, intel_dsi->ports) {
+		struct intel_dsi_host *host;
+
+		host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port);
+		if (!host)
+			goto err;
+
+		intel_dsi->dsi_hosts[port] = host;
+	}
+
 	if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
 		DRM_DEBUG_KMS("no device found\n");
 		goto err;
-- 
2.11.0

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[PATCH v10 04/15] drm/i915/icl: Add get config functionality for DSI

[Jani Nikula]

From: Madhav Chauhan <madhav.chauhan@intel.com>

This patch implements the functionality for getting PIPE
configuration to which DSI encoder is connected. Used during
the atomic modeset.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 806b8c323b53..b47e837f4493 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -1055,6 +1055,19 @@ static void gen11_dsi_disable(struct intel_encoder *encoder,
 	gen11_dsi_disable_io_power(encoder);
 }
 
+static void gen11_dsi_get_config(struct intel_encoder *encoder,
+				 struct intel_crtc_state *pipe_config)
+{
+	struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
+						   base);
+	u32 pixel_clk;
+
+	//FIXME: Calculate pixel clock using PLL functions once implemented.
+	pixel_clk = intel_dsi->pclk;
+	pipe_config->base.adjusted_mode.crtc_clock = pixel_clk;
+	pipe_config->port_clock = pixel_clk;
+}
+
 static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
 {
 	intel_encoder_destroy(encoder);
@@ -1167,6 +1180,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
 	encoder->pre_enable = gen11_dsi_pre_enable;
 	encoder->disable = gen11_dsi_disable;
 	encoder->port = port;
+	encoder->get_config = gen11_dsi_get_config;
 	encoder->type = INTEL_OUTPUT_DSI;
 	encoder->cloneable = 0;
 	encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
-- 
2.11.0

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[PATCH v10 05/15] drm/i915/icl: Get HW state for DSI encoder

[Jani Nikula]

From: Madhav Chauhan <madhav.chauhan@intel.com>

This patch read out the current hw state for DSI and
return true if encoder is active.

v2 by Jani:
 - Squash connector get hw state hook here
 - Squash encode get hw state fix here

v3 by Jani:
 - Add encoder->get_power_domains() (Imre)

v4 by Jani:
 - Make encoder->get_power_domains() sensible... (Imre)

Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c | 57 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 57 insertions(+)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index b47e837f4493..1881825432cb 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -1068,6 +1068,60 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
 	pipe_config->port_clock = pixel_clk;
 }
 
+static u64 gen11_dsi_get_power_domains(struct intel_encoder *encoder,
+				       struct intel_crtc_state *crtc_state)
+{
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	u64 domains = 0;
+	enum port port;
+
+	for_each_dsi_port(port, intel_dsi->ports)
+		domains |= (port == PORT_A ? POWER_DOMAIN_PORT_DDI_A_IO :
+			    POWER_DOMAIN_PORT_DDI_B_IO);
+
+	return domains;
+}
+
+static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
+				   enum pipe *pipe)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	u32 tmp;
+	enum port port;
+	enum transcoder dsi_trans;
+	bool ret = false;
+
+	if (!intel_display_power_get_if_enabled(dev_priv,
+						encoder->power_domain))
+		return false;
+
+	for_each_dsi_port(port, intel_dsi->ports) {
+		dsi_trans = dsi_port_to_transcoder(port);
+		tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
+		switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
+		case TRANS_DDI_EDP_INPUT_A_ON:
+			*pipe = PIPE_A;
+			break;
+		case TRANS_DDI_EDP_INPUT_B_ONOFF:
+			*pipe = PIPE_B;
+			break;
+		case TRANS_DDI_EDP_INPUT_C_ONOFF:
+			*pipe = PIPE_C;
+			break;
+		default:
+			DRM_ERROR("Invalid PIPE input\n");
+			goto out;
+		}
+
+		tmp = I915_READ(PIPECONF(dsi_trans));
+		ret = tmp & PIPECONF_ENABLE;
+	}
+out:
+	intel_display_power_put(dev_priv, encoder->power_domain);
+	return ret;
+}
+
 static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
 {
 	intel_encoder_destroy(encoder);
@@ -1181,10 +1235,12 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
 	encoder->disable = gen11_dsi_disable;
 	encoder->port = port;
 	encoder->get_config = gen11_dsi_get_config;
+	encoder->get_hw_state = gen11_dsi_get_hw_state;
 	encoder->type = INTEL_OUTPUT_DSI;
 	encoder->cloneable = 0;
 	encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
 	encoder->power_domain = POWER_DOMAIN_PORT_DSI;
+	encoder->get_power_domains = gen11_dsi_get_power_domains;
 
 	/* register DSI connector with DRM subsystem */
 	drm_connector_init(dev, connector, &gen11_dsi_connector_funcs,
@@ -1193,6 +1249,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
 	connector->display_info.subpixel_order = SubPixelHorizontalRGB;
 	connector->interlace_allowed = false;
 	connector->doublescan_allowed = false;
+	intel_connector->get_hw_state = intel_connector_get_hw_state;
 
 	/* attach connector to encoder */
 	intel_connector_attach_encoder(intel_connector, encoder);
-- 
2.11.0

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[PATCH v10 06/15] drm/i915/icl: Add DSI encoder remaining functions

[Jani Nikula]

From: Madhav Chauhan <madhav.chauhan@intel.com>

This patch implements compute config for Gen11 DSI encoder which is
required at the time of modeset.

v2 by Jani:
 - drop the enable nop hook
 - fixed_mode is always true
 - HAS_GMCH_DISPLAY() is always false

v3 by Jani:
 - set encoder->compute_config dropped during rebase

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 1881825432cb..8cdf736c2bbd 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -1068,6 +1068,37 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
 	pipe_config->port_clock = pixel_clk;
 }
 
+static bool gen11_dsi_compute_config(struct intel_encoder *encoder,
+				     struct intel_crtc_state *pipe_config,
+				     struct drm_connector_state *conn_state)
+{
+	struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
+						   base);
+	struct intel_connector *intel_connector = intel_dsi->attached_connector;
+	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
+	const struct drm_display_mode *fixed_mode =
+					intel_connector->panel.fixed_mode;
+	struct drm_display_mode *adjusted_mode =
+					&pipe_config->base.adjusted_mode;
+
+	intel_fixed_panel_mode(fixed_mode, adjusted_mode);
+	intel_pch_panel_fitting(crtc, pipe_config, conn_state->scaling_mode);
+
+	adjusted_mode->flags = 0;
+
+	/* Dual link goes to trancoder DSI'0' */
+	if (intel_dsi->ports == BIT(PORT_B))
+		pipe_config->cpu_transcoder = TRANSCODER_DSI_1;
+	else
+		pipe_config->cpu_transcoder = TRANSCODER_DSI_0;
+
+	pipe_config->clock_set = true;
+
+	//TODO: Add check if DSI PLL calculation is done
+
+	return true;
+}
+
 static u64 gen11_dsi_get_power_domains(struct intel_encoder *encoder,
 				       struct intel_crtc_state *crtc_state)
 {
@@ -1235,6 +1266,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
 	encoder->disable = gen11_dsi_disable;
 	encoder->port = port;
 	encoder->get_config = gen11_dsi_get_config;
+	encoder->compute_config = gen11_dsi_compute_config;
 	encoder->get_hw_state = gen11_dsi_get_hw_state;
 	encoder->type = INTEL_OUTPUT_DSI;
 	encoder->cloneable = 0;
-- 
2.11.0

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[PATCH v10 07/15] drm/i915/icl: Configure DSI Dual link mode

[Jani Nikula]

From: Madhav Chauhan <madhav.chauhan@intel.com>

This patch configures DSI video mode dual link by
programming DSS_CTL registers.

v2: Use new bitfield definitions from Anusha's patch
    Correct register to be programmed and use max
    depth buffer value (James)

v3 by Jani:
 - checkpatch fixes

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c | 42 +++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 41 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 8cdf736c2bbd..c4488aa0202a 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -257,6 +257,45 @@ static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
 	}
 }
 
+static void configure_dual_link_mode(struct intel_encoder *encoder,
+				     const struct intel_crtc_state *pipe_config)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	u32 dss_ctl1;
+
+	dss_ctl1 = I915_READ(DSS_CTL1);
+	dss_ctl1 |= SPLITTER_ENABLE;
+	dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
+	dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap);
+
+	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
+		const struct drm_display_mode *adjusted_mode =
+					&pipe_config->base.adjusted_mode;
+		u32 dss_ctl2;
+		u16 hactive = adjusted_mode->crtc_hdisplay;
+		u16 dl_buffer_depth;
+
+		dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE;
+		dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap;
+
+		if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH)
+			DRM_ERROR("DL buffer depth exceed max value\n");
+
+		dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
+		dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
+		dss_ctl2 = I915_READ(DSS_CTL2);
+		dss_ctl2 &= ~RIGHT_DL_BUF_TARGET_DEPTH_MASK;
+		dss_ctl2 |= RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
+		I915_WRITE(DSS_CTL2, dss_ctl2);
+	} else {
+		/* Interleave */
+		dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
+	}
+
+	I915_WRITE(DSS_CTL1, dss_ctl1);
+}
+
 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -591,7 +630,8 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 			I915_WRITE(TRANS_DDI_FUNC_CTL2(dsi_trans), tmp);
 		}
 
-		//TODO: configure DSS_CTL1
+		/* configure stream splitting */
+		configure_dual_link_mode(encoder, pipe_config);
 	}
 
 	for_each_dsi_port(port, intel_dsi->ports) {
-- 
2.11.0

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[PATCH v10 08/15] drm/i915/icl: Consider DSI for getting transcoder state

[Jani Nikula]

From: Madhav Chauhan <madhav.chauhan@intel.com>

For Gen11 DSI, we use similar registers like for eDP
to find if DSI encoder is connected or not to a pipe.
This patch refactors existing hsw_get_transcoder_state()
to handle this.

v2 by Jani:
 - Add WARN_ON(dsi && edp) (Ville)

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 31 ++++++++++++++++++++++++-------
 1 file changed, 24 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b219d5858160..affac1eae14b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9370,6 +9370,8 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	enum intel_display_power_domain power_domain;
 	u32 tmp;
+	bool is_dsi = false;
+	bool is_edp = false;
 
 	/*
 	 * The pipe->transcoder mapping is fixed with the exception of the eDP
@@ -9382,26 +9384,41 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
 	 * consistency and less surprising code; it's in always on power).
 	 */
 	tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
-	if (tmp & TRANS_DDI_FUNC_ENABLE) {
-		enum pipe trans_edp_pipe;
+	if (tmp & TRANS_DDI_FUNC_ENABLE)
+		is_edp = true;
+
+	if (IS_ICELAKE(dev_priv)) {
+		tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_DSI_0));
+		if (tmp & TRANS_DDI_FUNC_ENABLE)
+			is_dsi = true;
+	}
+
+	WARN_ON(is_edp && is_dsi);
+
+	if (is_edp || is_dsi) {
+		enum pipe trans_pipe;
 		switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
 		default:
 			WARN(1, "unknown pipe linked to edp transcoder\n");
 			/* fall through */
 		case TRANS_DDI_EDP_INPUT_A_ONOFF:
 		case TRANS_DDI_EDP_INPUT_A_ON:
-			trans_edp_pipe = PIPE_A;
+			trans_pipe = PIPE_A;
 			break;
 		case TRANS_DDI_EDP_INPUT_B_ONOFF:
-			trans_edp_pipe = PIPE_B;
+			trans_pipe = PIPE_B;
 			break;
 		case TRANS_DDI_EDP_INPUT_C_ONOFF:
-			trans_edp_pipe = PIPE_C;
+			trans_pipe = PIPE_C;
 			break;
 		}
 
-		if (trans_edp_pipe == crtc->pipe)
-			pipe_config->cpu_transcoder = TRANSCODER_EDP;
+		if (trans_pipe == crtc->pipe) {
+			if (is_edp)
+				pipe_config->cpu_transcoder = TRANSCODER_EDP;
+			else if (is_dsi)
+				pipe_config->cpu_transcoder = TRANSCODER_DSI_0;
+		}
 	}
 
 	power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
-- 
2.11.0

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[PATCH v10 09/15] drm/i915/icl: Get pipe timings for DSI

[Jani Nikula]

From: Madhav Chauhan <madhav.chauhan@intel.com>

Transcoder timings for Gen11 DSI encoder
is available at pipe level unlike in older platform
where port specific registers need to be accessed.

v2 by Jani:
 - get timings for (!dsi || icl) instead of (dsi && icl).

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index affac1eae14b..c6f62aee0e0c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9553,7 +9553,8 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
 	if (!active)
 		goto out;
 
-	if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
+	if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
+	    IS_ICELAKE(dev_priv)) {
 		haswell_get_ddi_port_state(crtc, pipe_config);
 		intel_get_pipe_timings(crtc, pipe_config);
 	}
-- 
2.11.0

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[PATCH v10 10/15] drm/i915/icl: Define missing bitfield for shortplug reg

[Jani Nikula]

From: Madhav Chauhan <madhav.chauhan@intel.com>

This patch define missing bitfield for shortplug ctl ddi
register which will be used for ICL DSI GPIO programming.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 470b6fd39c4c..dec4ce7a6634 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7694,6 +7694,7 @@ enum {
 #define   ICP_DDIB_HPD_LONG_DETECT		(2 << 4)
 #define   ICP_DDIB_HPD_SHORT_LONG_DETECT	(3 << 4)
 #define   ICP_DDIA_HPD_ENABLE			(1 << 3)
+#define   ICP_DDIA_HPD_OP_DRIVE_1		(1 << 2)
 #define   ICP_DDIA_HPD_STATUS_MASK		(3 << 0)
 #define   ICP_DDIA_HPD_NO_DETECT		(0 << 0)
 #define   ICP_DDIA_HPD_SHORT_DETECT		(1 << 0)
-- 
2.11.0

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[PATCH v10 11/15] drm/i915/icl: Define Panel power ctrl register

[Jani Nikula]

From: Madhav Chauhan <madhav.chauhan@intel.com>

There are two panel power sequencers. Each register
has two addressable instances. This patch defines
both the instances of Panel power control register

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dec4ce7a6634..779fa233eaf6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4612,6 +4612,17 @@ enum {
 #define _PP_STATUS			0x61200
 #define PP_STATUS(pps_idx)		_MMIO_PPS(pps_idx, _PP_STATUS)
 #define   PP_ON				(1 << 31)
+
+#define _PP_CONTROL_1			0xc7204
+#define _PP_CONTROL_2			0xc7304
+#define ICP_PP_CONTROL(x)		_MMIO(((x) == 1) ? _PP_CONTROL_1 : \
+					      _PP_CONTROL_2)
+#define  POWER_CYCLE_DELAY_MASK	(0x1f << 4)
+#define  POWER_CYCLE_DELAY_SHIFT	4
+#define  VDD_OVERRIDE_FORCE		(1 << 3)
+#define  BACKLIGHT_ENABLE		(1 << 2)
+#define  PWR_DOWN_ON_RESET		(1 << 1)
+#define  PWR_STATE_TARGET		(1 << 0)
 /*
  * Indicates that all dependencies of the panel are on:
  *
-- 
2.11.0

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[PATCH v10 12/15] drm/i915/icl: Define display GPIO pins for DSI

[Jani Nikula]

From: Madhav Chauhan <madhav.chauhan@intel.com>

Display Pins are the only GPIOs that need to be used by
driver for DSI panels. So driver should now have its own
implementation to toggle these pins based on GPIO info
received from VBT sequences.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_vbt.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index a72de81f4832..b41ca6436401 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -103,6 +103,18 @@ static struct gpio_map vlv_gpio_table[] = {
 #define CHV_GPIO_PAD_CFG1(f, i)		(0x4400 + (f) * 0x400 + (i) * 8 + 4)
 #define  CHV_GPIO_CFGLOCK		(1 << 31)
 
+/* ICL DSI Display GPIO Pins */
+#define  ICL_GPIO_DDSP_HPD_A		0
+#define  ICL_GPIO_L_VDDEN_1		1
+#define  ICL_GPIO_L_BKLTEN_1		2
+#define  ICL_GPIO_DDPA_CTRLCLK_1	3
+#define  ICL_GPIO_DDPA_CTRLDATA_1	4
+#define  ICL_GPIO_DDSP_HPD_B		5
+#define  ICL_GPIO_L_VDDEN_2		6
+#define  ICL_GPIO_L_BKLTEN_2		7
+#define  ICL_GPIO_DDPA_CTRLCLK_2	8
+#define  ICL_GPIO_DDPA_CTRLDATA_2	9
+
 static inline enum port intel_dsi_seq_port_to_port(u8 port)
 {
 	return port ? PORT_C : PORT_A;
-- 
2.11.0

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[PATCH v10 13/15] drm/i915/icl: add dummy DSI GPIO element execution function

[Jani Nikula]

Add dummy debug logging GPIO element execution function for ICL.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_vbt.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index b41ca6436401..a1a8b3790e61 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -336,6 +336,12 @@ static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
 	gpiod_set_value(gpio_desc, value);
 }
 
+static void icl_exec_gpio(struct drm_i915_private *dev_priv,
+			  u8 gpio_source, u8 gpio_index, bool value)
+{
+	DRM_DEBUG_KMS("Skipping ICL GPIO element execution\n");
+}
+
 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 {
 	struct drm_device *dev = intel_dsi->base.base.dev;
@@ -359,7 +365,9 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 	/* pull up/down */
 	value = *data++ & 1;
 
-	if (IS_VALLEYVIEW(dev_priv))
+	if (IS_ICELAKE(dev_priv))
+		icl_exec_gpio(dev_priv, gpio_source, gpio_index, value);
+	else if (IS_VALLEYVIEW(dev_priv))
 		vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
 	else if (IS_CHERRYVIEW(dev_priv))
 		chv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
-- 
2.11.0

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[PATCH v10 14/15] HACK: drm/i915/icl: Add changes to program DSI panel GPIOs

[Jani Nikula]

From: Madhav Chauhan <madhav.chauhan@intel.com>

For ICELAKE DSI, Display Pins are the only GPIOs
that need to be programmed. So DSI driver should have
its own implementation to toggle these pins based on
GPIO info coming from VBT sequences instead of using
platform specific GPIO driver.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_vbt.c | 38 +++++++++++++++++++++++++++++++++++-
 1 file changed, 37 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index a1a8b3790e61..e6686dbdf462 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -339,7 +339,43 @@ static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
 static void icl_exec_gpio(struct drm_i915_private *dev_priv,
 			  u8 gpio_source, u8 gpio_index, bool value)
 {
-	DRM_DEBUG_KMS("Skipping ICL GPIO element execution\n");
+	u32 val;
+
+	switch (gpio_index) {
+	case ICL_GPIO_DDSP_HPD_A:
+		val = I915_READ(SHOTPLUG_CTL_DDI);
+		val &= ~ICP_DDIA_HPD_ENABLE;
+		I915_WRITE(SHOTPLUG_CTL_DDI, val);
+		val = I915_READ(SHOTPLUG_CTL_DDI);
+
+		if (value)
+			val |= ICP_DDIA_HPD_OP_DRIVE_1;
+		else
+			val &= ~ICP_DDIA_HPD_OP_DRIVE_1;
+
+		I915_WRITE(SHOTPLUG_CTL_DDI, val);
+		break;
+	case ICL_GPIO_L_VDDEN_1:
+		val = I915_READ(ICP_PP_CONTROL(1));
+		if (value)
+			val |= PWR_STATE_TARGET;
+		else
+			val &= ~PWR_STATE_TARGET;
+		I915_WRITE(ICP_PP_CONTROL(1), val);
+		break;
+	case ICL_GPIO_L_BKLTEN_1:
+		val = I915_READ(ICP_PP_CONTROL(1));
+		if (value)
+			val |= BACKLIGHT_ENABLE;
+		else
+			val &= ~BACKLIGHT_ENABLE;
+		I915_WRITE(ICP_PP_CONTROL(1), val);
+		break;
+	default:
+		/* TODO: Add support for remaining GPIOs */
+		DRM_ERROR("Invalid GPIO no from VBT\n");
+		break;
+	}
 }
 
 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
-- 
2.11.0

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[PATCH v10 15/15] HACK: drm/i915/icl: Configure backlight functions for DSI

[Jani Nikula]

From: Madhav Chauhan <madhav.chauhan@intel.com>

Gen11 DSI doesn't use DCS commands based functionality
for enabling/disabling backlight but uses PWM based
functions similar to eDP.

Note by Jani: This should be decided by VBT, not hard coded. DCS
brightness control is still a thing.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_panel.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index e6cd7b55c018..b6df63aa11e3 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -1835,7 +1835,8 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel)
 	    intel_dp_aux_init_backlight_funcs(connector) == 0)
 		return;
 
-	if (connector->base.connector_type == DRM_MODE_CONNECTOR_DSI &&
+	if (IS_GEN9_LP(dev_priv) &&
+	    connector->base.connector_type == DRM_MODE_CONNECTOR_DSI &&
 	    intel_dsi_dcs_init_backlight_funcs(connector) == 0)
 		return;
 
-- 
2.11.0

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Re: [PATCH v10 00/15] drm/i915/icl: dsi enabling

[Jani Nikula]

On Fri, 02 Nov 2018, Jani Nikula <jani.nikula@intel.com> wrote:
> Next version of [1]. Sorry for the spam, needed to get the authorship
> straight. Fixed power domains and compute config hook initialization.

Also at icl-dsi-2018-11-02 branch of
https://cgit.freedesktop.org/~jani/drm/

BR,
Jani.

-- 
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Re: [PATCH v10 13/15] drm/i915/icl: add dummy DSI GPIO element execution function

[Madhav Chauhan]

On 11/2/2018 5:17 PM, Jani Nikula wrote:
> Add dummy debug logging GPIO element execution function for ICL.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Its kinda split of "drm/i915/icl: Add changes to program DSI panel GPIOs"
to pave out the way further. Looks good to me.

Reviewed-by: Madhav Chauhan <madhav.chauhan@intel.com>

Regards,
Madhav

> ---
>   drivers/gpu/drm/i915/intel_dsi_vbt.c | 10 +++++++++-
>   1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> index b41ca6436401..a1a8b3790e61 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> @@ -336,6 +336,12 @@ static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
>   	gpiod_set_value(gpio_desc, value);
>   }
>   
> +static void icl_exec_gpio(struct drm_i915_private *dev_priv,
> +			  u8 gpio_source, u8 gpio_index, bool value)
> +{
> +	DRM_DEBUG_KMS("Skipping ICL GPIO element execution\n");
> +}
> +
>   static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
>   {
>   	struct drm_device *dev = intel_dsi->base.base.dev;
> @@ -359,7 +365,9 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
>   	/* pull up/down */
>   	value = *data++ & 1;
>   
> -	if (IS_VALLEYVIEW(dev_priv))
> +	if (IS_ICELAKE(dev_priv))
> +		icl_exec_gpio(dev_priv, gpio_source, gpio_index, value);
> +	else if (IS_VALLEYVIEW(dev_priv))
>   		vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
>   	else if (IS_CHERRYVIEW(dev_priv))
>   		chv_exec_gpio(dev_priv, gpio_source, gpio_number, value);

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Re: [PATCH v10 06/15] drm/i915/icl: Add DSI encoder remaining functions

[Madhav Chauhan]

On 11/2/2018 5:17 PM, Jani Nikula wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> This patch implements compute config for Gen11 DSI encoder which is
> required at the time of modeset.
>
> v2 by Jani:
>   - drop the enable nop hook
>   - fixed_mode is always true
>   - HAS_GMCH_DISPLAY() is always false
>
> v3 by Jani:
>   - set encoder->compute_config dropped during rebase

Ok. :)

Regards,
Madhav

>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>   drivers/gpu/drm/i915/icl_dsi.c | 32 ++++++++++++++++++++++++++++++++
>   1 file changed, 32 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index 1881825432cb..8cdf736c2bbd 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -1068,6 +1068,37 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
>   	pipe_config->port_clock = pixel_clk;
>   }
>   
> +static bool gen11_dsi_compute_config(struct intel_encoder *encoder,
> +				     struct intel_crtc_state *pipe_config,
> +				     struct drm_connector_state *conn_state)
> +{
> +	struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
> +						   base);
> +	struct intel_connector *intel_connector = intel_dsi->attached_connector;
> +	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> +	const struct drm_display_mode *fixed_mode =
> +					intel_connector->panel.fixed_mode;
> +	struct drm_display_mode *adjusted_mode =
> +					&pipe_config->base.adjusted_mode;
> +
> +	intel_fixed_panel_mode(fixed_mode, adjusted_mode);
> +	intel_pch_panel_fitting(crtc, pipe_config, conn_state->scaling_mode);
> +
> +	adjusted_mode->flags = 0;
> +
> +	/* Dual link goes to trancoder DSI'0' */
> +	if (intel_dsi->ports == BIT(PORT_B))
> +		pipe_config->cpu_transcoder = TRANSCODER_DSI_1;
> +	else
> +		pipe_config->cpu_transcoder = TRANSCODER_DSI_0;
> +
> +	pipe_config->clock_set = true;
> +
> +	//TODO: Add check if DSI PLL calculation is done
> +
> +	return true;
> +}
> +
>   static u64 gen11_dsi_get_power_domains(struct intel_encoder *encoder,
>   				       struct intel_crtc_state *crtc_state)
>   {
> @@ -1235,6 +1266,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
>   	encoder->disable = gen11_dsi_disable;
>   	encoder->port = port;
>   	encoder->get_config = gen11_dsi_get_config;
> +	encoder->compute_config = gen11_dsi_compute_config;
>   	encoder->get_hw_state = gen11_dsi_get_hw_state;
>   	encoder->type = INTEL_OUTPUT_DSI;
>   	encoder->cloneable = 0;

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✗ Fi.CI.CHECKPATCH: warning for drm/i915/icl: dsi enabling (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915/icl: dsi enabling (rev5)
URL   : https://patchwork.freedesktop.org/series/51011/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
d23a54178f33 drm/i915/icl: Allocate DSI encoder/connector
-:137: CHECK:CAMELCASE: Avoid CamelCase: <SubPixelHorizontalRGB>
#137: FILE: drivers/gpu/drm/i915/icl_dsi.c:1043:
+	connector->display_info.subpixel_order = SubPixelHorizontalRGB;

total: 0 errors, 0 warnings, 1 checks, 145 lines checked
cfe6c143b720 drm/i915/icl: Fill DSI ports info
270b701c2f24 drm/i915/icl: Allocate DSI hosts and imlement host transfer
-:187: CHECK:LINE_SPACING: Please don't use multiple blank lines
#187: FILE: drivers/gpu/drm/i915/icl_dsi.c:1207:
 
+

total: 0 errors, 0 warnings, 1 checks, 171 lines checked
9e8bb6f3d10e drm/i915/icl: Add get config functionality for DSI
627892f10107 drm/i915/icl: Get HW state for DSI encoder
be3c778b70bc drm/i915/icl: Add DSI encoder remaining functions
ce70f993adae drm/i915/icl: Configure DSI Dual link mode
f90a102d651b drm/i915/icl: Consider DSI for getting transcoder state
86d27461e2a5 drm/i915/icl: Get pipe timings for DSI
89806b729adb drm/i915/icl: Define missing bitfield for shortplug reg
a4347dbf4292 drm/i915/icl: Define Panel power ctrl register
0c824e36c298 drm/i915/icl: Define display GPIO pins for DSI
bb2ac8890f29 drm/i915/icl: add dummy DSI GPIO element execution function
33b846632002 HACK: drm/i915/icl: Add changes to program DSI panel GPIOs
ce4a27ef96e5 HACK: drm/i915/icl: Configure backlight functions for DSI

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✗ Fi.CI.SPARSE: warning for drm/i915/icl: dsi enabling (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915/icl: dsi enabling (rev5)
URL   : https://patchwork.freedesktop.org/series/51011/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/icl: Allocate DSI encoder/connector
Okay!

Commit: drm/i915/icl: Fill DSI ports info
Okay!

Commit: drm/i915/icl: Allocate DSI hosts and imlement host transfer
+drivers/gpu/drm/i915/icl_dsi.c:129:33: warning: expression using sizeof(void)

Commit: drm/i915/icl: Add get config functionality for DSI
Okay!

Commit: drm/i915/icl: Get HW state for DSI encoder
Okay!

Commit: drm/i915/icl: Add DSI encoder remaining functions
Okay!

Commit: drm/i915/icl: Configure DSI Dual link mode
Okay!

Commit: drm/i915/icl: Consider DSI for getting transcoder state
Okay!

Commit: drm/i915/icl: Get pipe timings for DSI
Okay!

Commit: drm/i915/icl: Define missing bitfield for shortplug reg
Okay!

Commit: drm/i915/icl: Define Panel power ctrl register
Okay!

Commit: drm/i915/icl: Define display GPIO pins for DSI
Okay!

Commit: drm/i915/icl: add dummy DSI GPIO element execution function
Okay!

Commit: HACK: drm/i915/icl: Add changes to program DSI panel GPIOs
Okay!

Commit: HACK: drm/i915/icl: Configure backlight functions for DSI
Okay!

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✗ Fi.CI.BAT: failure for drm/i915/icl: dsi enabling (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915/icl: dsi enabling (rev5)
URL   : https://patchwork.freedesktop.org/series/51011/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_5078 -> Patchwork_10708 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_10708 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10708, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/51011/revisions/5/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10708:

  === IGT changes ===

    ==== Possible regressions ====

    igt@kms_flip@basic-flip-vs-wf_vblank:
      fi-icl-u:           PASS -> DMESG-WARN +17

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
      fi-icl-u2:          PASS -> DMESG-WARN +17

    
    ==== Warnings ====

    igt@drv_selftest@live_guc:
      fi-skl-iommu:       SKIP -> PASS +1

    
== Known issues ==

  Here are the changes found in Patchwork_10708 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_module_reload@basic-reload:
      fi-blb-e6850:       NOTRUN -> INCOMPLETE (fdo#107718)

    igt@drv_selftest@live_hangcheck:
      fi-skl-guc:         PASS -> DMESG-FAIL (fdo#108593)

    igt@kms_frontbuffer_tracking@basic:
      fi-byt-clapper:     PASS -> FAIL (fdo#103167)

    igt@kms_pipe_crc_basic@read-crc-pipe-b:
      fi-byt-clapper:     PASS -> FAIL (fdo#107362)

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
      fi-byt-clapper:     PASS -> FAIL (fdo#107362, fdo#103191) +2

    
    ==== Possible fixes ====

    igt@drv_selftest@live_hangcheck:
      fi-skl-iommu:       INCOMPLETE (fdo#108602) -> PASS

    igt@gem_exec_suspend@basic-s3:
      fi-blb-e6850:       INCOMPLETE (fdo#107718) -> PASS

    igt@kms_flip@basic-flip-vs-modeset:
      fi-skl-6700hq:      DMESG-WARN (fdo#105998) -> PASS +1

    igt@kms_frontbuffer_tracking@basic:
      fi-hsw-peppy:       DMESG-WARN (fdo#102614) -> PASS

    igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
      fi-byt-clapper:     FAIL (fdo#107362) -> PASS

    
    ==== Warnings ====

    igt@drv_selftest@live_contexts:
      fi-icl-u2:          DMESG-FAIL (fdo#108569) -> INCOMPLETE (fdo#108315)

    
  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
  fdo#108315 https://bugs.freedesktop.org/show_bug.cgi?id=108315
  fdo#108569 https://bugs.freedesktop.org/show_bug.cgi?id=108569
  fdo#108593 https://bugs.freedesktop.org/show_bug.cgi?id=108593
  fdo#108602 https://bugs.freedesktop.org/show_bug.cgi?id=108602


== Participating hosts (44 -> 42) ==

  Additional (1): fi-pnv-d510 
  Missing    (3): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 


== Build changes ==

    * Linux: CI_DRM_5078 -> Patchwork_10708

  CI_DRM_5078: 3309ab4d8894496bb432017ee7cc765edb48a5f3 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4704: ace031dcb1e8bf2b32b4b0d54a55eb30e8f41d6f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10708: ce4a27ef96e5eda21d60c951ed097085dda7f456 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

ce4a27ef96e5 HACK: drm/i915/icl: Configure backlight functions for DSI
33b846632002 HACK: drm/i915/icl: Add changes to program DSI panel GPIOs
bb2ac8890f29 drm/i915/icl: add dummy DSI GPIO element execution function
0c824e36c298 drm/i915/icl: Define display GPIO pins for DSI
a4347dbf4292 drm/i915/icl: Define Panel power ctrl register
89806b729adb drm/i915/icl: Define missing bitfield for shortplug reg
86d27461e2a5 drm/i915/icl: Get pipe timings for DSI
f90a102d651b drm/i915/icl: Consider DSI for getting transcoder state
ce70f993adae drm/i915/icl: Configure DSI Dual link mode
be3c778b70bc drm/i915/icl: Add DSI encoder remaining functions
627892f10107 drm/i915/icl: Get HW state for DSI encoder
9e8bb6f3d10e drm/i915/icl: Add get config functionality for DSI
270b701c2f24 drm/i915/icl: Allocate DSI hosts and imlement host transfer
cfe6c143b720 drm/i915/icl: Fill DSI ports info
d23a54178f33 drm/i915/icl: Allocate DSI encoder/connector

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10708/issues.html
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Re: [PATCH v10 13/15] drm/i915/icl: add dummy DSI GPIO element execution function

[Jani Nikula]

On Fri, 02 Nov 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> On 11/2/2018 5:17 PM, Jani Nikula wrote:
>> Add dummy debug logging GPIO element execution function for ICL.
>>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> Its kinda split of "drm/i915/icl: Add changes to program DSI panel GPIOs"
> to pave out the way further. Looks good to me.

Yeah since there was controversy with that change, add this one to not
take the other platform code paths for ICL.

> Reviewed-by: Madhav Chauhan <madhav.chauhan@intel.com>

Thanks,
Jani.

>
> Regards,
> Madhav
>
>> ---
>>   drivers/gpu/drm/i915/intel_dsi_vbt.c | 10 +++++++++-
>>   1 file changed, 9 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> index b41ca6436401..a1a8b3790e61 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> @@ -336,6 +336,12 @@ static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
>>   	gpiod_set_value(gpio_desc, value);
>>   }
>>   
>> +static void icl_exec_gpio(struct drm_i915_private *dev_priv,
>> +			  u8 gpio_source, u8 gpio_index, bool value)
>> +{
>> +	DRM_DEBUG_KMS("Skipping ICL GPIO element execution\n");
>> +}
>> +
>>   static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
>>   {
>>   	struct drm_device *dev = intel_dsi->base.base.dev;
>> @@ -359,7 +365,9 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
>>   	/* pull up/down */
>>   	value = *data++ & 1;
>>   
>> -	if (IS_VALLEYVIEW(dev_priv))
>> +	if (IS_ICELAKE(dev_priv))
>> +		icl_exec_gpio(dev_priv, gpio_source, gpio_index, value);
>> +	else if (IS_VALLEYVIEW(dev_priv))
>>   		vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
>>   	else if (IS_CHERRYVIEW(dev_priv))
>>   		chv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
>

-- 
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Re: [PATCH v10 05/15] drm/i915/icl: Get HW state for DSI encoder

[Madhav Chauhan]

On 11/2/2018 5:17 PM, Jani Nikula wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> This patch read out the current hw state for DSI and
> return true if encoder is active.
>
> v2 by Jani:
>   - Squash connector get hw state hook here
>   - Squash encode get hw state fix here
>
> v3 by Jani:
>   - Add encoder->get_power_domains() (Imre)
>
> v4 by Jani:
>   - Make encoder->get_power_domains() sensible... (Imre)

Changes looks fine to me.

Regards,
Madhav

>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>   drivers/gpu/drm/i915/icl_dsi.c | 57 ++++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 57 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index b47e837f4493..1881825432cb 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -1068,6 +1068,60 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
>   	pipe_config->port_clock = pixel_clk;
>   }
>   
> +static u64 gen11_dsi_get_power_domains(struct intel_encoder *encoder,
> +				       struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	u64 domains = 0;
> +	enum port port;
> +
> +	for_each_dsi_port(port, intel_dsi->ports)
> +		domains |= (port == PORT_A ? POWER_DOMAIN_PORT_DDI_A_IO :
> +			    POWER_DOMAIN_PORT_DDI_B_IO);
> +
> +	return domains;
> +}
> +
> +static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
> +				   enum pipe *pipe)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	u32 tmp;
> +	enum port port;
> +	enum transcoder dsi_trans;
> +	bool ret = false;
> +
> +	if (!intel_display_power_get_if_enabled(dev_priv,
> +						encoder->power_domain))
> +		return false;
> +
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		dsi_trans = dsi_port_to_transcoder(port);
> +		tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
> +		switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
> +		case TRANS_DDI_EDP_INPUT_A_ON:
> +			*pipe = PIPE_A;
> +			break;
> +		case TRANS_DDI_EDP_INPUT_B_ONOFF:
> +			*pipe = PIPE_B;
> +			break;
> +		case TRANS_DDI_EDP_INPUT_C_ONOFF:
> +			*pipe = PIPE_C;
> +			break;
> +		default:
> +			DRM_ERROR("Invalid PIPE input\n");
> +			goto out;
> +		}
> +
> +		tmp = I915_READ(PIPECONF(dsi_trans));
> +		ret = tmp & PIPECONF_ENABLE;
> +	}
> +out:
> +	intel_display_power_put(dev_priv, encoder->power_domain);
> +	return ret;
> +}
> +
>   static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
>   {
>   	intel_encoder_destroy(encoder);
> @@ -1181,10 +1235,12 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
>   	encoder->disable = gen11_dsi_disable;
>   	encoder->port = port;
>   	encoder->get_config = gen11_dsi_get_config;
> +	encoder->get_hw_state = gen11_dsi_get_hw_state;
>   	encoder->type = INTEL_OUTPUT_DSI;
>   	encoder->cloneable = 0;
>   	encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
>   	encoder->power_domain = POWER_DOMAIN_PORT_DSI;
> +	encoder->get_power_domains = gen11_dsi_get_power_domains;
>   
>   	/* register DSI connector with DRM subsystem */
>   	drm_connector_init(dev, connector, &gen11_dsi_connector_funcs,
> @@ -1193,6 +1249,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
>   	connector->display_info.subpixel_order = SubPixelHorizontalRGB;
>   	connector->interlace_allowed = false;
>   	connector->doublescan_allowed = false;
> +	intel_connector->get_hw_state = intel_connector_get_hw_state;
>   
>   	/* attach connector to encoder */
>   	intel_connector_attach_encoder(intel_connector, encoder);

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Re: [PATCH v10 00/15] drm/i915/icl: dsi enabling

[Jani Nikula]

On Fri, 02 Nov 2018, Jani Nikula <jani.nikula@intel.com> wrote:
> Next version of [1]. Sorry for the spam, needed to get the authorship
> straight. Fixed power domains and compute config hook initialization.

It looks like DDI intel_ddi_get_hw_state() returns true for ICL DSI as
well. I'm not sure how this wasn't a problem before, but if I'm not
mistaken it is now.

At least that's my only explanation to intel_ddi_get_config() hitting
WARN_ON(transcoder_is_dsi(cpu_transcoder)).

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Graphics Center
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✗ Fi.CI.BAT: failure for drm/i915/icl: dsi enabling (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915/icl: dsi enabling (rev5)
URL   : https://patchwork.freedesktop.org/series/51011/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_5078 -> Patchwork_10709 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_10709 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10709, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/51011/revisions/5/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10709:

  === IGT changes ===

    ==== Possible regressions ====

    igt@kms_flip@basic-flip-vs-wf_vblank:
      fi-icl-u:           PASS -> DMESG-WARN +17

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
      fi-icl-u2:          PASS -> DMESG-WARN +17

    
== Known issues ==

  Here are the changes found in Patchwork_10709 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
      fi-byt-clapper:     PASS -> FAIL (fdo#103191, fdo#107362) +1
      fi-skl-6700k2:      PASS -> FAIL (fdo#103191, fdo#107362)

    
    ==== Possible fixes ====

    igt@gem_exec_suspend@basic-s3:
      fi-blb-e6850:       INCOMPLETE (fdo#107718) -> PASS

    igt@kms_flip@basic-flip-vs-modeset:
      fi-skl-6700hq:      DMESG-WARN (fdo#105998) -> PASS +1

    igt@kms_frontbuffer_tracking@basic:
      fi-hsw-peppy:       DMESG-WARN (fdo#102614) -> PASS

    
  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718


== Participating hosts (44 -> 41) ==

  Additional (2): fi-bwr-2160 fi-pnv-d510 
  Missing    (5): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-skl-iommu 


== Build changes ==

    * Linux: CI_DRM_5078 -> Patchwork_10709

  CI_DRM_5078: 3309ab4d8894496bb432017ee7cc765edb48a5f3 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4704: ace031dcb1e8bf2b32b4b0d54a55eb30e8f41d6f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10709: 5564f1b6f670d995837e3f0814e4ae2cf3948f3d @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

5564f1b6f670 HACK: drm/i915/icl: Configure backlight functions for DSI
d2ce8fc9b5f1 HACK: drm/i915/icl: Add changes to program DSI panel GPIOs
51069758915e drm/i915/icl: add dummy DSI GPIO element execution function
f2281281387b drm/i915/icl: Define display GPIO pins for DSI
1403aedc31f3 drm/i915/icl: Define Panel power ctrl register
7c151f89d317 drm/i915/icl: Define missing bitfield for shortplug reg
849a5d4f9c42 drm/i915/icl: Get pipe timings for DSI
d5148017f3e8 drm/i915/icl: Consider DSI for getting transcoder state
24f9b5fd0ed4 drm/i915/icl: Configure DSI Dual link mode
4a7595f75490 drm/i915/icl: Add DSI encoder remaining functions
684e685f2be4 drm/i915/icl: Get HW state for DSI encoder
99f39d537adb drm/i915/icl: Add get config functionality for DSI
8f61d29c75a6 drm/i915/icl: Allocate DSI hosts and imlement host transfer
f1b03756cb68 drm/i915/icl: Fill DSI ports info
c4edb3f5081a drm/i915/icl: Allocate DSI encoder/connector

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10709/issues.html
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Re: [PATCH v10 00/15] drm/i915/icl: dsi enabling

[Madhav Chauhan]

On 11/2/2018 7:15 PM, Jani Nikula wrote:
> On Fri, 02 Nov 2018, Jani Nikula <jani.nikula@intel.com> wrote:
>> Next version of [1]. Sorry for the spam, needed to get the authorship
>> straight. Fixed power domains and compute config hook initialization.
> It looks like DDI intel_ddi_get_hw_state() returns true for ICL DSI as
> well. I'm not sure how this wasn't a problem before, but if I'm not
> mistaken it is now.
>
> At least that's my only explanation to intel_ddi_get_config() hitting
> WARN_ON(transcoder_is_dsi(cpu_transcoder)).

I didn't observe that while testing. Where can we access the complete log??

Regards,
Madhav

>
> BR,
> Jani.
>
>

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Re: [PATCH v10 00/15] drm/i915/icl: dsi enabling

[Jani Nikula]

On Sat, 03 Nov 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> On 11/2/2018 7:15 PM, Jani Nikula wrote:
>> On Fri, 02 Nov 2018, Jani Nikula <jani.nikula@intel.com> wrote:
>>> Next version of [1]. Sorry for the spam, needed to get the authorship
>>> straight. Fixed power domains and compute config hook initialization.
>> It looks like DDI intel_ddi_get_hw_state() returns true for ICL DSI as
>> well. I'm not sure how this wasn't a problem before, but if I'm not
>> mistaken it is now.
>>
>> At least that's my only explanation to intel_ddi_get_config() hitting
>> WARN_ON(transcoder_is_dsi(cpu_transcoder)).
>
> I didn't observe that while testing. Where can we access the complete log??

Vandita reported that.

BR,
Jani.

>
> Regards,
> Madhav
>
>>
>> BR,
>> Jani.
>>
>>
>

-- 
Jani Nikula, Intel Open Source Graphics Center
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Re: [PATCH v10 00/15] drm/i915/icl: dsi enabling

[Kulkarni, Vandita]

> -----Original Message-----
> From: Nikula, Jani
> Sent: Sunday, November 4, 2018 12:46 AM
> To: Chauhan, Madhav <madhav.chauhan@intel.com>; intel-
> gfx@lists.freedesktop.org; Kulkarni, Vandita <vandita.kulkarni@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Subject: Re: [Intel-gfx] [PATCH v10 00/15] drm/i915/icl: dsi enabling
> 
> On Sat, 03 Nov 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> > On 11/2/2018 7:15 PM, Jani Nikula wrote:
> >> On Fri, 02 Nov 2018, Jani Nikula <jani.nikula@intel.com> wrote:
> >>> Next version of [1]. Sorry for the spam, needed to get the
> >>> authorship straight. Fixed power domains and compute config hook
> initialization.
> >> It looks like DDI intel_ddi_get_hw_state() returns true for ICL DSI
Yes, it does, checked on Jani's latest branch.
> >> as well. I'm not sure how this wasn't a problem before, but if I'm
> >> not mistaken it is now.
> >>
> >> At least that's my only explanation to intel_ddi_get_config() hitting
> >> WARN_ON(transcoder_is_dsi(cpu_transcoder)).
> >
> > I didn't observe that while testing. Where can we access the complete log??
Sent.
-Vandita
> 
> Vandita reported that.
> 
> BR,
> Jani.
> 
> >
> > Regards,
> > Madhav
> >
> >>
> >> BR,
> >> Jani.
> >>
> >>
> >
> 
> --
> Jani Nikula, Intel Open Source Graphics Center
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Re: [PATCH v10 00/15] drm/i915/icl: dsi enabling

[Chauhan, Madhav]

> -----Original Message-----
> From: Kulkarni, Vandita
> Sent: Monday, November 5, 2018 11:17 AM
> To: Nikula, Jani <jani.nikula@intel.com>; Chauhan, Madhav
> <madhav.chauhan@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Subject: RE: [Intel-gfx] [PATCH v10 00/15] drm/i915/icl: dsi enabling
> 
> 
> 
> > -----Original Message-----
> > From: Nikula, Jani
> > Sent: Sunday, November 4, 2018 12:46 AM
> > To: Chauhan, Madhav <madhav.chauhan@intel.com>; intel-
> > gfx@lists.freedesktop.org; Kulkarni, Vandita
> > <vandita.kulkarni@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Subject: Re: [Intel-gfx] [PATCH v10 00/15] drm/i915/icl: dsi enabling
> >
> > On Sat, 03 Nov 2018, Madhav Chauhan <madhav.chauhan@intel.com>
> wrote:
> > > On 11/2/2018 7:15 PM, Jani Nikula wrote:
> > >> On Fri, 02 Nov 2018, Jani Nikula <jani.nikula@intel.com> wrote:
> > >>> Next version of [1]. Sorry for the spam, needed to get the
> > >>> authorship straight. Fixed power domains and compute config hook
> > initialization.
> > >> It looks like DDI intel_ddi_get_hw_state() returns true for ICL DSI
> Yes, it does, checked on Jani's latest branch.
> > >> as well. I'm not sure how this wasn't a problem before, but if I'm
> > >> not mistaken it is now.
> > >>
> > >> At least that's my only explanation to intel_ddi_get_config()
> > >> hitting WARN_ON(transcoder_is_dsi(cpu_transcoder)).
> > >
> > > I didn't observe that while testing. Where can we access the complete
> log??
> Sent.

There were some patches from Clock enabling and one hack wrt to VBT parsing.
Vandita will be trying with those.

Regards,
Madhav

> -Vandita
> >
> > Vandita reported that.
> >
> > BR,
> > Jani.
> >
> > >
> > > Regards,
> > > Madhav
> > >
> > >>
> > >> BR,
> > >> Jani.
> > >>
> > >>
> > >
> >
> > --
> > Jani Nikula, Intel Open Source Graphics Center
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Re: [PATCH v10 00/15] drm/i915/icl: dsi enabling

[Kulkarni, Vandita]

> -----Original Message-----
> From: Chauhan, Madhav
> Sent: Monday, November 5, 2018 3:03 PM
> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; Nikula, Jani
> <jani.nikula@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Subject: RE: [Intel-gfx] [PATCH v10 00/15] drm/i915/icl: dsi enabling
> 
> > -----Original Message-----
> > From: Kulkarni, Vandita
> > Sent: Monday, November 5, 2018 11:17 AM
> > To: Nikula, Jani <jani.nikula@intel.com>; Chauhan, Madhav
> > <madhav.chauhan@intel.com>; intel-gfx@lists.freedesktop.org
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Subject: RE: [Intel-gfx] [PATCH v10 00/15] drm/i915/icl: dsi enabling
> >
> >
> >
> > > -----Original Message-----
> > > From: Nikula, Jani
> > > Sent: Sunday, November 4, 2018 12:46 AM
> > > To: Chauhan, Madhav <madhav.chauhan@intel.com>; intel-
> > > gfx@lists.freedesktop.org; Kulkarni, Vandita
> > > <vandita.kulkarni@intel.com>
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Subject: Re: [Intel-gfx] [PATCH v10 00/15] drm/i915/icl: dsi
> > > enabling
> > >
> > > On Sat, 03 Nov 2018, Madhav Chauhan <madhav.chauhan@intel.com>
> > wrote:
> > > > On 11/2/2018 7:15 PM, Jani Nikula wrote:
> > > >> On Fri, 02 Nov 2018, Jani Nikula <jani.nikula@intel.com> wrote:
> > > >>> Next version of [1]. Sorry for the spam, needed to get the
> > > >>> authorship straight. Fixed power domains and compute config hook
> > > initialization.
> > > >> It looks like DDI intel_ddi_get_hw_state() returns true for ICL
> > > >> DSI
> > Yes, it does, checked on Jani's latest branch.
> > > >> as well. I'm not sure how this wasn't a problem before, but if
> > > >> I'm not mistaken it is now.
> > > >>
> > > >> At least that's my only explanation to intel_ddi_get_config()
> > > >> hitting WARN_ON(transcoder_is_dsi(cpu_transcoder)).
> > > >
> > > > I didn't observe that while testing. Where can we access the
> > > > complete
> > log??
> > Sent.
> 
> There were some patches from Clock enabling and one hack wrt to VBT parsing.
> Vandita will be trying with those.
Thanks Madhav, but looks like just that is not enough. Will keep you posted.

Regards,
Vandita
> 
> Regards,
> Madhav
> 
> > -Vandita
> > >
> > > Vandita reported that.
> > >
> > > BR,
> > > Jani.
> > >
> > > >
> > > > Regards,
> > > > Madhav
> > > >
> > > >>
> > > >> BR,
> > > >> Jani.
> > > >>
> > > >>
> > > >
> > >
> > > --
> > > Jani Nikula, Intel Open Source Graphics Center
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Re: [PATCH v10 00/15] drm/i915/icl: dsi enabling

[Chauhan, Madhav]

> -----Original Message-----
> From: Kulkarni, Vandita
> Sent: Monday, November 5, 2018 3:26 PM
> To: Chauhan, Madhav <madhav.chauhan@intel.com>; Nikula, Jani
> <jani.nikula@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Subject: RE: [Intel-gfx] [PATCH v10 00/15] drm/i915/icl: dsi enabling
> 
> 
> 
> > -----Original Message-----
> > From: Chauhan, Madhav
> > Sent: Monday, November 5, 2018 3:03 PM
> > To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; Nikula, Jani
> > <jani.nikula@intel.com>; intel-gfx@lists.freedesktop.org
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Subject: RE: [Intel-gfx] [PATCH v10 00/15] drm/i915/icl: dsi enabling
> >
> > > -----Original Message-----
> > > From: Kulkarni, Vandita
> > > Sent: Monday, November 5, 2018 11:17 AM
> > > To: Nikula, Jani <jani.nikula@intel.com>; Chauhan, Madhav
> > > <madhav.chauhan@intel.com>; intel-gfx@lists.freedesktop.org
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Subject: RE: [Intel-gfx] [PATCH v10 00/15] drm/i915/icl: dsi
> > > enabling
> > >
> > >
> > >
> > > > -----Original Message-----
> > > > From: Nikula, Jani
> > > > Sent: Sunday, November 4, 2018 12:46 AM
> > > > To: Chauhan, Madhav <madhav.chauhan@intel.com>; intel-
> > > > gfx@lists.freedesktop.org; Kulkarni, Vandita
> > > > <vandita.kulkarni@intel.com>
> > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > Subject: Re: [Intel-gfx] [PATCH v10 00/15] drm/i915/icl: dsi
> > > > enabling
> > > >
> > > > On Sat, 03 Nov 2018, Madhav Chauhan <madhav.chauhan@intel.com>
> > > wrote:
> > > > > On 11/2/2018 7:15 PM, Jani Nikula wrote:
> > > > >> On Fri, 02 Nov 2018, Jani Nikula <jani.nikula@intel.com> wrote:
> > > > >>> Next version of [1]. Sorry for the spam, needed to get the
> > > > >>> authorship straight. Fixed power domains and compute config
> > > > >>> hook
> > > > initialization.
> > > > >> It looks like DDI intel_ddi_get_hw_state() returns true for ICL
> > > > >> DSI
> > > Yes, it does, checked on Jani's latest branch.
> > > > >> as well. I'm not sure how this wasn't a problem before, but if
> > > > >> I'm not mistaken it is now.
> > > > >>
> > > > >> At least that's my only explanation to intel_ddi_get_config()
> > > > >> hitting (transcoder_is_dsi(cpu_transcoder)).
> > > > >
> > > > > I didn't observe that while testing. Where can we access the
> > > > > complete
> > > log??
> > > Sent.
> >
> > There were some patches from Clock enabling and one hack wrt to VBT
> parsing.
> > Vandita will be trying with those.
> Thanks Madhav, but looks like just that is not enough. Will keep you posted.

Ok. So you included VBT Patch + PLL Enabling + Clock gate/ungated patches.
Whats the issue now?? Still WARN_ON??

Regards,
Madhav

> 
> Regards,
> Vandita
> >
> > Regards,
> > Madhav
> >
> > > -Vandita
> > > >
> > > > Vandita reported that.
> > > >
> > > > BR,
> > > > Jani.
> > > >
> > > > >
> > > > > Regards,
> > > > > Madhav
> > > > >
> > > > >>
> > > > >> BR,
> > > > >> Jani.
> > > > >>
> > > > >>
> > > > >
> > > >
> > > > --
> > > > Jani Nikula, Intel Open Source Graphics Center
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Re: [PATCH v10 00/15] drm/i915/icl: dsi enabling

[Kulkarni, Vandita]

> -----Original Message-----
> From: Chauhan, Madhav
> Sent: Monday, November 5, 2018 3:46 PM
> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; Nikula, Jani
> <jani.nikula@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Subject: RE: [Intel-gfx] [PATCH v10 00/15] drm/i915/icl: dsi enabling
> 
> > -----Original Message-----
> > From: Kulkarni, Vandita
> > Sent: Monday, November 5, 2018 3:26 PM
> > To: Chauhan, Madhav <madhav.chauhan@intel.com>; Nikula, Jani
> > <jani.nikula@intel.com>; intel-gfx@lists.freedesktop.org
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Subject: RE: [Intel-gfx] [PATCH v10 00/15] drm/i915/icl: dsi enabling
> >
> >
> >
> > > -----Original Message-----
> > > From: Chauhan, Madhav
> > > Sent: Monday, November 5, 2018 3:03 PM
> > > To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; Nikula, Jani
> > > <jani.nikula@intel.com>; intel-gfx@lists.freedesktop.org
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Subject: RE: [Intel-gfx] [PATCH v10 00/15] drm/i915/icl: dsi
> > > enabling
> > >
> > > > -----Original Message-----
> > > > From: Kulkarni, Vandita
> > > > Sent: Monday, November 5, 2018 11:17 AM
> > > > To: Nikula, Jani <jani.nikula@intel.com>; Chauhan, Madhav
> > > > <madhav.chauhan@intel.com>; intel-gfx@lists.freedesktop.org
> > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > Subject: RE: [Intel-gfx] [PATCH v10 00/15] drm/i915/icl: dsi
> > > > enabling
> > > >
> > > >
> > > >
> > > > > -----Original Message-----
> > > > > From: Nikula, Jani
> > > > > Sent: Sunday, November 4, 2018 12:46 AM
> > > > > To: Chauhan, Madhav <madhav.chauhan@intel.com>; intel-
> > > > > gfx@lists.freedesktop.org; Kulkarni, Vandita
> > > > > <vandita.kulkarni@intel.com>
> > > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > > Subject: Re: [Intel-gfx] [PATCH v10 00/15] drm/i915/icl: dsi
> > > > > enabling
> > > > >
> > > > > On Sat, 03 Nov 2018, Madhav Chauhan <madhav.chauhan@intel.com>
> > > > wrote:
> > > > > > On 11/2/2018 7:15 PM, Jani Nikula wrote:
> > > > > >> On Fri, 02 Nov 2018, Jani Nikula <jani.nikula@intel.com> wrote:
> > > > > >>> Next version of [1]. Sorry for the spam, needed to get the
> > > > > >>> authorship straight. Fixed power domains and compute config
> > > > > >>> hook
> > > > > initialization.
> > > > > >> It looks like DDI intel_ddi_get_hw_state() returns true for
> > > > > >> ICL DSI
> > > > Yes, it does, checked on Jani's latest branch.
> > > > > >> as well. I'm not sure how this wasn't a problem before, but
> > > > > >> if I'm not mistaken it is now.
> > > > > >>
> > > > > >> At least that's my only explanation to intel_ddi_get_config()
> > > > > >> hitting (transcoder_is_dsi(cpu_transcoder)).
> > > > > >
> > > > > > I didn't observe that while testing. Where can we access the
> > > > > > complete
> > > > log??
> > > > Sent.
> > >
> > > There were some patches from Clock enabling and one hack wrt to VBT
> > parsing.
> > > Vandita will be trying with those.
> > Thanks Madhav, but looks like just that is not enough. Will keep you posted.

> Ok. So you included VBT Patch + PLL Enabling + Clock gate/ungated patches.
Yes.

> Whats the issue now?? Still WARN_ON??
Looks like the VBT hack fixes the WARN_ON and the ddi calls.
Thanks for the help.

Unfortunately, it doesn't boot, even with the above recipe. There is a hard hang.

Regards,
Vandita
> 
> Regards,
> Madhav
> 
> >
> > Regards,
> > Vandita
> > >
> > > Regards,
> > > Madhav
> > >
> > > > -Vandita
> > > > >
> > > > > Vandita reported that.
> > > > >
> > > > > BR,
> > > > > Jani.
> > > > >
> > > > > >
> > > > > > Regards,
> > > > > > Madhav
> > > > > >
> > > > > >>
> > > > > >> BR,
> > > > > >> Jani.
> > > > > >>
> > > > > >>
> > > > > >
> > > > >
> > > > > --
> > > > > Jani Nikula, Intel Open Source Graphics Center
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Re: [PATCH v10 05/15] drm/i915/icl: Get HW state for DSI encoder

[Lisovskiy, Stanislav]

On Fri, 2018-11-02 at 13:47 +0200, Jani Nikula wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
> 
> This patch read out the current hw state for DSI and
> return true if encoder is active.
> 
> v2 by Jani:
>  - Squash connector get hw state hook here
>  - Squash encode get hw state fix here
> 
> v3 by Jani:
>  - Add encoder->get_power_domains() (Imre)
> 
> v4 by Jani:
>  - Make encoder->get_power_domains() sensible... (Imre)
> 
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/icl_dsi.c | 57
> ++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 57 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c
> b/drivers/gpu/drm/i915/icl_dsi.c
> index b47e837f4493..1881825432cb 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -1068,6 +1068,60 @@ static void gen11_dsi_get_config(struct
> intel_encoder *encoder,
>  	pipe_config->port_clock = pixel_clk;
>  }
>  
> +static u64 gen11_dsi_get_power_domains(struct intel_encoder
> *encoder,
> +				       struct intel_crtc_state
> *crtc_state)
> +{
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder-
> >base);
> +	u64 domains = 0;
> +	enum port port;
> +
> +	for_each_dsi_port(port, intel_dsi->ports)
> +		domains |= (port == PORT_A ?
> POWER_DOMAIN_PORT_DDI_A_IO :
> +			    POWER_DOMAIN_PORT_DDI_B_IO);

After investigating this with Imre, we found that this should be:

for_each_dsi_port(port, intel_dsi->ports)
	domains |= (port == PORT_A ? BIT(POWER_DOMAIN_PORT_DDI_A_IO) :
		BIT(POWER_DOMAIN_PORT_DDI_B_IO));

As POWER_DOMAIN_PORT_DDI_A_IO and POWER_DOMAIN_PORT_DDI_B_IO are actual
enum values, not bit positions. Otherwise we are getting garbage in
returned domains and dmesg warnings regarding power wells.
With those fixed, at least power well dmesg warnings are gone.

> +
> +	return domains;
> +}
> +
> +static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
> +				   enum pipe *pipe)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder-
> >base.dev);
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder-
> >base);
> +	u32 tmp;
> +	enum port port;
> +	enum transcoder dsi_trans;
> +	bool ret = false;
> +
> +	if (!intel_display_power_get_if_enabled(dev_priv,
> +						encoder-
> >power_domain))
> +		return false;
> +
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		dsi_trans = dsi_port_to_transcoder(port);
> +		tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
> +		switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
> +		case TRANS_DDI_EDP_INPUT_A_ON:
> +			*pipe = PIPE_A;
> +			break;
> +		case TRANS_DDI_EDP_INPUT_B_ONOFF:
> +			*pipe = PIPE_B;
> +			break;
> +		case TRANS_DDI_EDP_INPUT_C_ONOFF:
> +			*pipe = PIPE_C;
> +			break;
> +		default:
> +			DRM_ERROR("Invalid PIPE input\n");
> +			goto out;
> +		}
> +
> +		tmp = I915_READ(PIPECONF(dsi_trans));
> +		ret = tmp & PIPECONF_ENABLE;
> +	}
> +out:
> +	intel_display_power_put(dev_priv, encoder->power_domain);
> +	return ret;
> +}
> +
>  static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
>  {
>  	intel_encoder_destroy(encoder);
> @@ -1181,10 +1235,12 @@ void icl_dsi_init(struct drm_i915_private
> *dev_priv)
>  	encoder->disable = gen11_dsi_disable;
>  	encoder->port = port;
>  	encoder->get_config = gen11_dsi_get_config;
> +	encoder->get_hw_state = gen11_dsi_get_hw_state;
>  	encoder->type = INTEL_OUTPUT_DSI;
>  	encoder->cloneable = 0;
>  	encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) |
> BIT(PIPE_C);
>  	encoder->power_domain = POWER_DOMAIN_PORT_DSI;
> +	encoder->get_power_domains = gen11_dsi_get_power_domains;
>  
>  	/* register DSI connector with DRM subsystem */
>  	drm_connector_init(dev, connector,
> &gen11_dsi_connector_funcs,
> @@ -1193,6 +1249,7 @@ void icl_dsi_init(struct drm_i915_private
> *dev_priv)
>  	connector->display_info.subpixel_order =
> SubPixelHorizontalRGB;
>  	connector->interlace_allowed = false;
>  	connector->doublescan_allowed = false;
> +	intel_connector->get_hw_state =
> intel_connector_get_hw_state;
>  
>  	/* attach connector to encoder */
>  	intel_connector_attach_encoder(intel_connector, encoder);
-- 
Best Regards,

Lisovskiy Stanislav
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Re: [PATCH v10 00/15] drm/i915/icl: dsi enabling

[Madhav Chauhan]

On 11/2/2018 5:17 PM, Jani Nikula wrote:
> Next version of [1]. Sorry for the spam, needed to get the authorship
> straight. Fixed power domains and compute config hook initialization.

Overall, with this series ICL DSI dual link video mode feature looks
complete to me. Thanks!!

Regards,
Madhav

>
> BR,
> Jani.
>
> [1] https://patchwork.freedesktop.org/series/51011/
>
>
> Jani Nikula (1):
>    drm/i915/icl: add dummy DSI GPIO element execution function
>
> Madhav Chauhan (14):
>    drm/i915/icl: Allocate DSI encoder/connector
>    drm/i915/icl: Fill DSI ports info
>    drm/i915/icl: Allocate DSI hosts and imlement host transfer
>    drm/i915/icl: Add get config functionality for DSI
>    drm/i915/icl: Get HW state for DSI encoder
>    drm/i915/icl: Add DSI encoder remaining functions
>    drm/i915/icl: Configure DSI Dual link mode
>    drm/i915/icl: Consider DSI for getting transcoder state
>    drm/i915/icl: Get pipe timings for DSI
>    drm/i915/icl: Define missing bitfield for shortplug reg
>    drm/i915/icl: Define Panel power ctrl register
>    drm/i915/icl: Define display GPIO pins for DSI
>    HACK: drm/i915/icl: Add changes to program DSI panel GPIOs
>    HACK: drm/i915/icl: Configure backlight functions for DSI
>
>   drivers/gpu/drm/i915/i915_reg.h      |  12 +
>   drivers/gpu/drm/i915/icl_dsi.c       | 417 ++++++++++++++++++++++++++++++++++-
>   drivers/gpu/drm/i915/intel_display.c |  34 ++-
>   drivers/gpu/drm/i915/intel_dsi_vbt.c |  58 ++++-
>   drivers/gpu/drm/i915/intel_panel.c   |   3 +-
>   5 files changed, 505 insertions(+), 19 deletions(-)
>

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Re: [PATCH v10 00/15] drm/i915/icl: dsi enabling

[Chauhan, Madhav]

> -----Original Message-----
> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
> Madhav Chauhan
> Sent: Friday, November 30, 2018 7:43 PM
> To: Nikula, Jani <jani.nikula@intel.com>; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v10 00/15] drm/i915/icl: dsi enabling
> 
> On 11/2/2018 5:17 PM, Jani Nikula wrote:
> > Next version of [1]. Sorry for the spam, needed to get the authorship
> > straight. Fixed power domains and compute config hook initialization.
> 
> Overall, with this series ICL DSI dual link video mode feature looks complete
> to me. Thanks!!

I meant for v11 :)

> 
> Regards,
> Madhav
> 
> >
> > BR,
> > Jani.
> >
> > [1] https://patchwork.freedesktop.org/series/51011/
> >
> >
> > Jani Nikula (1):
> >    drm/i915/icl: add dummy DSI GPIO element execution function
> >
> > Madhav Chauhan (14):
> >    drm/i915/icl: Allocate DSI encoder/connector
> >    drm/i915/icl: Fill DSI ports info
> >    drm/i915/icl: Allocate DSI hosts and imlement host transfer
> >    drm/i915/icl: Add get config functionality for DSI
> >    drm/i915/icl: Get HW state for DSI encoder
> >    drm/i915/icl: Add DSI encoder remaining functions
> >    drm/i915/icl: Configure DSI Dual link mode
> >    drm/i915/icl: Consider DSI for getting transcoder state
> >    drm/i915/icl: Get pipe timings for DSI
> >    drm/i915/icl: Define missing bitfield for shortplug reg
> >    drm/i915/icl: Define Panel power ctrl register
> >    drm/i915/icl: Define display GPIO pins for DSI
> >    HACK: drm/i915/icl: Add changes to program DSI panel GPIOs
> >    HACK: drm/i915/icl: Configure backlight functions for DSI
> >
> >   drivers/gpu/drm/i915/i915_reg.h      |  12 +
> >   drivers/gpu/drm/i915/icl_dsi.c       | 417
> ++++++++++++++++++++++++++++++++++-
> >   drivers/gpu/drm/i915/intel_display.c |  34 ++-
> >   drivers/gpu/drm/i915/intel_dsi_vbt.c |  58 ++++-
> >   drivers/gpu/drm/i915/intel_panel.c   |   3 +-
> >   5 files changed, 505 insertions(+), 19 deletions(-)
> >
> 
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> Intel-gfx@lists.freedesktop.org
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