From: Marek Vasut <marek.vasut@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH V3 07/13] mmc: tmio: Do not set divider to 1 in DDR mode
Date: Fri, 2 Nov 2018 16:03:22 +0100 [thread overview]
Message-ID: <20181102150328.21972-7-marek.vasut+renesas@gmail.com> (raw)
In-Reply-To: <20181102150328.21972-1-marek.vasut+renesas@gmail.com>
The TMIO core has a quirk where divider == 1 must not be set in DDR modes.
Handle this by setting divider to 2, as suggested in the documentation.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
---
V2: No change
V3: No change
---
drivers/mmc/tmio-common.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c
index 3ba2f07460..424b60ce52 100644
--- a/drivers/mmc/tmio-common.c
+++ b/drivers/mmc/tmio-common.c
@@ -574,6 +574,10 @@ static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv,
divisor = DIV_ROUND_UP(mclk, mmc->clock);
+ /* Do not set divider to 0xff in DDR mode */
+ if (mmc->ddr_mode && (divisor == 1))
+ divisor = 2;
+
if (divisor <= 1)
val = (priv->caps & TMIO_SD_CAP_RCAR) ?
TMIO_SD_CLKCTL_RCAR_DIV1 : TMIO_SD_CLKCTL_DIV1;
--
2.18.0
next prev parent reply other threads:[~2018-11-02 15:03 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-02 15:03 [U-Boot] [PATCH V3 01/13] mmc: tmio: Simplify pinmux handling Marek Vasut
2018-11-02 15:03 ` [U-Boot] [PATCH V3 02/13] mmc: tmio: Improve error handling Marek Vasut
2018-11-02 15:03 ` [U-Boot] [PATCH V3 03/13] mmc: tmio: Silence transfer errors when tuning Marek Vasut
2018-11-02 15:03 ` [U-Boot] [PATCH V3 04/13] mmc: tmio: Configure clock before any other IOS Marek Vasut
2018-11-02 15:03 ` [U-Boot] [PATCH V3 05/13] mmc: tmio: Preinitialize regulator to 3.3V Marek Vasut
2018-11-02 15:03 ` [U-Boot] [PATCH V3 06/13] mmc: tmio: Switch to clock framework Marek Vasut
2018-11-02 15:03 ` Marek Vasut [this message]
2018-11-02 15:03 ` [U-Boot] [PATCH V3 08/13] mmc: tmio: Keep generating clock when clock are enabled Marek Vasut
2018-11-02 15:03 ` [U-Boot] [PATCH V3 09/13] mmc: tmio: sdhi: Touch SCC only when UHS capable Marek Vasut
2018-11-02 15:03 ` [U-Boot] [PATCH V3 10/13] mmc: tmio: sdhi: Clear HS400 settings when resetting SCC Marek Vasut
2018-11-02 15:03 ` [U-Boot] [PATCH V3 11/13] mmc: tmio: sdhi: Implement waiting for DAT0 line state Marek Vasut
2018-11-02 15:03 ` [U-Boot] [PATCH V3 12/13] mmc: tmio: sdhi: Switch CPG settings in UHS modes Marek Vasut
2018-11-02 15:03 ` [U-Boot] [PATCH V3 13/13] mmc: tmio: sdhi: Merge DTCNTL access into single register write Marek Vasut
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