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Date: Fri, 2 Nov 2018 16:26:50 +0100
From: Simon Horman <horms@verge.net.au>
To: Niklas =?utf-8?Q?S=C3=B6derlund?= <niklas.soderlund@ragnatech.se>
Cc: Wolfram Sang <wsa+renesas@sang-engineering.com>,
        Masahiro Yamada <yamada.masahiro@socionext.com>,
        Ulf Hansson <ulf.hansson@linaro.org>,
        linux-mmc@vger.kernel.org, linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH] mmc: renesas_sdhi: remove workaround for HS400 clock
Message-ID: <20181102152646.37qfp2nma4xqqxle@verge.net.au>
References: <20181031225944.1226-1-niklas.soderlund@ragnatech.se>
 <20181102115502.if7heamsrphlal5k@verge.net.au>
 <20181102124247.GA13506@bigcity.dyn.berto.se>
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On Fri, Nov 02, 2018 at 01:42:47PM +0100, Niklas Söderlund wrote:
> Hi Simon,
> 
> On 2018-11-02 12:55:02 +0100, Simon Horman wrote:
> > On Wed, Oct 31, 2018 at 11:59:44PM +0100, Niklas Söderlund wrote:
> > > From: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
> > > 
> > > The driver sets an incorrect clock and depends on the clock driver
> > > knowledge of this incorrect setting to still set a 200Mhz SDn clock.
> > > Instead of spreading the workaround between the two drivers the clock
> > > driver should be made aware of the ES versions where the special clock
> > > handling is needed no need to keep this workaround in the SDHI driver.
> > > 
> > > Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
> > 
> > Does this change cause a regression pending an update
> > to the clock driver?
> 
> No it does not, the corresponding BSP commit to the clock driver [1] was 
> never part of upstream. This change should never have been merged 
> upstream as it uses the hack from the BSP clock driver. Also HS400 have 
> never been enabled upstream for Gen3.
> 
> 1. 11fca067bde0221d ("clk: renesas: rcar-gen3: Fix SD divider setting")

Thanks, got it.

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>