From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46754) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gJjzP-0005OW-Ih for qemu-devel@nongnu.org; Mon, 05 Nov 2018 13:52:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gJjzO-0001At-21 for qemu-devel@nongnu.org; Mon, 05 Nov 2018 13:52:43 -0500 From: Aaron Lindsay Date: Mon, 5 Nov 2018 18:52:01 +0000 Message-ID: <20181105185046.2802-11-aaron@os.amperecomputing.com> References: <20181105185046.2802-1-aaron@os.amperecomputing.com> In-Reply-To: <20181105185046.2802-1-aaron@os.amperecomputing.com> Content-Language: en-US Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: [Qemu-devel] [PATCH v7 10/12] target/arm: PMU: Set PMCR.N to 4 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "qemu-arm@nongnu.org" , Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite , Richard Henderson Cc: "qemu-devel@nongnu.org" , Michael Spradling , Digant Desai , Aaron Lindsay , Aaron Lindsay This both advertises that we support four counters and enables them because the pmu_num_counters() reads this value from PMCR. Signed-off-by: Aaron Lindsay Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index e3ec36490c..11eb62bdda 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1753,7 +1753,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .access =3D PL1_W, .type =3D ARM_CP_NOP }, /* Performance monitors are implementation defined in v7, * but with an ARM recommended set of registers, which we - * follow (although we don't actually implement any counters) + * follow. * * Performance registers fall into three categories: * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) @@ -5508,10 +5508,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) } if (arm_feature(env, ARM_FEATURE_V7)) { /* v7 performance monitor control register: same implementor - * field as main ID register, and we implement only the cycle - * count register. + * field as main ID register, and we implement four counters in + * addition to the cycle count register. */ - unsigned int i, pmcrn =3D 0; + unsigned int i, pmcrn =3D 4; ARMCPRegInfo pmcr =3D { .name =3D "PMCR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 = =3D 0, .opc2 =3D 0, .access =3D PL0_RW, @@ -5526,7 +5526,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL0_RW, .accessfn =3D pmreg_access, .type =3D ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcr), - .resetvalue =3D cpu->midr & 0xff000000, + .resetvalue =3D (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHI= FT), .writefn =3D pmcr_write, .raw_writefn =3D raw_write, }; define_one_arm_cp_reg(cpu, &pmcr); --=20 2.19.1