From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46858) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gJjzX-0005ZR-Mj for qemu-devel@nongnu.org; Mon, 05 Nov 2018 13:52:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gJjzW-0001Sa-7r for qemu-devel@nongnu.org; Mon, 05 Nov 2018 13:52:51 -0500 From: Aaron Lindsay Date: Mon, 5 Nov 2018 18:52:03 +0000 Message-ID: <20181105185046.2802-13-aaron@os.amperecomputing.com> References: <20181105185046.2802-1-aaron@os.amperecomputing.com> In-Reply-To: <20181105185046.2802-1-aaron@os.amperecomputing.com> Content-Language: en-US Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: [Qemu-devel] [PATCH v7 12/12] target/arm: Send interrupts on PMU counter overflow List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "qemu-arm@nongnu.org" , Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite , Richard Henderson Cc: "qemu-devel@nongnu.org" , Michael Spradling , Digant Desai , Aaron Lindsay , Aaron Lindsay Setup a QEMUTimer to get a callback when we expect counters to next overflow and trigger an interrupt at that time. Signed-off-by: Aaron Lindsay --- target/arm/cpu.c | 11 ++++ target/arm/cpu.h | 7 +++ target/arm/helper.c | 126 +++++++++++++++++++++++++++++++++++++++++--- 3 files changed, 138 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d1c766d180..7cb6a76afb 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -764,6 +764,12 @@ static void arm_cpu_finalizefn(Object *obj) QLIST_REMOVE(hook, node); g_free(hook); } +#ifndef CONFIG_USER_ONLY + if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { + timer_deinit(cpu->pmu_timer); + timer_free(cpu->pmu_timer); + } +#endif } =20 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) @@ -967,6 +973,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Error = **errp) arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); } + +#ifndef CONFIG_USER_ONLY + cpu->pmu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_= cb, + cpu); +#endif } else { cpu->pmceid0 =3D 0x00000000; cpu->pmceid1 =3D 0x00000000; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 067f6efdb6..fa49dc4c47 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -730,6 +730,8 @@ struct ARMCPU { =20 /* Timers used by the generic (architected) timer */ QEMUTimer *gt_timer[NUM_GTIMERS]; + /* Timer used by the PMU */ + QEMUTimer *pmu_timer; /* GPIO outputs for generic timer */ qemu_irq gt_timer_outputs[NUM_GTIMERS]; /* GPIO output for GICv3 maintenance interrupt signal */ @@ -988,6 +990,11 @@ void pmccntr_op_finish(CPUARMState *env); void pmu_op_start(CPUARMState *env); void pmu_op_finish(CPUARMState *env); =20 +/** + * Called when a PMU counter is due to overflow + */ +void arm_pmu_timer_cb(void *opaque); + /** * Functions to register as EL change hooks for PMU mode filtering */ diff --git a/target/arm/helper.c b/target/arm/helper.c index cff3a5a562..6c3f997b0e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -977,6 +977,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { /* Definitions for the PMU registers */ #define PMCRN_MASK 0xf800 #define PMCRN_SHIFT 11 +#define PMCRLC 0x40 #define PMCRDP 0x10 #define PMCRD 0x8 #define PMCRC 0x4 @@ -996,6 +997,8 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { PMXEVTYPER_M | PMXEVTYPER_MT | \ PMXEVTYPER_EVTCOUNT) =20 +#define PMEVCNTR_OVERFLOW_MASK ((uint64_t)1 << 31) + #define PMCCFILTR 0xf8000000 #define PMCCFILTR_M PMXEVTYPER_M #define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M) @@ -1020,6 +1023,11 @@ typedef struct pm_event { * counters hold a difference from the return value from this function */ uint64_t (*get_count)(CPUARMState *); + /* Return how many nanoseconds it will take (at a minimum) for count e= vents + * to occur. A negative value indicates the counter will never overflo= w, or + * that the counter has otherwise arranged for the overflow bit to be = set + * and the PMU interrupt to be raised on overflow. */ + int64_t (*ns_per_count)(uint64_t); } pm_event; =20 static bool event_always_supported(CPUARMState *env) @@ -1036,6 +1044,11 @@ static uint64_t swinc_get_count(CPUARMState *env) return 0; } =20 +static int64_t swinc_ns_per(uint64_t ignored) +{ + return -1; +} + /* * Return the underlying cycle count for the PMU cycle counters. If we're = in * usermode, simply return 0. @@ -1051,6 +1064,11 @@ static uint64_t cycles_get_count(CPUARMState *env) } =20 #ifndef CONFIG_USER_ONLY +static int64_t cycles_ns_per(uint64_t cycles) +{ + return (ARM_CPU_FREQ / NANOSECONDS_PER_SECOND) * cycles; +} + static bool instructions_supported(CPUARMState *env) { return use_icount =3D=3D 1 /* Precise instruction counting */; @@ -1060,21 +1078,29 @@ static uint64_t instructions_get_count(CPUARMState = *env) { return (uint64_t)cpu_get_icount_raw(); } + +static int64_t instructions_ns_per(uint64_t icount) +{ + return cpu_icount_to_ns((int64_t)icount); +} #endif =20 static const pm_event pm_events[] =3D { { .number =3D 0x000, /* SW_INCR */ .supported =3D event_always_supported, .get_count =3D swinc_get_count, + .ns_per_count =3D swinc_ns_per, }, #ifndef CONFIG_USER_ONLY { .number =3D 0x008, /* INST_RETIRED, Instruction architecturally exec= uted */ .supported =3D instructions_supported, .get_count =3D instructions_get_count, + .ns_per_count =3D instructions_ns_per, }, { .number =3D 0x011, /* CPU_CYCLES, Cycle */ .supported =3D event_always_supported, .get_count =3D cycles_get_count, + .ns_per_count =3D cycles_ns_per, } #endif }; @@ -1273,6 +1299,13 @@ static bool pmu_counter_enabled(CPUARMState *env, ui= nt8_t counter) return enabled && !prohibited && !filtered; } =20 +static void pmu_update_irq(CPUARMState *env) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && + (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); +} + /* * Ensure c15_ccnt is the guest-visible count so that operations such as * enabling/disabling the counter or filtering, modifying the count itself= , @@ -1290,7 +1323,18 @@ void pmccntr_op_start(CPUARMState *env) eff_cycles /=3D 64; } =20 - env->cp15.c15_ccnt =3D eff_cycles - env->cp15.c15_ccnt_delta; + uint64_t new_pmccntr =3D eff_cycles - env->cp15.c15_ccnt_delta; + + unsigned int overflow_bit =3D (env->cp15.c9_pmcr & PMCRLC) ? 63 : = 31; + uint64_t overflow_mask =3D (uint64_t)1 << overflow_bit; + if (!(new_pmccntr & overflow_mask) && + (env->cp15.c15_ccnt & overflow_mask)) { + env->cp15.c9_pmovsr |=3D (1 << 31); + new_pmccntr &=3D ~overflow_mask; + pmu_update_irq(env); + } + + env->cp15.c15_ccnt =3D new_pmccntr; } env->cp15.c15_ccnt_delta =3D cycles; } @@ -1303,13 +1347,28 @@ void pmccntr_op_start(CPUARMState *env) void pmccntr_op_finish(CPUARMState *env) { if (pmu_counter_enabled(env, 31)) { - uint64_t prev_cycles =3D env->cp15.c15_ccnt_delta; +#ifndef CONFIG_USER_ONLY + uint64_t delta; + if (env->cp15.c9_pmcr & PMCRLC) { + delta =3D UINT64_MAX - env->cp15.c15_ccnt + 1; + } else { + delta =3D UINT32_MAX - (uint32_t)env->cp15.c15_ccnt + 1; + } + int64_t overflow_in =3D cycles_ns_per(delta); + + if (overflow_in > 0) { + int64_t overflow_at =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) = + + overflow_in; + ARMCPU *cpu =3D arm_env_get_cpu(env); + timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); + } +#endif =20 + uint64_t prev_cycles =3D env->cp15.c15_ccnt_delta; if (env->cp15.c9_pmcr & PMCRD) { /* Increment once every 64 processor clock cycles */ prev_cycles /=3D 64; } - env->cp15.c15_ccnt_delta =3D prev_cycles - env->cp15.c15_ccnt; } } @@ -1325,8 +1384,15 @@ static void pmevcntr_op_start(CPUARMState *env, uint= 8_t counter) } =20 if (pmu_counter_enabled(env, counter)) { - env->cp15.c14_pmevcntr[counter] =3D - count - env->cp15.c14_pmevcntr_delta[counter]; + uint64_t new_pmevcntr =3D count - env->cp15.c14_pmevcntr_delta[cou= nter]; + + if (!(new_pmevcntr & PMEVCNTR_OVERFLOW_MASK) && + (env->cp15.c14_pmevcntr[counter] & PMEVCNTR_OVERFLOW_MASK)= ) { + env->cp15.c9_pmovsr |=3D (1 << counter); + new_pmevcntr &=3D ~PMEVCNTR_OVERFLOW_MASK; + pmu_update_irq(env); + } + env->cp15.c14_pmevcntr[counter] =3D new_pmevcntr; } env->cp15.c14_pmevcntr_delta[counter] =3D count; } @@ -1334,6 +1400,21 @@ static void pmevcntr_op_start(CPUARMState *env, uint= 8_t counter) static void pmevcntr_op_finish(CPUARMState *env, uint8_t counter) { if (pmu_counter_enabled(env, counter)) { +#ifndef CONFIG_USER_ONLY + uint16_t event =3D env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_E= VTCOUNT; + uint16_t event_idx =3D supported_event_map[event]; + uint64_t delta =3D UINT32_MAX - + (uint32_t)env->cp15.c14_pmevcntr[counter] + 1; + int64_t overflow_in =3D pm_events[event_idx].ns_per_count(delta); + + if (overflow_in > 0) { + int64_t overflow_at =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) = + + overflow_in; + ARMCPU *cpu =3D arm_env_get_cpu(env); + timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); + } +#endif + env->cp15.c14_pmevcntr_delta[counter] -=3D env->cp15.c14_pmevcntr[counter]; } @@ -1367,6 +1448,19 @@ void pmu_post_el_change(ARMCPU *cpu, void *ignored) pmu_op_finish(&cpu->env); } =20 +void arm_pmu_timer_cb(void *opaque) +{ + ARMCPU *cpu =3D opaque; + + /* Update all the counter values based on the current underlying count= s, + * triggering interrupts to be raised, if necessary. pmu_op_finish() a= lso + * has the effect of setting the cpu->pmu_timer to the next earliest t= ime a + * counter may expire. + */ + pmu_op_start(&cpu->env); + pmu_op_finish(&cpu->env); +} + static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1403,7 +1497,21 @@ static void pmswinc_write(CPUARMState *env, const AR= MCPRegInfo *ri, /* counter is SW_INCR */ (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) =3D=3D = 0x0) { pmevcntr_op_start(env, i); - env->cp15.c14_pmevcntr[i]++; + + /* Detect if this write causes an overflow since we can't pred= ict + * PMSWINC overflows like we can for other events + */ + uint64_t new_pmswinc =3D env->cp15.c14_pmevcntr[i] + 1; + + if (!(new_pmswinc & PMEVCNTR_OVERFLOW_MASK) && + (env->cp15.c14_pmevcntr[i] & PMEVCNTR_OVERFLOW_MASK)) = { + env->cp15.c9_pmovsr |=3D (1 << i); + new_pmswinc &=3D ~PMEVCNTR_OVERFLOW_MASK; + pmu_update_irq(env); + } + + env->cp15.c14_pmevcntr[i] =3D new_pmswinc; + pmevcntr_op_finish(env, i); } } @@ -1474,6 +1582,7 @@ static void pmcntenset_write(CPUARMState *env, const = ARMCPRegInfo *ri, { value &=3D pmu_counter_mask(env); env->cp15.c9_pmcnten |=3D value; + pmu_update_irq(env); } =20 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1481,6 +1590,7 @@ static void pmcntenclr_write(CPUARMState *env, const = ARMCPRegInfo *ri, { value &=3D pmu_counter_mask(env); env->cp15.c9_pmcnten &=3D ~value; + pmu_update_irq(env); } =20 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1488,6 +1598,7 @@ static void pmovsr_write(CPUARMState *env, const ARMC= PRegInfo *ri, { value &=3D pmu_counter_mask(env); env->cp15.c9_pmovsr &=3D ~value; + pmu_update_irq(env); } =20 static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1495,6 +1606,7 @@ static void pmovsset_write(CPUARMState *env, const AR= MCPRegInfo *ri, { value &=3D pmu_counter_mask(env); env->cp15.c9_pmovsr |=3D value; + pmu_update_irq(env); } =20 static void pmevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1681,6 +1793,7 @@ static void pmintenset_write(CPUARMState *env, const = ARMCPRegInfo *ri, /* We have no event counters so only the C bit can be changed */ value &=3D pmu_counter_mask(env); env->cp15.c9_pminten |=3D value; + pmu_update_irq(env); } =20 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1688,6 +1801,7 @@ static void pmintenclr_write(CPUARMState *env, const = ARMCPRegInfo *ri, { value &=3D pmu_counter_mask(env); env->cp15.c9_pminten &=3D ~value; + pmu_update_irq(env); } =20 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, --=20 2.19.1