From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60252) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gJzh0-0008IZ-TI for qemu-devel@nongnu.org; Tue, 06 Nov 2018 06:38:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gJzgz-0004OG-NE for qemu-devel@nongnu.org; Tue, 06 Nov 2018 06:38:46 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:52310) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gJzgz-00049H-GJ for qemu-devel@nongnu.org; Tue, 06 Nov 2018 06:38:45 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gJzgm-0007dI-WF for qemu-devel@nongnu.org; Tue, 06 Nov 2018 11:38:33 +0000 From: Peter Maydell Date: Tue, 6 Nov 2018 11:38:25 +0000 Message-Id: <20181106113826.25810-5-peter.maydell@linaro.org> In-Reply-To: <20181106113826.25810-1-peter.maydell@linaro.org> References: <20181106113826.25810-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PULL 4/5] target/arm: Set S and PTW in 64-bit PAR format List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org In do_ats_write() we construct a PAR value based on the result of the translation. A comment says "S2WLK and FSTAGE are always zero, because we don't implement virtualization". Since we do in fact now implement virtualization, add the missing code that sets these bits based on the reported ARMMMUFaultInfo. (These bits are named PTW and S in ARMv8, so we follow that convention in the new comments in this patch.) Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Reviewed-by: Alex Bennée Message-id: 20181016093703.10637-2-peter.maydell@linaro.org --- target/arm/helper.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0ea95b08151..69f684abd89 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2347,10 +2347,12 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, par64 |= 1; /* F */ par64 |= (fsr & 0x3f) << 1; /* FS */ - /* Note that S2WLK and FSTAGE are always zero, because we don't - * implement virtualization and therefore there can't be a stage 2 - * fault. - */ + if (fi.stage2) { + par64 |= (1 << 9); /* S */ + } + if (fi.s1ptw) { + par64 |= (1 << 8); /* PTW */ + } } } else { /* fsr is a DFSR/IFSR value for the short descriptor -- 2.19.1