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From: Borislav Petkov <bp@alien8.de>
To: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: linux@armlinux.org.uk, u.kleine-koenig@pengutronix.de,
	jlu@pengutronix.de, linux-arm-kernel@lists.infradead.org,
	linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	devicetree@vger.kernel.org
Subject: Re: [PATCH v5 5/8] ARM: l2x0: add marvell,ecc-enable property for aurora
Date: Thu, 8 Nov 2018 16:17:43 +0100	[thread overview]
Message-ID: <20181108151743.GE7543@zn.tnic> (raw)
In-Reply-To: <20181029072535.31667-6-chris.packham@alliedtelesis.co.nz>

On Mon, Oct 29, 2018 at 08:25:32PM +1300, Chris Packham wrote:
> The aurora cache on the Marvell Armada-XP SoC supports ECC protection
> for the L2 data arrays. Add a "marvell,ecc-enable" device tree property
> which can be used to enable this.
> 
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> [jlu@pengutronix.de: use aurora specific define AURORA_ACR_ECC_EN]
> Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
> ---
>  Documentation/devicetree/bindings/arm/l2c2x0.txt | 2 ++
>  arch/arm/mm/cache-l2x0.c                         | 7 +++++++
>  2 files changed, 9 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt b/Documentation/devicetree/bindings/arm/l2c2x0.txt
> index fbe6cb21f4cf..15a84f0ba9f1 100644
> --- a/Documentation/devicetree/bindings/arm/l2c2x0.txt
> +++ b/Documentation/devicetree/bindings/arm/l2c2x0.txt
> @@ -76,6 +76,8 @@ Optional properties:
>    specified to indicate that such transforms are precluded.
>  - arm,parity-enable : enable parity checking on the L2 cache (L220 or PL310).
>  - arm,parity-disable : disable parity checking on the L2 cache (L220 or PL310).
> +- marvell,ecc-enable : enable ECC protection on the L2 cache
> +- marvell,ecc-disable : disable ECC protection on the L2 cache
>  - arm,outer-sync-disable : disable the outer sync operation on the L2 cache.
>    Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that
>    will randomly hang unless outer sync operations are disabled.
> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
> index b70bee74750d..644f786e4fa9 100644
> --- a/arch/arm/mm/cache-l2x0.c
> +++ b/arch/arm/mm/cache-l2x0.c
> @@ -1505,6 +1505,13 @@ static void __init aurora_of_parse(const struct device_node *np,
>  		mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK;
>  	}
>  
> +	if (of_property_read_bool(np, "marvell,ecc-enable")) {
> +		mask |= AURORA_ACR_ECC_EN;
> +		val |= AURORA_ACR_ECC_EN;
> +	} else if (of_property_read_bool(np, "marvell,ecc-disable")) {
> +		mask |= AURORA_ACR_ECC_EN;
> +	}
> +
>  	if (of_property_read_bool(np, "arm,parity-enable")) {
>  		mask |= AURORA_ACR_PARITY_EN;
>  		val |= AURORA_ACR_PARITY_EN;
> -- 

checkpatch complains here:

WARNING: DT binding docs and includes should be a separate patch. See: Documentation/devicetree/bindings/submitting-patches.txt

-- 
Regards/Gruss,
    Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

WARNING: multiple messages have this Message-ID
From: Borislav Petkov <bp@alien8.de>
To: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: linux@armlinux.org.uk, u.kleine-koenig@pengutronix.de,
	jlu@pengutronix.de, linux-arm-kernel@lists.infradead.org,
	linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	devicetree@vger.kernel.org
Subject: [v5,5/8] ARM: l2x0: add marvell,ecc-enable property for aurora
Date: Thu, 8 Nov 2018 16:17:43 +0100	[thread overview]
Message-ID: <20181108151743.GE7543@zn.tnic> (raw)

On Mon, Oct 29, 2018 at 08:25:32PM +1300, Chris Packham wrote:
> The aurora cache on the Marvell Armada-XP SoC supports ECC protection
> for the L2 data arrays. Add a "marvell,ecc-enable" device tree property
> which can be used to enable this.
> 
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> [jlu@pengutronix.de: use aurora specific define AURORA_ACR_ECC_EN]
> Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
> ---
>  Documentation/devicetree/bindings/arm/l2c2x0.txt | 2 ++
>  arch/arm/mm/cache-l2x0.c                         | 7 +++++++
>  2 files changed, 9 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt b/Documentation/devicetree/bindings/arm/l2c2x0.txt
> index fbe6cb21f4cf..15a84f0ba9f1 100644
> --- a/Documentation/devicetree/bindings/arm/l2c2x0.txt
> +++ b/Documentation/devicetree/bindings/arm/l2c2x0.txt
> @@ -76,6 +76,8 @@ Optional properties:
>    specified to indicate that such transforms are precluded.
>  - arm,parity-enable : enable parity checking on the L2 cache (L220 or PL310).
>  - arm,parity-disable : disable parity checking on the L2 cache (L220 or PL310).
> +- marvell,ecc-enable : enable ECC protection on the L2 cache
> +- marvell,ecc-disable : disable ECC protection on the L2 cache
>  - arm,outer-sync-disable : disable the outer sync operation on the L2 cache.
>    Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that
>    will randomly hang unless outer sync operations are disabled.
> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
> index b70bee74750d..644f786e4fa9 100644
> --- a/arch/arm/mm/cache-l2x0.c
> +++ b/arch/arm/mm/cache-l2x0.c
> @@ -1505,6 +1505,13 @@ static void __init aurora_of_parse(const struct device_node *np,
>  		mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK;
>  	}
>  
> +	if (of_property_read_bool(np, "marvell,ecc-enable")) {
> +		mask |= AURORA_ACR_ECC_EN;
> +		val |= AURORA_ACR_ECC_EN;
> +	} else if (of_property_read_bool(np, "marvell,ecc-disable")) {
> +		mask |= AURORA_ACR_ECC_EN;
> +	}
> +
>  	if (of_property_read_bool(np, "arm,parity-enable")) {
>  		mask |= AURORA_ACR_PARITY_EN;
>  		val |= AURORA_ACR_PARITY_EN;
> -- 

checkpatch complains here:

WARNING: DT binding docs and includes should be a separate patch. See: Documentation/devicetree/bindings/submitting-patches.txt

WARNING: multiple messages have this Message-ID
From: bp@alien8.de (Borislav Petkov)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 5/8] ARM: l2x0: add marvell,ecc-enable property for aurora
Date: Thu, 8 Nov 2018 16:17:43 +0100	[thread overview]
Message-ID: <20181108151743.GE7543@zn.tnic> (raw)
In-Reply-To: <20181029072535.31667-6-chris.packham@alliedtelesis.co.nz>

On Mon, Oct 29, 2018 at 08:25:32PM +1300, Chris Packham wrote:
> The aurora cache on the Marvell Armada-XP SoC supports ECC protection
> for the L2 data arrays. Add a "marvell,ecc-enable" device tree property
> which can be used to enable this.
> 
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> [jlu at pengutronix.de: use aurora specific define AURORA_ACR_ECC_EN]
> Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
> ---
>  Documentation/devicetree/bindings/arm/l2c2x0.txt | 2 ++
>  arch/arm/mm/cache-l2x0.c                         | 7 +++++++
>  2 files changed, 9 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt b/Documentation/devicetree/bindings/arm/l2c2x0.txt
> index fbe6cb21f4cf..15a84f0ba9f1 100644
> --- a/Documentation/devicetree/bindings/arm/l2c2x0.txt
> +++ b/Documentation/devicetree/bindings/arm/l2c2x0.txt
> @@ -76,6 +76,8 @@ Optional properties:
>    specified to indicate that such transforms are precluded.
>  - arm,parity-enable : enable parity checking on the L2 cache (L220 or PL310).
>  - arm,parity-disable : disable parity checking on the L2 cache (L220 or PL310).
> +- marvell,ecc-enable : enable ECC protection on the L2 cache
> +- marvell,ecc-disable : disable ECC protection on the L2 cache
>  - arm,outer-sync-disable : disable the outer sync operation on the L2 cache.
>    Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that
>    will randomly hang unless outer sync operations are disabled.
> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
> index b70bee74750d..644f786e4fa9 100644
> --- a/arch/arm/mm/cache-l2x0.c
> +++ b/arch/arm/mm/cache-l2x0.c
> @@ -1505,6 +1505,13 @@ static void __init aurora_of_parse(const struct device_node *np,
>  		mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK;
>  	}
>  
> +	if (of_property_read_bool(np, "marvell,ecc-enable")) {
> +		mask |= AURORA_ACR_ECC_EN;
> +		val |= AURORA_ACR_ECC_EN;
> +	} else if (of_property_read_bool(np, "marvell,ecc-disable")) {
> +		mask |= AURORA_ACR_ECC_EN;
> +	}
> +
>  	if (of_property_read_bool(np, "arm,parity-enable")) {
>  		mask |= AURORA_ACR_PARITY_EN;
>  		val |= AURORA_ACR_PARITY_EN;
> -- 

checkpatch complains here:

WARNING: DT binding docs and includes should be a separate patch. See: Documentation/devicetree/bindings/submitting-patches.txt

-- 
Regards/Gruss,
    Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

  parent reply	other threads:[~2018-11-08 15:17 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-29  7:25 [PATCH v5 0/8] EDAC drivers for Armada XP L2 and DDR Chris Packham
2018-10-29  7:25 ` Chris Packham
2018-10-29  7:25 ` [PATCH v5 1/8] ARM: l2c: move cache-aurora-l2.h to asm/hardware Chris Packham
2018-10-29  7:25   ` Chris Packham
2018-10-29  7:25   ` [v5,1/8] " Chris Packham
2018-10-29  7:25 ` [PATCH v5 2/8] ARM: aurora-l2: add prefix to MAX_RANGE_SIZE Chris Packham
2018-10-29  7:25   ` Chris Packham
2018-10-29  7:25   ` [v5,2/8] " Chris Packham
2018-10-29  7:25 ` [PATCH v5 3/8] ARM: aurora-l2: add defines for parity and ECC registers Chris Packham
2018-10-29  7:25   ` Chris Packham
2018-10-29  7:25   ` [v5,3/8] " Chris Packham
2018-10-29  7:25 ` [PATCH v5 4/8] ARM: l2x0: support parity-enable/disable on aurora Chris Packham
2018-10-29  7:25   ` Chris Packham
2018-10-29  7:25   ` [v5,4/8] " Chris Packham
2018-10-29  7:25 ` [PATCH v5 5/8] ARM: l2x0: add marvell,ecc-enable property for aurora Chris Packham
2018-10-29  7:25   ` Chris Packham
2018-10-29  7:25   ` [v5,5/8] " Chris Packham
2018-10-30 19:31   ` [PATCH v5 5/8] " Rob Herring
2018-10-30 19:31     ` Rob Herring
2018-10-30 19:31     ` Rob Herring
2018-10-30 19:31     ` [v5,5/8] " Rob Herring
2018-11-08 15:17   ` Borislav Petkov [this message]
2018-11-08 15:17     ` [PATCH v5 5/8] " Borislav Petkov
2018-11-08 15:17     ` [v5,5/8] " Borislav Petkov
2018-10-29  7:25 ` [PATCH v5 6/8] EDAC: Add missing debugfs_create_x32 wrapper Chris Packham
2018-10-29  7:25   ` Chris Packham
2018-10-29  7:25   ` [v5,6/8] " Chris Packham
2018-10-29  7:25 ` [PATCH v5 7/8] EDAC: Add driver for the Marvell Armada XP SDRAM and L2 cache ECC Chris Packham
2018-10-29  7:25   ` Chris Packham
2018-10-29  7:25   ` [v5,7/8] " Chris Packham
2018-10-29  7:25 ` [PATCH v5 8/8] EDAC: armada_xp: Add support for more SoCs Chris Packham
2018-10-29  7:25   ` Chris Packham
2018-10-29  7:25   ` [v5,8/8] " Chris Packham

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