From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,UPPERCASE_50_75,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E647BC43441 for ; Fri, 9 Nov 2018 07:04:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AB7AA20883 for ; Fri, 9 Nov 2018 07:04:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b="SmlZi/7r" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AB7AA20883 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=alliedtelesis.co.nz Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728065AbeKIQnc (ORCPT ); Fri, 9 Nov 2018 11:43:32 -0500 Received: from gate2.alliedtelesis.co.nz ([202.36.163.20]:45793 "EHLO gate2.alliedtelesis.co.nz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728060AbeKIQnb (ORCPT ); Fri, 9 Nov 2018 11:43:31 -0500 Received: from mmarshal3.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id AD66E886B5; Fri, 9 Nov 2018 20:04:15 +1300 (NZDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1541747055; bh=kYBflEaqCViIATbPoUT7Qcmh1CYF3yDA8Hzlo/yMh20=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=SmlZi/7rtU0WFTocr+BsHp1Ckwvz+ooaNhnJyPJfjwdzeY9SdfzN0V1otX+ybOELn HSVQUN9AXow2akmfcaH/8cryHyZ/b0SuBWPklzYNKE56vbRETNS8B3njveHVBvTtek DytQuB9jVPxth52SGAbeJ7cCcYPCFuXQ3v5JBEV/1o/oGyv7m4VWlRBwNjQQFhqVmb Zog8OxHx0Houk+OPHF+urLNd+U2KaI3JE2zpksYg099VLPurcBip7LApHud5dNY5Af mVyxSEwMQ0nsLr8RTHmbiubcqAATeXOXg67oYWXSE9R2bfQH3eyaAV93Dw4ZOCvsay a9czGUiyhIsCQ== Received: from smtp (Not Verified[10.32.16.33]) by mmarshal3.atlnz.lc with Trustwave SEG (v7,5,8,10121) id ; Fri, 09 Nov 2018 20:03:59 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by smtp (Postfix) with ESMTP id 77A3913EEA1; Fri, 9 Nov 2018 20:04:04 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 548481E0BC9; Fri, 9 Nov 2018 20:03:59 +1300 (NZDT) From: Chris Packham To: linux@armlinux.org.uk, bp@alien8.de, arnd@arndb.de, jlu@pengutronix.de, gregory.clement@bootlin.com Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Packham Subject: [PATCH v6 3/9] ARM: aurora-l2: add defines for parity and ECC registers Date: Fri, 9 Nov 2018 20:03:43 +1300 Message-Id: <20181109070349.20464-4-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181109070349.20464-1-chris.packham@alliedtelesis.co.nz> References: <20181109070349.20464-1-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable x-atlnz-ls: pat Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Jan Luebbe These defines will be used by subsequent patches to add support for the parity check and error correction functionality in the Aurora L2 cache controller. Signed-off-by: Jan Luebbe Signed-off-by: Chris Packham --- =20.../include/asm/hardware/cache-aurora-l2.h | 48 +++++++++++++++++++= =201 file changed, 48 insertions(+) diff --git a/arch/arm/include/asm/hardware/cache-aurora-l2.h b/arch/arm/i= nclude/asm/hardware/cache-aurora-l2.h index dc5c479ec4c3..39769ffa0051 100644 --- a/arch/arm/include/asm/hardware/cache-aurora-l2.h +++ b/arch/arm/include/asm/hardware/cache-aurora-l2.h @@ -31,6 +31,9 @@ =20#define AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU \ =20 (3 << AURORA_ACR_REPLACEMENT_OFFSET) =20 +#define AURORA_ACR_PARITY_EN (1 << 21) +#define AURORA_ACR_ECC_EN (1 << 20) + =20#define AURORA_ACR_FORCE_WRITE_POLICY_OFFSET 0 =20#define AURORA_ACR_FORCE_WRITE_POLICY_MASK \ =20 (0x3 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET) @@ -41,6 +44,51 @@ =20#define AURORA_ACR_FORCE_WRITE_THRO_POLICY \ =20 (2 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET) =20 +#define AURORA_ERR_CNT_REG 0x600 +#define AURORA_ERR_ATTR_CAP_REG 0x608 +#define AURORA_ERR_ADDR_CAP_REG 0x60c +#define AURORA_ERR_WAY_CAP_REG 0x610 +#define AURORA_ERR_INJECT_CTL_REG 0x614 +#define AURORA_ERR_INJECT_MASK_REG 0x618 + +#define AURORA_ERR_CNT_CLR_OFFSET 31 +#define AURORA_ERR_CNT_CLR \ + (0x1 << AURORA_ERR_CNT_CLR_OFFSET) +#define AURORA_ERR_CNT_UE_OFFSET 16 +#define AURORA_ERR_CNT_UE_MASK \ + (0x7fff << AURORA_ERR_CNT_UE_OFFSET) +#define AURORA_ERR_CNT_CE_OFFSET 0 +#define AURORA_ERR_CNT_CE_MASK \ + (0xffff << AURORA_ERR_CNT_CE_OFFSET) + +#define AURORA_ERR_ATTR_SRC_OFF 16 +#define AURORA_ERR_ATTR_SRC_MSK \ + (0x7 << AURORA_ERR_ATTR_SRC_OFF) +#define AURORA_ERR_ATTR_TXN_OFF 12 +#define AURORA_ERR_ATTR_TXN_MSK \ + (0xf << AURORA_ERR_ATTR_TXN_OFF) +#define AURORA_ERR_ATTR_ERR_OFF 8 +#define AURORA_ERR_ATTR_ERR_MSK \ + (0x3 << AURORA_ERR_ATTR_ERR_OFF) +#define AURORA_ERR_ATTR_CAP_VALID_OFF 0 +#define AURORA_ERR_ATTR_CAP_VALID \ + (0x1 << AURORA_ERR_ATTR_CAP_VALID_OFF) + +#define AURORA_ERR_ADDR_CAP_ADDR_MASK 0xffffffe0 + +#define AURORA_ERR_WAY_IDX_OFF 8 +#define AURORA_ERR_WAY_IDX_MSK \ + (0xfff << AURORA_ERR_WAY_IDX_OFF) +#define AURORA_ERR_WAY_CAP_WAY_OFFSET 1 +#define AURORA_ERR_WAY_CAP_WAY_MASK \ + (0xf << AURORA_ERR_WAY_CAP_WAY_OFFSET) + +#define AURORA_ERR_INJECT_CTL_ADDR_MASK 0xfffffff0 +#define AURORA_ERR_ATTR_TXN_OFF 12 +#define AURORA_ERR_INJECT_CTL_EN_MASK 0x3 +#define AURORA_ERR_INJECT_CTL_EN_PARITY 0x2 +#define AURORA_ERR_INJECT_CTL_EN_ECC 0x1 + =20#define AURORA_MAX_RANGE_SIZE 1024 =20 =20#define AURORA_WAY_SIZE_SHIFT 2 --=20 2.19.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v6,3/9] ARM: aurora-l2: add defines for parity and ECC registers From: Chris Packham Message-Id: <20181109070349.20464-4-chris.packham@alliedtelesis.co.nz> Date: Fri, 9 Nov 2018 20:03:43 +1300 To: linux@armlinux.org.uk, bp@alien8.de, arnd@arndb.de, jlu@pengutronix.de, gregory.clement@bootlin.com Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Packham List-ID: RnJvbTogSmFuIEx1ZWJiZSA8amx1QHBlbmd1dHJvbml4LmRlPgoKVGhlc2UgZGVmaW5lcyB3aWxs IGJlIHVzZWQgYnkgc3Vic2VxdWVudCBwYXRjaGVzIHRvIGFkZCBzdXBwb3J0IGZvciB0aGUKcGFy aXR5IGNoZWNrIGFuZCBlcnJvciBjb3JyZWN0aW9uIGZ1bmN0aW9uYWxpdHkgaW4gdGhlIEF1cm9y YSBMMiBjYWNoZQpjb250cm9sbGVyLgoKU2lnbmVkLW9mZi1ieTogSmFuIEx1ZWJiZSA8amx1QHBl bmd1dHJvbml4LmRlPgpTaWduZWQtb2ZmLWJ5OiBDaHJpcyBQYWNraGFtIDxjaHJpcy5wYWNraGFt QGFsbGllZHRlbGVzaXMuY28ubno+Ci0tLQogLi4uL2luY2x1ZGUvYXNtL2hhcmR3YXJlL2NhY2hl LWF1cm9yYS1sMi5oICAgIHwgNDggKysrKysrKysrKysrKysrKysrKwogMSBmaWxlIGNoYW5nZWQs IDQ4IGluc2VydGlvbnMoKykKCmRpZmYgLS1naXQgYS9hcmNoL2FybS9pbmNsdWRlL2FzbS9oYXJk d2FyZS9jYWNoZS1hdXJvcmEtbDIuaCBiL2FyY2gvYXJtL2luY2x1ZGUvYXNtL2hhcmR3YXJlL2Nh Y2hlLWF1cm9yYS1sMi5oCmluZGV4IGRjNWM0NzllYzRjMy4uMzk3NjlmZmEwMDUxIDEwMDY0NAot LS0gYS9hcmNoL2FybS9pbmNsdWRlL2FzbS9oYXJkd2FyZS9jYWNoZS1hdXJvcmEtbDIuaAorKysg Yi9hcmNoL2FybS9pbmNsdWRlL2FzbS9oYXJkd2FyZS9jYWNoZS1hdXJvcmEtbDIuaApAQCAtMzEs NiArMzEsOSBAQAogI2RlZmluZSBBVVJPUkFfQUNSX1JFUExBQ0VNRU5UX1RZUEVfU0VNSVBMUlUg XAogCSgzIDw8IEFVUk9SQV9BQ1JfUkVQTEFDRU1FTlRfT0ZGU0VUKQogCisjZGVmaW5lIEFVUk9S QV9BQ1JfUEFSSVRZX0VOCSgxIDw8IDIxKQorI2RlZmluZSBBVVJPUkFfQUNSX0VDQ19FTgkoMSA8 PCAyMCkKKwogI2RlZmluZSBBVVJPUkFfQUNSX0ZPUkNFX1dSSVRFX1BPTElDWV9PRkZTRVQJMAog I2RlZmluZSBBVVJPUkFfQUNSX0ZPUkNFX1dSSVRFX1BPTElDWV9NQVNLCVwKIAkoMHgzIDw8IEFV Uk9SQV9BQ1JfRk9SQ0VfV1JJVEVfUE9MSUNZX09GRlNFVCkKQEAgLTQxLDYgKzQ0LDUxIEBACiAj ZGVmaW5lIEFVUk9SQV9BQ1JfRk9SQ0VfV1JJVEVfVEhST19QT0xJQ1kJXAogCSgyIDw8IEFVUk9S QV9BQ1JfRk9SQ0VfV1JJVEVfUE9MSUNZX09GRlNFVCkKIAorI2RlZmluZSBBVVJPUkFfRVJSX0NO VF9SRUcgICAgICAgICAgMHg2MDAKKyNkZWZpbmUgQVVST1JBX0VSUl9BVFRSX0NBUF9SRUcgICAg IDB4NjA4CisjZGVmaW5lIEFVUk9SQV9FUlJfQUREUl9DQVBfUkVHICAgICAweDYwYworI2RlZmlu ZSBBVVJPUkFfRVJSX1dBWV9DQVBfUkVHICAgICAgMHg2MTAKKyNkZWZpbmUgQVVST1JBX0VSUl9J TkpFQ1RfQ1RMX1JFRyAgIDB4NjE0CisjZGVmaW5lIEFVUk9SQV9FUlJfSU5KRUNUX01BU0tfUkVH ICAweDYxOAorCisjZGVmaW5lIEFVUk9SQV9FUlJfQ05UX0NMUl9PRkZTRVQgICAgICAgICAzMQor I2RlZmluZSBBVVJPUkFfRVJSX0NOVF9DTFIJCSAgIFwKKwkoMHgxIDw8IEFVUk9SQV9FUlJfQ05U X0NMUl9PRkZTRVQpCisjZGVmaW5lIEFVUk9SQV9FUlJfQ05UX1VFX09GRlNFVCAgICAgICAgICAx NgorI2RlZmluZSBBVVJPUkFfRVJSX0NOVF9VRV9NQVNLICAgICAgICAgICAgIFwKKwkoMHg3ZmZm IDw8IEFVUk9SQV9FUlJfQ05UX1VFX09GRlNFVCkKKyNkZWZpbmUgQVVST1JBX0VSUl9DTlRfQ0Vf T0ZGU0VUICAgICAgICAgICAwCisjZGVmaW5lIEFVUk9SQV9FUlJfQ05UX0NFX01BU0sgICAgICAg ICAgICAgXAorCSgweGZmZmYgPDwgQVVST1JBX0VSUl9DTlRfQ0VfT0ZGU0VUKQorCisjZGVmaW5l IEFVUk9SQV9FUlJfQVRUUl9TUkNfT0ZGICAgICAgICAgICAxNgorI2RlZmluZSBBVVJPUkFfRVJS X0FUVFJfU1JDX01TSyAgICAgICAgICAgIFwKKwkoMHg3IDw8IEFVUk9SQV9FUlJfQVRUUl9TUkNf T0ZGKQorI2RlZmluZSBBVVJPUkFfRVJSX0FUVFJfVFhOX09GRiAgICAgICAgICAgMTIKKyNkZWZp bmUgQVVST1JBX0VSUl9BVFRSX1RYTl9NU0sgICAgICAgICAgICBcCisJKDB4ZiA8PCBBVVJPUkFf RVJSX0FUVFJfVFhOX09GRikKKyNkZWZpbmUgQVVST1JBX0VSUl9BVFRSX0VSUl9PRkYgICAgICAg ICAgICA4CisjZGVmaW5lIEFVUk9SQV9FUlJfQVRUUl9FUlJfTVNLICAgICAgICAgICAgXAorCSgw eDMgPDwgQVVST1JBX0VSUl9BVFRSX0VSUl9PRkYpCisjZGVmaW5lIEFVUk9SQV9FUlJfQVRUUl9D QVBfVkFMSURfT0ZGICAgICAgMAorI2RlZmluZSBBVVJPUkFfRVJSX0FUVFJfQ0FQX1ZBTElEICAg ICAgICAgIFwKKwkoMHgxIDw8IEFVUk9SQV9FUlJfQVRUUl9DQVBfVkFMSURfT0ZGKQorCisjZGVm aW5lIEFVUk9SQV9FUlJfQUREUl9DQVBfQUREUl9NQVNLIDB4ZmZmZmZmZTAKKworI2RlZmluZSBB VVJPUkFfRVJSX1dBWV9JRFhfT0ZGICAgICAgICAgICAgIDgKKyNkZWZpbmUgQVVST1JBX0VSUl9X QVlfSURYX01TSyAgICAgICAgICAgICBcCisJKDB4ZmZmIDw8IEFVUk9SQV9FUlJfV0FZX0lEWF9P RkYpCisjZGVmaW5lIEFVUk9SQV9FUlJfV0FZX0NBUF9XQVlfT0ZGU0VUICAgICAgMQorI2RlZmlu ZSBBVVJPUkFfRVJSX1dBWV9DQVBfV0FZX01BU0sgICAgICAgIFwKKwkoMHhmIDw8IEFVUk9SQV9F UlJfV0FZX0NBUF9XQVlfT0ZGU0VUKQorCisjZGVmaW5lIEFVUk9SQV9FUlJfSU5KRUNUX0NUTF9B RERSX01BU0sgMHhmZmZmZmZmMAorI2RlZmluZSBBVVJPUkFfRVJSX0FUVFJfVFhOX09GRiAgIDEy CisjZGVmaW5lIEFVUk9SQV9FUlJfSU5KRUNUX0NUTF9FTl9NQVNLICAgICAgICAgIDB4MworI2Rl ZmluZSBBVVJPUkFfRVJSX0lOSkVDVF9DVExfRU5fUEFSSVRZICAgICAgICAweDIKKyNkZWZpbmUg QVVST1JBX0VSUl9JTkpFQ1RfQ1RMX0VOX0VDQyAgICAgICAgICAgMHgxCisKICNkZWZpbmUgQVVS T1JBX01BWF9SQU5HRV9TSVpFCTEwMjQKIAogI2RlZmluZSBBVVJPUkFfV0FZX1NJWkVfU0hJRlQJ Mgo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: chris.packham@alliedtelesis.co.nz (Chris Packham) Date: Fri, 9 Nov 2018 20:03:43 +1300 Subject: [PATCH v6 3/9] ARM: aurora-l2: add defines for parity and ECC registers In-Reply-To: <20181109070349.20464-1-chris.packham@alliedtelesis.co.nz> References: <20181109070349.20464-1-chris.packham@alliedtelesis.co.nz> Message-ID: <20181109070349.20464-4-chris.packham@alliedtelesis.co.nz> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org From: Jan Luebbe These defines will be used by subsequent patches to add support for the parity check and error correction functionality in the Aurora L2 cache controller. Signed-off-by: Jan Luebbe Signed-off-by: Chris Packham --- .../include/asm/hardware/cache-aurora-l2.h | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm/include/asm/hardware/cache-aurora-l2.h b/arch/arm/include/asm/hardware/cache-aurora-l2.h index dc5c479ec4c3..39769ffa0051 100644 --- a/arch/arm/include/asm/hardware/cache-aurora-l2.h +++ b/arch/arm/include/asm/hardware/cache-aurora-l2.h @@ -31,6 +31,9 @@ #define AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU \ (3 << AURORA_ACR_REPLACEMENT_OFFSET) +#define AURORA_ACR_PARITY_EN (1 << 21) +#define AURORA_ACR_ECC_EN (1 << 20) + #define AURORA_ACR_FORCE_WRITE_POLICY_OFFSET 0 #define AURORA_ACR_FORCE_WRITE_POLICY_MASK \ (0x3 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET) @@ -41,6 +44,51 @@ #define AURORA_ACR_FORCE_WRITE_THRO_POLICY \ (2 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET) +#define AURORA_ERR_CNT_REG 0x600 +#define AURORA_ERR_ATTR_CAP_REG 0x608 +#define AURORA_ERR_ADDR_CAP_REG 0x60c +#define AURORA_ERR_WAY_CAP_REG 0x610 +#define AURORA_ERR_INJECT_CTL_REG 0x614 +#define AURORA_ERR_INJECT_MASK_REG 0x618 + +#define AURORA_ERR_CNT_CLR_OFFSET 31 +#define AURORA_ERR_CNT_CLR \ + (0x1 << AURORA_ERR_CNT_CLR_OFFSET) +#define AURORA_ERR_CNT_UE_OFFSET 16 +#define AURORA_ERR_CNT_UE_MASK \ + (0x7fff << AURORA_ERR_CNT_UE_OFFSET) +#define AURORA_ERR_CNT_CE_OFFSET 0 +#define AURORA_ERR_CNT_CE_MASK \ + (0xffff << AURORA_ERR_CNT_CE_OFFSET) + +#define AURORA_ERR_ATTR_SRC_OFF 16 +#define AURORA_ERR_ATTR_SRC_MSK \ + (0x7 << AURORA_ERR_ATTR_SRC_OFF) +#define AURORA_ERR_ATTR_TXN_OFF 12 +#define AURORA_ERR_ATTR_TXN_MSK \ + (0xf << AURORA_ERR_ATTR_TXN_OFF) +#define AURORA_ERR_ATTR_ERR_OFF 8 +#define AURORA_ERR_ATTR_ERR_MSK \ + (0x3 << AURORA_ERR_ATTR_ERR_OFF) +#define AURORA_ERR_ATTR_CAP_VALID_OFF 0 +#define AURORA_ERR_ATTR_CAP_VALID \ + (0x1 << AURORA_ERR_ATTR_CAP_VALID_OFF) + +#define AURORA_ERR_ADDR_CAP_ADDR_MASK 0xffffffe0 + +#define AURORA_ERR_WAY_IDX_OFF 8 +#define AURORA_ERR_WAY_IDX_MSK \ + (0xfff << AURORA_ERR_WAY_IDX_OFF) +#define AURORA_ERR_WAY_CAP_WAY_OFFSET 1 +#define AURORA_ERR_WAY_CAP_WAY_MASK \ + (0xf << AURORA_ERR_WAY_CAP_WAY_OFFSET) + +#define AURORA_ERR_INJECT_CTL_ADDR_MASK 0xfffffff0 +#define AURORA_ERR_ATTR_TXN_OFF 12 +#define AURORA_ERR_INJECT_CTL_EN_MASK 0x3 +#define AURORA_ERR_INJECT_CTL_EN_PARITY 0x2 +#define AURORA_ERR_INJECT_CTL_EN_ECC 0x1 + #define AURORA_MAX_RANGE_SIZE 1024 #define AURORA_WAY_SIZE_SHIFT 2 -- 2.19.1