From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40029) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gM8eI-0004xz-EU for qemu-devel@nongnu.org; Mon, 12 Nov 2018 04:36:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gM8eF-000780-6y for qemu-devel@nongnu.org; Mon, 12 Nov 2018 04:36:50 -0500 Received: from mx1.redhat.com ([209.132.183.28]:33502) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gM8eE-00075e-TP for qemu-devel@nongnu.org; Mon, 12 Nov 2018 04:36:47 -0500 Date: Mon, 12 Nov 2018 17:36:38 +0800 From: Peter Xu Message-ID: <20181112093638.GG20675@xz-x1> References: <1541764187-10732-1-git-send-email-yu.c.zhang@linux.intel.com> <1541764187-10732-4-git-send-email-yu.c.zhang@linux.intel.com> <20181112085121.GD20675@xz-x1> <20181112092548.4rnr56lw6zgzmfwh@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20181112092548.4rnr56lw6zgzmfwh@linux.intel.com> Subject: Re: [Qemu-devel] [PATCH v1 3/3] intel-iommu: search iotlb for levels supported by the address width. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Yu Zhang Cc: Eduardo Habkost , "Michael S. Tsirkin" , qemu-devel@nongnu.org, Paolo Bonzini , Richard Henderson On Mon, Nov 12, 2018 at 05:25:48PM +0800, Yu Zhang wrote: > On Mon, Nov 12, 2018 at 04:51:22PM +0800, Peter Xu wrote: > > On Fri, Nov 09, 2018 at 07:49:47PM +0800, Yu Zhang wrote: > > > This patch updates vtd_lookup_iotlb() to search cached mappings only > > > for all page levels supported by address width of current vIOMMU. Also, > > > to cover 57-bit width, the shift of source id(VTD_IOTLB_SID_SHIFT) and > > > of page level(VTD_IOTLB_LVL_SHIFT) are enlarged by 9 - the stride of > > > one paging structure level. > > > > > > Signed-off-by: Yu Zhang > > > --- > > > Cc: "Michael S. Tsirkin" > > > Cc: Marcel Apfelbaum > > > Cc: Paolo Bonzini > > > Cc: Richard Henderson > > > Cc: Eduardo Habkost > > > Cc: Peter Xu > > > --- > > > hw/i386/intel_iommu.c | 5 +++-- > > > hw/i386/intel_iommu_internal.h | 7 ++----- > > > 2 files changed, 5 insertions(+), 7 deletions(-) > > > > > > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c > > > index 9cdf755..ce7e17e 100644 > > > --- a/hw/i386/intel_iommu.c > > > +++ b/hw/i386/intel_iommu.c > > > @@ -254,11 +254,12 @@ static uint64_t vtd_get_iotlb_gfn(hwaddr addr, uint32_t level) > > > static VTDIOTLBEntry *vtd_lookup_iotlb(IntelIOMMUState *s, uint16_t source_id, > > > hwaddr addr) > > > { > > > - VTDIOTLBEntry *entry; > > > + VTDIOTLBEntry *entry = NULL; > > > uint64_t key; > > > int level; > > > + int max_level = (s->aw_bits - VTD_PAGE_SHIFT_4K) / VTD_SL_LEVEL_BITS; > > > > > > - for (level = VTD_SL_PT_LEVEL; level < VTD_SL_PML4_LEVEL; level++) { > > > + for (level = VTD_SL_PT_LEVEL; level < max_level; level++) { > > > > My understanding of current IOTLB is that it only caches the last > > level of mapping, say: > > > > - level 1: 4K page > > - level 2: 2M page > > - level 3: 1G page > > > > So we don't check against level=4 even if x-aw-bits=48 is specified. > > > > Here does it mean that we're going to have... 512G iommu huge pages? > > > > No. My bad, I misunderstood this routine. And now I believe we do not > need this patch. :-) Yeah good to confirm that :-) Regards, -- Peter Xu