[PATCH 0/3] Make STM32 interrupt controller use hwspinlock

[PATCH 0/3] Make STM32 interrupt controller use hwspinlock

[Benjamin Gaignard]

This series allow to protect STM32 interrupt controller configuration registers
with a hwspinlock to avoid conflicting accesses between processors. 

Benjamin Gaignard (3):
  dt-bindings: interrupt-controller: stm32: Document hwlock properties
  irqchip: stm32: protect configuration registers with hwspinlock
  ARM: dts: stm32: Add hwlock for irqchip on stm32mp157

 .../interrupt-controller/st,stm32-exti.txt         |  4 +++
 arch/arm/boot/dts/stm32mp157c.dtsi                 |  1 +
 drivers/irqchip/irq-stm32-exti.c                   | 36 ++++++++++++++++++----
 3 files changed, 35 insertions(+), 6 deletions(-)

-- 
2.15.0

[PATCH 0/3] Make STM32 interrupt controller use hwspinlock

[Benjamin Gaignard]

This series allow to protect STM32 interrupt controller configuration registers
with a hwspinlock to avoid conflicting accesses between processors. 

Benjamin Gaignard (3):
  dt-bindings: interrupt-controller: stm32: Document hwlock properties
  irqchip: stm32: protect configuration registers with hwspinlock
  ARM: dts: stm32: Add hwlock for irqchip on stm32mp157

 .../interrupt-controller/st,stm32-exti.txt         |  4 +++
 arch/arm/boot/dts/stm32mp157c.dtsi                 |  1 +
 drivers/irqchip/irq-stm32-exti.c                   | 36 ++++++++++++++++++----
 3 files changed, 35 insertions(+), 6 deletions(-)

-- 
2.15.0

[PATCH 1/3] dt-bindings: interrupt-controller: stm32: Document hwlock properties

[Benjamin Gaignard]

Add hwlocks as optional property

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
---
 .../devicetree/bindings/interrupt-controller/st,stm32-exti.txt        | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
index 6a36bf66d932..cd01b2292ec6 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
@@ -14,6 +14,10 @@ Required properties:
   (only needed for exti controller with multiple exti under
   same parent interrupt: st,stm32-exti and st,stm32h7-exti)
 
+Optional properties:
+
+- hwlocks: reference to a phandle of a hardware spinlock provider node.
+
 Example:
 
 exti: interrupt-controller@40013c00 {
-- 
2.15.0

[PATCH 1/3] dt-bindings: interrupt-controller: stm32: Document hwlock properties

[Benjamin Gaignard]

Add hwlocks as optional property

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
---
 .../devicetree/bindings/interrupt-controller/st,stm32-exti.txt        | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
index 6a36bf66d932..cd01b2292ec6 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
@@ -14,6 +14,10 @@ Required properties:
   (only needed for exti controller with multiple exti under
   same parent interrupt: st,stm32-exti and st,stm32h7-exti)
 
+Optional properties:
+
+- hwlocks: reference to a phandle of a hardware spinlock provider node.
+
 Example:
 
 exti: interrupt-controller at 40013c00 {
-- 
2.15.0

[PATCH 2/3] irqchip: stm32: protect configuration registers with hwspinlock

[Benjamin Gaignard]

If a hwspinlock is defined in device tree use it to protect
configuration registers.

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
---
 drivers/irqchip/irq-stm32-exti.c | 36 ++++++++++++++++++++++++++++++------
 1 file changed, 30 insertions(+), 6 deletions(-)

diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
index 0a2088e12d96..a010a2eed078 100644
--- a/drivers/irqchip/irq-stm32-exti.c
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -6,6 +6,7 @@
  */
 
 #include <linux/bitops.h>
+#include <linux/hwspinlock.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/irq.h>
@@ -20,6 +21,8 @@
 
 #define IRQS_PER_BANK 32
 
+#define HWSPINLOCK_TIMEOUT	5 /* msec */
+
 struct stm32_exti_bank {
 	u32 imr_ofst;
 	u32 emr_ofst;
@@ -47,6 +50,7 @@ struct stm32_exti_drv_data {
 struct stm32_exti_chip_data {
 	struct stm32_exti_host_data *host_data;
 	const struct stm32_exti_bank *reg_bank;
+	struct hwspinlock *hwlock;
 	struct raw_spinlock rlock;
 	u32 wake_active;
 	u32 mask_cache;
@@ -275,25 +279,34 @@ static int stm32_irq_set_type(struct irq_data *d, unsigned int type)
 	struct stm32_exti_chip_data *chip_data = gc->private;
 	const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
 	u32 rtsr, ftsr;
-	int err;
+	int err = 0;
 
 	irq_gc_lock(gc);
 
+	if (chip_data->hwlock)
+		err = hwspin_lock_timeout(chip_data->hwlock,
+					  HWSPINLOCK_TIMEOUT);
+
+	if (err)
+		goto unlock;
+
 	rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst);
 	ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst);
 
 	err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
-	if (err) {
-		irq_gc_unlock(gc);
-		return err;
-	}
+	if (err)
+		goto unspinlock;
 
 	irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst);
 	irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst);
 
+unspinlock:
+	if (chip_data->hwlock)
+		hwspin_unlock(chip_data->hwlock);
+unlock:
 	irq_gc_unlock(gc);
 
-	return 0;
+	return err;
 }
 
 static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data,
@@ -670,6 +683,7 @@ static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data,
 	int nr_irqs, ret, i;
 	struct irq_chip_generic *gc;
 	struct irq_domain *domain;
+	struct hwspinlock *hwlock = NULL;
 
 	host_data = stm32_exti_host_init(drv_data, node);
 	if (!host_data)
@@ -692,12 +706,22 @@ static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data,
 		goto out_free_domain;
 	}
 
+	/* hwspinlock is optional */
+	ret = of_hwspin_lock_get_id(node, 0);
+	if (ret < 0) {
+		if (ret == -EPROBE_DEFER)
+			goto out_free_domain;
+	} else {
+		hwlock = hwspin_lock_request_specific(ret);
+	}
+
 	for (i = 0; i < drv_data->bank_nr; i++) {
 		const struct stm32_exti_bank *stm32_bank;
 		struct stm32_exti_chip_data *chip_data;
 
 		stm32_bank = drv_data->exti_banks[i];
 		chip_data = stm32_exti_chip_init(host_data, i, node);
+		chip_data->hwlock = hwlock;
 
 		gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK);
 
-- 
2.15.0

[PATCH 2/3] irqchip: stm32: protect configuration registers with hwspinlock

[Benjamin Gaignard]

If a hwspinlock is defined in device tree use it to protect
configuration registers.

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
---
 drivers/irqchip/irq-stm32-exti.c | 36 ++++++++++++++++++++++++++++++------
 1 file changed, 30 insertions(+), 6 deletions(-)

diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
index 0a2088e12d96..a010a2eed078 100644
--- a/drivers/irqchip/irq-stm32-exti.c
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -6,6 +6,7 @@
  */
 
 #include <linux/bitops.h>
+#include <linux/hwspinlock.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/irq.h>
@@ -20,6 +21,8 @@
 
 #define IRQS_PER_BANK 32
 
+#define HWSPINLOCK_TIMEOUT	5 /* msec */
+
 struct stm32_exti_bank {
 	u32 imr_ofst;
 	u32 emr_ofst;
@@ -47,6 +50,7 @@ struct stm32_exti_drv_data {
 struct stm32_exti_chip_data {
 	struct stm32_exti_host_data *host_data;
 	const struct stm32_exti_bank *reg_bank;
+	struct hwspinlock *hwlock;
 	struct raw_spinlock rlock;
 	u32 wake_active;
 	u32 mask_cache;
@@ -275,25 +279,34 @@ static int stm32_irq_set_type(struct irq_data *d, unsigned int type)
 	struct stm32_exti_chip_data *chip_data = gc->private;
 	const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
 	u32 rtsr, ftsr;
-	int err;
+	int err = 0;
 
 	irq_gc_lock(gc);
 
+	if (chip_data->hwlock)
+		err = hwspin_lock_timeout(chip_data->hwlock,
+					  HWSPINLOCK_TIMEOUT);
+
+	if (err)
+		goto unlock;
+
 	rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst);
 	ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst);
 
 	err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
-	if (err) {
-		irq_gc_unlock(gc);
-		return err;
-	}
+	if (err)
+		goto unspinlock;
 
 	irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst);
 	irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst);
 
+unspinlock:
+	if (chip_data->hwlock)
+		hwspin_unlock(chip_data->hwlock);
+unlock:
 	irq_gc_unlock(gc);
 
-	return 0;
+	return err;
 }
 
 static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data,
@@ -670,6 +683,7 @@ static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data,
 	int nr_irqs, ret, i;
 	struct irq_chip_generic *gc;
 	struct irq_domain *domain;
+	struct hwspinlock *hwlock = NULL;
 
 	host_data = stm32_exti_host_init(drv_data, node);
 	if (!host_data)
@@ -692,12 +706,22 @@ static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data,
 		goto out_free_domain;
 	}
 
+	/* hwspinlock is optional */
+	ret = of_hwspin_lock_get_id(node, 0);
+	if (ret < 0) {
+		if (ret == -EPROBE_DEFER)
+			goto out_free_domain;
+	} else {
+		hwlock = hwspin_lock_request_specific(ret);
+	}
+
 	for (i = 0; i < drv_data->bank_nr; i++) {
 		const struct stm32_exti_bank *stm32_bank;
 		struct stm32_exti_chip_data *chip_data;
 
 		stm32_bank = drv_data->exti_banks[i];
 		chip_data = stm32_exti_chip_init(host_data, i, node);
+		chip_data->hwlock = hwlock;
 
 		gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK);
 
-- 
2.15.0

[PATCH 3/3] ARM: dts: stm32: Add hwlock for irqchip on stm32mp157

[Benjamin Gaignard]

Define a hwspinlock to be used by irq controller

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
---
 arch/arm/boot/dts/stm32mp157c.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi
index 98f824d8b0f0..7c9ee32b775d 100644
--- a/arch/arm/boot/dts/stm32mp157c.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c.dtsi
@@ -824,6 +824,7 @@
 			interrupt-controller;
 			#interrupt-cells = <2>;
 			reg = <0x5000d000 0x400>;
+			hwlocks = <&hsem 0>;
 		};
 
 		syscfg: syscon@50020000 {
-- 
2.15.0

[PATCH 3/3] ARM: dts: stm32: Add hwlock for irqchip on stm32mp157

[Benjamin Gaignard]

Define a hwspinlock to be used by irq controller

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
---
 arch/arm/boot/dts/stm32mp157c.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi
index 98f824d8b0f0..7c9ee32b775d 100644
--- a/arch/arm/boot/dts/stm32mp157c.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c.dtsi
@@ -824,6 +824,7 @@
 			interrupt-controller;
 			#interrupt-cells = <2>;
 			reg = <0x5000d000 0x400>;
+			hwlocks = <&hsem 0>;
 		};
 
 		syscfg: syscon at 50020000 {
-- 
2.15.0

Re: [PATCH 1/3] dt-bindings: interrupt-controller: stm32: Document hwlock properties

[Rob Herring]

On Tue, Nov 13, 2018 at 03:48:03PM +0100, Benjamin Gaignard wrote:
> Add hwlocks as optional property
> 
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>

Should be linaro.org S-o-b?

> ---
>  .../devicetree/bindings/interrupt-controller/st,stm32-exti.txt        | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
> index 6a36bf66d932..cd01b2292ec6 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
> +++ b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
> @@ -14,6 +14,10 @@ Required properties:
>    (only needed for exti controller with multiple exti under
>    same parent interrupt: st,stm32-exti and st,stm32h7-exti)
>  
> +Optional properties:
> +
> +- hwlocks: reference to a phandle of a hardware spinlock provider node.
> +
>  Example:
>  
>  exti: interrupt-controller@40013c00 {
> -- 
> 2.15.0
> 

Re: [PATCH 1/3] dt-bindings: interrupt-controller: stm32: Document hwlock properties

[Rob Herring]

On Tue, Nov 13, 2018 at 03:48:03PM +0100, Benjamin Gaignard wrote:
> Add hwlocks as optional property
> 
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>

Should be linaro.org S-o-b?

> ---
>  .../devicetree/bindings/interrupt-controller/st,stm32-exti.txt        | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
> index 6a36bf66d932..cd01b2292ec6 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
> +++ b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
> @@ -14,6 +14,10 @@ Required properties:
>    (only needed for exti controller with multiple exti under
>    same parent interrupt: st,stm32-exti and st,stm32h7-exti)
>  
> +Optional properties:
> +
> +- hwlocks: reference to a phandle of a hardware spinlock provider node.
> +
>  Example:
>  
>  exti: interrupt-controller@40013c00 {
> -- 
> 2.15.0
> 

_______________________________________________
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linux-arm-kernel@lists.infradead.org
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Re: [PATCH 2/3] irqchip: stm32: protect configuration registers with hwspinlock

[Marc Zyngier]

On 13/11/2018 14:48, Benjamin Gaignard wrote:
> If a hwspinlock is defined in device tree use it to protect
> configuration registers.
> 
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
> ---
>  drivers/irqchip/irq-stm32-exti.c | 36 ++++++++++++++++++++++++++++++------
>  1 file changed, 30 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
> index 0a2088e12d96..a010a2eed078 100644
> --- a/drivers/irqchip/irq-stm32-exti.c
> +++ b/drivers/irqchip/irq-stm32-exti.c
> @@ -6,6 +6,7 @@
>   */
>  
>  #include <linux/bitops.h>
> +#include <linux/hwspinlock.h>
>  #include <linux/interrupt.h>
>  #include <linux/io.h>
>  #include <linux/irq.h>
> @@ -20,6 +21,8 @@
>  
>  #define IRQS_PER_BANK 32
>  
> +#define HWSPINLOCK_TIMEOUT	5 /* msec */
> +
>  struct stm32_exti_bank {
>  	u32 imr_ofst;
>  	u32 emr_ofst;
> @@ -47,6 +50,7 @@ struct stm32_exti_drv_data {
>  struct stm32_exti_chip_data {
>  	struct stm32_exti_host_data *host_data;
>  	const struct stm32_exti_bank *reg_bank;
> +	struct hwspinlock *hwlock;
>  	struct raw_spinlock rlock;
>  	u32 wake_active;
>  	u32 mask_cache;
> @@ -275,25 +279,34 @@ static int stm32_irq_set_type(struct irq_data *d, unsigned int type)
>  	struct stm32_exti_chip_data *chip_data = gc->private;
>  	const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
>  	u32 rtsr, ftsr;
> -	int err;
> +	int err = 0;
>  
>  	irq_gc_lock(gc);
>  
> +	if (chip_data->hwlock)
> +		err = hwspin_lock_timeout(chip_data->hwlock,
> +					  HWSPINLOCK_TIMEOUT);
> +
> +	if (err)
> +		goto unlock;
> +
>  	rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst);
>  	ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst);
>  
>  	err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
> -	if (err) {
> -		irq_gc_unlock(gc);
> -		return err;
> -	}
> +	if (err)
> +		goto unspinlock;
>  
>  	irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst);
>  	irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst);
>  
> +unspinlock:
> +	if (chip_data->hwlock)
> +		hwspin_unlock(chip_data->hwlock);
> +unlock:
>  	irq_gc_unlock(gc);
>  
> -	return 0;
> +	return err;
>  }
>  
>  static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data,
> @@ -670,6 +683,7 @@ static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data,
>  	int nr_irqs, ret, i;
>  	struct irq_chip_generic *gc;
>  	struct irq_domain *domain;
> +	struct hwspinlock *hwlock = NULL;
>  
>  	host_data = stm32_exti_host_init(drv_data, node);
>  	if (!host_data)
> @@ -692,12 +706,22 @@ static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data,
>  		goto out_free_domain;
>  	}
>  
> +	/* hwspinlock is optional */
> +	ret = of_hwspin_lock_get_id(node, 0);
> +	if (ret < 0) {
> +		if (ret == -EPROBE_DEFER)
> +			goto out_free_domain;

Wouldn't it make sense to probe for this before allocating the domain?

> +	} else {
> +		hwlock = hwspin_lock_request_specific(ret);
> +	}
> +
>  	for (i = 0; i < drv_data->bank_nr; i++) {
>  		const struct stm32_exti_bank *stm32_bank;
>  		struct stm32_exti_chip_data *chip_data;
>  
>  		stm32_bank = drv_data->exti_banks[i];
>  		chip_data = stm32_exti_chip_init(host_data, i, node);
> +		chip_data->hwlock = hwlock;
>  
>  		gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK);
>  
> 

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

Re: [PATCH 2/3] irqchip: stm32: protect configuration registers with hwspinlock

[Marc Zyngier]

On 13/11/2018 14:48, Benjamin Gaignard wrote:
> If a hwspinlock is defined in device tree use it to protect
> configuration registers.
> 
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
> ---
>  drivers/irqchip/irq-stm32-exti.c | 36 ++++++++++++++++++++++++++++++------
>  1 file changed, 30 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
> index 0a2088e12d96..a010a2eed078 100644
> --- a/drivers/irqchip/irq-stm32-exti.c
> +++ b/drivers/irqchip/irq-stm32-exti.c
> @@ -6,6 +6,7 @@
>   */
>  
>  #include <linux/bitops.h>
> +#include <linux/hwspinlock.h>
>  #include <linux/interrupt.h>
>  #include <linux/io.h>
>  #include <linux/irq.h>
> @@ -20,6 +21,8 @@
>  
>  #define IRQS_PER_BANK 32
>  
> +#define HWSPINLOCK_TIMEOUT	5 /* msec */
> +
>  struct stm32_exti_bank {
>  	u32 imr_ofst;
>  	u32 emr_ofst;
> @@ -47,6 +50,7 @@ struct stm32_exti_drv_data {
>  struct stm32_exti_chip_data {
>  	struct stm32_exti_host_data *host_data;
>  	const struct stm32_exti_bank *reg_bank;
> +	struct hwspinlock *hwlock;
>  	struct raw_spinlock rlock;
>  	u32 wake_active;
>  	u32 mask_cache;
> @@ -275,25 +279,34 @@ static int stm32_irq_set_type(struct irq_data *d, unsigned int type)
>  	struct stm32_exti_chip_data *chip_data = gc->private;
>  	const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
>  	u32 rtsr, ftsr;
> -	int err;
> +	int err = 0;
>  
>  	irq_gc_lock(gc);
>  
> +	if (chip_data->hwlock)
> +		err = hwspin_lock_timeout(chip_data->hwlock,
> +					  HWSPINLOCK_TIMEOUT);
> +
> +	if (err)
> +		goto unlock;
> +
>  	rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst);
>  	ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst);
>  
>  	err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
> -	if (err) {
> -		irq_gc_unlock(gc);
> -		return err;
> -	}
> +	if (err)
> +		goto unspinlock;
>  
>  	irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst);
>  	irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst);
>  
> +unspinlock:
> +	if (chip_data->hwlock)
> +		hwspin_unlock(chip_data->hwlock);
> +unlock:
>  	irq_gc_unlock(gc);
>  
> -	return 0;
> +	return err;
>  }
>  
>  static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data,
> @@ -670,6 +683,7 @@ static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data,
>  	int nr_irqs, ret, i;
>  	struct irq_chip_generic *gc;
>  	struct irq_domain *domain;
> +	struct hwspinlock *hwlock = NULL;
>  
>  	host_data = stm32_exti_host_init(drv_data, node);
>  	if (!host_data)
> @@ -692,12 +706,22 @@ static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data,
>  		goto out_free_domain;
>  	}
>  
> +	/* hwspinlock is optional */
> +	ret = of_hwspin_lock_get_id(node, 0);
> +	if (ret < 0) {
> +		if (ret == -EPROBE_DEFER)
> +			goto out_free_domain;

Wouldn't it make sense to probe for this before allocating the domain?

> +	} else {
> +		hwlock = hwspin_lock_request_specific(ret);
> +	}
> +
>  	for (i = 0; i < drv_data->bank_nr; i++) {
>  		const struct stm32_exti_bank *stm32_bank;
>  		struct stm32_exti_chip_data *chip_data;
>  
>  		stm32_bank = drv_data->exti_banks[i];
>  		chip_data = stm32_exti_chip_init(host_data, i, node);
> +		chip_data->hwlock = hwlock;
>  
>  		gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK);
>  
> 

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

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Re: [PATCH 1/3] dt-bindings: interrupt-controller: stm32: Document hwlock properties

[Marc Zyngier]

On 04/12/2018 20:47, Rob Herring wrote:
> On Tue, Nov 13, 2018 at 03:48:03PM +0100, Benjamin Gaignard wrote:
>> Add hwlocks as optional property
>>
>> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
> 
> Should be linaro.org S-o-b?

What is the status on this? I'm not going to queue it if there is a
doubt on the SoB...

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

Re: [PATCH 1/3] dt-bindings: interrupt-controller: stm32: Document hwlock properties

[Marc Zyngier]

On 04/12/2018 20:47, Rob Herring wrote:
> On Tue, Nov 13, 2018 at 03:48:03PM +0100, Benjamin Gaignard wrote:
>> Add hwlocks as optional property
>>
>> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
> 
> Should be linaro.org S-o-b?

What is the status on this? I'm not going to queue it if there is a
doubt on the SoB...

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

_______________________________________________
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Re: [PATCH 1/3] dt-bindings: interrupt-controller: stm32: Document hwlock properties

[Benjamin Gaignard]

Le jeu. 13 déc. 2018 à 15:23, Marc Zyngier <marc.zyngier@arm.com> a écrit :
>
> On 04/12/2018 20:47, Rob Herring wrote:
> > On Tue, Nov 13, 2018 at 03:48:03PM +0100, Benjamin Gaignard wrote:
> >> Add hwlocks as optional property
> >>
> >> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
> >
> > Should be linaro.org S-o-b?
>
> What is the status on this? I'm not going to queue it if there is a
> doubt on the SoB...

I will fix that in version 2 (even if I don't really understand the issue)

Benjamin
>
> Thanks,
>
>         M.
> --
> Jazz is not dead. It just smells funny...



-- 
Benjamin Gaignard

Graphic Study Group

Linaro.org │ Open source software for ARM SoCs

Follow Linaro: Facebook | Twitter | Blog

Re: [PATCH 1/3] dt-bindings: interrupt-controller: stm32: Document hwlock properties

[Benjamin Gaignard]

Le jeu. 13 déc. 2018 à 15:23, Marc Zyngier <marc.zyngier@arm.com> a écrit :
>
> On 04/12/2018 20:47, Rob Herring wrote:
> > On Tue, Nov 13, 2018 at 03:48:03PM +0100, Benjamin Gaignard wrote:
> >> Add hwlocks as optional property
> >>
> >> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
> >
> > Should be linaro.org S-o-b?
>
> What is the status on this? I'm not going to queue it if there is a
> doubt on the SoB...

I will fix that in version 2 (even if I don't really understand the issue)

Benjamin
>
> Thanks,
>
>         M.
> --
> Jazz is not dead. It just smells funny...



-- 
Benjamin Gaignard

Graphic Study Group

Linaro.org │ Open source software for ARM SoCs

Follow Linaro: Facebook | Twitter | Blog

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Re: [PATCH 1/3] dt-bindings: interrupt-controller: stm32: Document hwlock properties

[Marc Zyngier]

On Thu, 13 Dec 2018 14:55:06 +0000,
Benjamin Gaignard <benjamin.gaignard@linaro.org> wrote:
> 
> Le jeu. 13 déc. 2018 à 15:23, Marc Zyngier <marc.zyngier@arm.com> a écrit :
> >
> > On 04/12/2018 20:47, Rob Herring wrote:
> > > On Tue, Nov 13, 2018 at 03:48:03PM +0100, Benjamin Gaignard wrote:
> > >> Add hwlocks as optional property
> > >>
> > >> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
> > >
> > > Should be linaro.org S-o-b?
> >
> > What is the status on this? I'm not going to queue it if there is a
> > doubt on the SoB...
> 
> I will fix that in version 2 (even if I don't really understand the
> issue)

It depends which hat you had on at the time you wrote the patches.

Thanks,

	M.

-- 
Jazz is not dead, it just smell funny.

Re: [PATCH 1/3] dt-bindings: interrupt-controller: stm32: Document hwlock properties

[Marc Zyngier]

On Thu, 13 Dec 2018 14:55:06 +0000,
Benjamin Gaignard <benjamin.gaignard@linaro.org> wrote:
> 
> Le jeu. 13 déc. 2018 à 15:23, Marc Zyngier <marc.zyngier@arm.com> a écrit :
> >
> > On 04/12/2018 20:47, Rob Herring wrote:
> > > On Tue, Nov 13, 2018 at 03:48:03PM +0100, Benjamin Gaignard wrote:
> > >> Add hwlocks as optional property
> > >>
> > >> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
> > >
> > > Should be linaro.org S-o-b?
> >
> > What is the status on this? I'm not going to queue it if there is a
> > doubt on the SoB...
> 
> I will fix that in version 2 (even if I don't really understand the
> issue)

It depends which hat you had on at the time you wrote the patches.

Thanks,

	M.

-- 
Jazz is not dead, it just smell funny.

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