From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Tue, 20 Nov 2018 13:04:05 +0100 Subject: [U-Boot] [PATCH u-boot-marvell v3 06/10] watchdog: armada_37xx: Fix compliance with kernel's driver In-Reply-To: <20181120120409.12822-1-marek.behun@nic.cz> References: <20181120120409.12822-1-marek.behun@nic.cz> Message-ID: <20181120120409.12822-6-marek.behun@nic.cz> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable To: u-boot@lists.denx.de The Armada 37xx watchdog driver was recently accepted for mainline kernel by watchdog subsystem maintainer, but the driver works a little different than the one in U-Boot. This patch fixes this. Signed-off-by: Marek Beh=C3=BAn --- drivers/watchdog/armada-37xx-wdt.c | 109 ++++++++++++++++++----------- 1 file changed, 67 insertions(+), 42 deletions(-) diff --git a/drivers/watchdog/armada-37xx-wdt.c b/drivers/watchdog/armada-3= 7xx-wdt.c index 0fa4fda4fc..91cd8a6e6a 100644 --- a/drivers/watchdog/armada-37xx-wdt.c +++ b/drivers/watchdog/armada-37xx-wdt.c @@ -22,42 +22,63 @@ struct a37xx_wdt { }; =20 /* - * We use Counter 1 for watchdog timer, because so does Marvell's Linux by - * default. + * We use Counter 1 as watchdog timer, and Counter 0 for re-triggering Cou= nter 1 */ =20 -#define CNTR_CTRL 0x10 +#define CNTR_CTRL(id) ((id) * 0x10) #define CNTR_CTRL_ENABLE 0x0001 #define CNTR_CTRL_ACTIVE 0x0002 #define CNTR_CTRL_MODE_MASK 0x000c #define CNTR_CTRL_MODE_ONESHOT 0x0000 +#define CNTR_CTRL_MODE_HWSIG 0x000c +#define CNTR_CTRL_TRIG_SRC_MASK 0x00f0 +#define CNTR_CTRL_TRIG_SRC_PREV_CNTR 0x0050 #define CNTR_CTRL_PRESCALE_MASK 0xff00 #define CNTR_CTRL_PRESCALE_MIN 2 #define CNTR_CTRL_PRESCALE_SHIFT 8 =20 -#define CNTR_COUNT_LOW 0x14 -#define CNTR_COUNT_HIGH 0x18 +#define CNTR_COUNT_LOW(id) (CNTR_CTRL(id) + 0x4) +#define CNTR_COUNT_HIGH(id) (CNTR_CTRL(id) + 0x8) =20 -static void set_counter_value(struct a37xx_wdt *priv) +static void set_counter_value(struct a37xx_wdt *priv, int id, u64 val) { - writel(priv->timeout & 0xffffffff, priv->reg + CNTR_COUNT_LOW); - writel(priv->timeout >> 32, priv->reg + CNTR_COUNT_HIGH); + writel(val & 0xffffffff, priv->reg + CNTR_COUNT_LOW(id)); + writel(val >> 32, priv->reg + CNTR_COUNT_HIGH(id)); } =20 -static void a37xx_wdt_enable(struct a37xx_wdt *priv) +static void counter_enable(struct a37xx_wdt *priv, int id) { - u32 reg =3D readl(priv->reg + CNTR_CTRL); + setbits_le32(priv->reg + CNTR_CTRL(id), CNTR_CTRL_ENABLE); +} =20 - reg |=3D CNTR_CTRL_ENABLE; - writel(reg, priv->reg + CNTR_CTRL); +static void counter_disable(struct a37xx_wdt *priv, int id) +{ + clrbits_le32(priv->reg + CNTR_CTRL(id), CNTR_CTRL_ENABLE); } =20 -static void a37xx_wdt_disable(struct a37xx_wdt *priv) +static int init_counter(struct a37xx_wdt *priv, int id, u32 mode, u32 trig= _src) { - u32 reg =3D readl(priv->reg + CNTR_CTRL); + u32 reg; + + reg =3D readl(priv->reg + CNTR_CTRL(id)); + if (reg & CNTR_CTRL_ACTIVE) + return -EBUSY; + + reg &=3D ~(CNTR_CTRL_MODE_MASK | CNTR_CTRL_PRESCALE_MASK | + CNTR_CTRL_TRIG_SRC_MASK); + + /* set mode */ + reg |=3D mode; + + /* set prescaler to the min value */ + reg |=3D CNTR_CTRL_PRESCALE_MIN << CNTR_CTRL_PRESCALE_SHIFT; + + /* set trigger source */ + reg |=3D trig_src; =20 - reg &=3D ~CNTR_CTRL_ENABLE; - writel(reg, priv->reg + CNTR_CTRL); + writel(reg, priv->reg + CNTR_CTRL(id)); + + return 0; } =20 static int a37xx_wdt_reset(struct udevice *dev) @@ -67,9 +88,9 @@ static int a37xx_wdt_reset(struct udevice *dev) if (!priv->timeout) return -EINVAL; =20 - a37xx_wdt_disable(priv); - set_counter_value(priv); - a37xx_wdt_enable(priv); + /* counter 1 is retriggered by forcing end count on counter 0 */ + counter_disable(priv, 0); + counter_enable(priv, 0); =20 return 0; } @@ -78,10 +99,14 @@ static int a37xx_wdt_expire_now(struct udevice *dev, ul= ong flags) { struct a37xx_wdt *priv =3D dev_get_priv(dev); =20 - a37xx_wdt_disable(priv); - priv->timeout =3D 0; - set_counter_value(priv); - a37xx_wdt_enable(priv); + /* first we set timeout to 0 */ + counter_disable(priv, 1); + set_counter_value(priv, 1, 0); + counter_enable(priv, 1); + + /* and then we start counter 1 by forcing end count on counter 0 */ + counter_disable(priv, 0); + counter_enable(priv, 0); =20 return 0; } @@ -89,26 +114,25 @@ static int a37xx_wdt_expire_now(struct udevice *dev, u= long flags) static int a37xx_wdt_start(struct udevice *dev, u64 ms, ulong flags) { struct a37xx_wdt *priv =3D dev_get_priv(dev); - u32 reg; - - reg =3D readl(priv->reg + CNTR_CTRL); - - if (reg & CNTR_CTRL_ACTIVE) - return -EBUSY; + int err; =20 - /* set mode */ - reg =3D (reg & ~CNTR_CTRL_MODE_MASK) | CNTR_CTRL_MODE_ONESHOT; + err =3D init_counter(priv, 0, CNTR_CTRL_MODE_ONESHOT, 0); + if (err < 0) + return err; =20 - /* set prescaler to the min value */ - reg &=3D ~CNTR_CTRL_PRESCALE_MASK; - reg |=3D CNTR_CTRL_PRESCALE_MIN << CNTR_CTRL_PRESCALE_SHIFT; + err =3D init_counter(priv, 1, CNTR_CTRL_MODE_HWSIG, + CNTR_CTRL_TRIG_SRC_PREV_CNTR); + if (err < 0) + return err; =20 priv->timeout =3D ms * priv->clk_rate / 1000 / CNTR_CTRL_PRESCALE_MIN; =20 - writel(reg, priv->reg + CNTR_CTRL); + set_counter_value(priv, 0, 0); + set_counter_value(priv, 1, priv->timeout); + counter_enable(priv, 1); =20 - set_counter_value(priv); - a37xx_wdt_enable(priv); + /* we have to force end count on counter 0 to start counter 1 */ + counter_enable(priv, 0); =20 return 0; } @@ -117,7 +141,9 @@ static int a37xx_wdt_stop(struct udevice *dev) { struct a37xx_wdt *priv =3D dev_get_priv(dev); =20 - a37xx_wdt_disable(priv); + counter_disable(priv, 1); + counter_disable(priv, 0); + writel(0, priv->sel_reg); =20 return 0; } @@ -139,11 +165,10 @@ static int a37xx_wdt_probe(struct udevice *dev) =20 priv->clk_rate =3D (ulong)get_ref_clk() * 1000000; =20 - a37xx_wdt_disable(priv); - /* - * We use timer 1 as watchdog timer (because Marvell's Linux uses that - * timer as default), therefore we only set bit TIMER1_IS_WCHDOG_TIMER. + * We use counter 1 as watchdog timer, therefore we only set bit + * TIMER1_IS_WCHDOG_TIMER. Counter 0 is only used to force re-trigger on + * counter 1. */ writel(1 << 1, priv->sel_reg); =20 --=20 2.18.1